DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 13, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on June 13, 2026. Claims 1 and 9 have been amended. No new claims have been added. No claims have been
canceled. Claims 13-18 have been withdrawn. Currently, claims 1-12 and 19-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim initially recites, “wherein the plurality of conductive patterns includes a select line and a first conductive pattern” which appears to identify the select line and the first conductive pattern as separate elements included within the plurality of conductive patterns. The claim subsequently recites, “the first conductive pattern corresponding to the select line”. This creates an ambiguity as to whether the first conductive pattern is itself the select line or whether the first conductive pattern is a separate conductive pattern that merely corresponds to the select line.
If the first conductive pattern is intended to be the select line, the earlier recitation of, “a select line and a first conductive pattern” appears to identify them as two separate elements.
Conversely, if the first conductive pattern and the select line are distinct elements, it is unclear what is meant by the first conductive pattern “corresponding to” the select line and which conductive pattern is used in determining the subsequently recited width of the channel structure.
Claim 1 defines the channel structure as comprising a first channel layer, a second channel layer and a gate insulating layer. Claim 1 further recites that, “wherein a width of the channel structure extending through the first conductive pattern corresponding to the select line is narrower than a width of the channel structure extending through the plurality of conductive patterns other than the first conductive pattern”. It is unclear what structural dimension constitutes the recited “width of the channel structure”. In the disclosure, the first channel, the second channel and the gate insulating layer do not appear to have reduced layer thickness at the select line. Rather, the narrowing appears to result from a reduction in the width of the core surrounded by the channel layers and gate insulating layer. At the select line, the channel structure includes all three layers. Through the other conductive patterns however, it includes only the first channel layer. Therefore, if the width is measured across all parts of the channel structure, the portion at the select line may be wider rather than narrower.
Claims 2-8 and 19 depend upon claims 1 and do not rectify the problem therefore, they are also rejected.
Regarding claim 9, the claim initially recites, “wherein the plurality of conductive patterns includes a select line and a first conductive pattern” which appears to identify the select line and the first conductive pattern as separate elements included within the plurality of conductive patterns. The claim subsequently recites, “the first conductive pattern corresponding to the select line”. This creates an ambiguity as to whether the first conductive pattern is itself the select line or whether the first conductive pattern is a separate conductive pattern that merely corresponds to the select line.
If the first conductive pattern is intended to be the select line, the earlier recitation of, “a select line and a first conductive pattern” appears to identify them as two separate elements.
Conversely, if the first conductive pattern and the select line are distinct elements, it is unclear what is meant by the first conductive pattern “corresponding to” the select line and which conductive pattern is used in determining the subsequently recited width of the channel structure.
Claim 9 recites that the channel structure comprises a core insulating layer, a first channel layer, a second channel layer and a gate insulating layer. Claim 9 further recites, “a width of the channel structure extending through the first conductive pattern corresponding to the select line is narrower than a width of the channel structure extending through the plurality of conductive patterns other than the first conductive pattern”.
It is unclear what structural dimension constitutes the recited “width of the channel structure”. As illustrated in Figure 8E, the core insulating layer appears narrower at the select line. However, the claimed channel structure at the select line also includes the first channel layer, the second channel layer and the gate insulating layer. When the widths of all components expressly recited as forming the channel structure are considered, the overall channel structure at the select line appears wider rather than narrower than the channel structure, including the core insulating layer and the first channel layer, extending through the other conductive patterns.
Claims 10-12 and 20 depend upon claim 9 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-11 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable by Tsutsumi et al. (US 2020/0251489 A1; hereafter Tsutsumi) in view of Pachamuthu et al. (US 2017/0125438 A1; hereafter Pachamuthu), Parekh (US 2021/0398859 A1) and Choi et al. (US 2018/0151672 A1; hereafter Choi).
Regarding claim 1, Tsutsumi teaches a semiconductor memory device (see e.g., Figures 5 and 10-14) comprising:
a gate stacked body including a plurality of interlayer insulating layers (see e.g., a plurality of insulating layers 32, Para [0200], Figures 10-14) and a plurality of conductive patterns (see e.g., plurality of electrically conductive layer 46, Para [0213], Figures 14A,14B) that are alternately stacked in a first direction (see e.g., the plurality of insulating layer 32 and the plurality of conductive layer 46 are alternately stacked in a vertical direction on the substrate 9, Figures 10-14);
wherein the plurality of conductive patterns includes a select line and a first conductive pattern (see e.g., A bottommost electrically conductive layer 46 provided upon formation of the electrically conductive layers 46 within the alternating stack (32, 46) may comprise a select gate electrode for the field effect transistors, Para [0220], Figures 10-14; Examiner’s interpretation: first conductive pattern and select line are considered same);
a channel structure (see e.g., a channel structure including the vertical channel 60 of the memory stack structure 55, which is formed in a respective one of the memory openings 49, and the pedestal channel portion 11, Paras [0185], [0187], [0190], Figures 5 and 10-14) penetrating at least a portion of the gate stacked body (see e.g., the vertical channel 60 penetrates the alternating stack of insulating layer 32 and the conductive layer 46, Figures 5 and 10-14), and an upper surface of the channel structure exposed by the gate stacked body (see e.g., the upper surface of the pedestal channel portion 11 is exposed by the gate stack and is in contact with the semiconductor layer 10, Para [0168], Figures 5 and 10-14);
a memory layer disposed between the channel structure and the gate stacked body (see e.g., a set of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 in a memory opening 49 constitutes a memory film 50 disposed between the vertical channel 60 and the alternating stack of insulating layer 32 and the conductive layer 46, Paras [0180], Figure 5); and a source line structure formed on the gate stacked body to contact the upper surface of the channel structure (see e.g., semiconductor material layer 10 contacting the upper surface of the pedestal channel portion 11, Paras [0143], [0168], Figures 5 and 10-14),
wherein the channel structure comprises:
a first channel layer extending in the first direction (see e.g., the vertical channel 60, Para [0185], Figures 5 and 10-14);
a second channel layer disposed between the first channel layer and the select line and between the first channel layer and the source line structure (see e.g., pedestal channel portion 11 is disposed between the vertical channel 60 and the bottommost electrically conductive layer 46 which may comprise a select gate electrode for the field effect transistors and between the vertical channel 60 and the semiconductor material layer 10, Paras [0168], [0181], [0220], Figures 5 and 10-14).
a gate insulating layer (see e.g., tubular dielectric spacer 216, Para [0204], Figures 10-14) disposed between the select line and the second channel layer (see e.g., the tubular dielectric spacer 216 is disposed between the bottommost electrically conductive layer 46 which is the select gate electrode for the field effect transistors and the pedestal channel portion 11, Para [0220], Figures 10-14);
Tsutsumi does not explicitly teach
“ a slit extending in the first direction within the gate stacked body….wherein the slit is not overlapped with the select line in a second direction crossing the first direction”.
In a similar field of endeavor Parekh teaches
a slit passing through the gate stacked body (see e.g., as shown in modified Figure 2H, a slit passes through the gate stacked body 132 including alternating insulative structures 128 and the conductive structures 130, Para [0040]); …..
wherein the slit is not overlapped with the select line in a second direction crossing the first direction.
As shown in Figure 4 of the instant application, the select line is segmented into left side and right portions by an opening that is filled with an interlayer dielectric (ILD)material. This opening coincides with the slit passing through the word lines.
This configuration is exactly taught by Parekh. As shown in modified Figure 2H of Parekh, their select line is also divided into a left side and a right side by a similar opening which is filled with an insulating material (214) and likewise overlaps the slit passing through the word lines. Therefore, the claimed limitation regarding non-overlap in the second direction is considered to be met by Parekh.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Parekh’s teachings of wherein the slit is not overlapped with the select line in a second direction crossing the first direction in the device of Tsutsumi in order to divide the gate stack.
Tsutsumi does not explicitly teach
“wherein the gate insulating layer covers an entire sidewall of the second channel layer”.
In a similar field of endeavor Pachamuthu
wherein the gate insulating layer covers an entire sidewall of the second channel layer (see e.g., dielectric collar structure 501 covers an entire sidewall of the epitaxial channel portion 11, Paras [0057], [0172], [0175], Figure 2K).
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement Pachamuthu’s teachings of wherein the gate insulating layer covers an entire sidewall of the second channel layer in the device of Tsutsumi as it functions as a gate dielectric of a select transistor of a vertical NAND string.
Tsutsumi does not explicitly teach
“wherein a width of the channel structure extending through the first conductive pattern corresponding to the select line is narrower than a width of the channel structure extending through the plurality of conductive patterns other than the first conductive pattern”.
A change in shape is a matter of design choice, which a person within the level of ordinary skill in the art would have found to be obvious absent persuasive evidence that the particular configuration of the side face of the nonmagent is at a nonzero angle with respect wo a side face of the layer stack was significant, and a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
In a similar field of endeavor Choi teaches
wherein a width of the channel structure extending through the first conductive pattern corresponding to the select line is narrower than a width of the channel structure extending through the plurality of conductive patterns other than the first conductive pattern (see e.g., lower electrode Ela serves as the ground selection line. The lower semiconductor pattern LSP penetrates Ela, thus the portion of the channel structure extending through Ela is narrower than the portions of the channel structure extending through the overlying conductive patterns, Para [0023], Figures 1 and 22).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Choi’s teachings of wherein a width of the channel structure extending through the first conductive pattern corresponding to the select line is narrower than a width of the channel structure extending through the plurality of conductive patterns other than the first conductive pattern in the device of Tsutsumi as the tapered or narrowed profile represents a known alternative geometry for forming a vertical channel through a select line. Selection of the particular opening profile would have been a matter of design choice based on the desired channel geometry and etching conditions as the modified opening would perform the same function of accommodating the channel structure through the select line and stacked conductive patterns.
Regarding claim 9, Tsutsumi teaches a semiconductor memory device (see e.g., Figures 5 and 10-14) comprising:
a gate stacked body including a plurality of interlayer insulating layers (see e.g., a plurality of insulating layers 32, Para [0200], Figures 10-14) and a plurality of conductive patterns (see e.g., plurality of electrically conductive layer 46, Para [0213], Figures 14A,14B) that are alternately stacked in a first direction (see e.g., the plurality of insulating layer 32 and the plurality of conductive layer 46 are alternately stacked in a vertical direction on the substrate 9, Figures 10-14), wherein the plurality of conductive patterns includes a select line and a first conductive pattern (see e.g., A bottommost electrically conductive layer 46 provided upon formation of the electrically conductive layers 46 within the alternating stack (32, 46) may comprise a select gate electrode for the field effect transistors, Para [0220], Figures 10-14; Examiner’s interpretation: the select line and the first conductive pattern are the same);
a channel structure (see e.g., a channel structure including the vertical channel 60 of the memory stack structure 55, which is formed in a respective one of the memory openings 49, and the pedestal channel portion 11, Paras [0185], [0187], [0190], Figures 5 and 10-14) penetrating at least a portion of the gate stacked body (see e.g., the vertical channel 60 penetrates the alternating stack of insulating layer 32 and the conductive layer 46, Figures 5 and 10-14), and an upper surface of the channel structure exposed by the gate stacked body (see e.g., the upper surface of the pedestal channel portion 11 is exposed by the gate stack and is in contact with the semiconductor layer 10, Para [0168], Figures 5 and 10-14);
a memory layer configured to enclose a sidewall of the channel structure (see e.g., a set of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 in a memory opening 49 constitutes a memory film 50 enclosing a sidewall of the vertical channel 60, Paras [0180], Figure 5); and a source line structure formed on the gate stacked body to contact the upper surface of the channel structure (see e.g., semiconductor material layer 10 contacting the upper surface of the pedestal channel portion 11, Paras [0143], [0168], Figures 5 and 10-14);
wherein the channel structure comprises:
a core insulating layer extending in the first direction (see e.g., dielectric core 62 extending in the vertical direction, Para [0184], Figures 5 and 10-14);
a first channel layer (see e.g., the vertical channel 60, Para [0185], Figures 5 and 10-14) configured to enclose an outer wall of the core insulating layer; and (see e.g., vertical channel 60 encloses the outer wall of the dielectric core 62, Para [0185], Figures 5 and 10-14)
a second channel layer disposed between the first channel layer and the select line and between the first channel layer and the source line structure (see e.g., pedestal channel portion 11 is disposed between the vertical channel 60 and the bottommost electrically conductive layer 46 which may comprise a select gate electrode for the field effect transistors and between the vertical channel 60 and the semiconductor material layer 10, Paras [0168], [0181], [0220], Figures 5 and 10-14); and
a gate insulating layer (see e.g., tubular dielectric spacer 216, Para [0204], Figures 10-14) disposed between the second channel layer and the select line (see e.g., the tubular dielectric spacer 216 is disposed between the bottommost electrically conductive layer 46 which is the select gate electrode for the field effect transistors and the pedestal channel portion 11, Para [0220], Figures 10-14);
Tsutsumi does not explicitly teach
“a slit extending in the first direction within the gate stacked body; … wherein the slit is not overlapped with the select line in a second direction crossing the first direction”.
In a similar field of endeavor Parekh teaches
a slit passing through the gate stacked body (see e.g., as shown in modified Figure 2H, a slit passes through the gate stacked body 132 including alternating insulative structures 128 and the conductive structures 130, Para [0040]); …
wherein the slit is not overlapped with the select line in a second direction crossing the first direction.
As shown in Figure 4 of the instant application, the select line is segmented into left side and right portions by an opening that is filled with an interlayer dielectric (ILD) material. This opening coincides with the slit passing through the word lines.
This configuration is exactly taught by Parekh. As shown in modified Figure 2H of Parekh, their select line is also divided into a left side and a right side by a similar opening which is filled with an insulating material (214) and likewise overlaps the slit passing through the word lines. Therefore, the claimed limitation regarding non-overlap in the second direction is considered to be met by Parekh.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Parekh’s teachings of wherein the slit is not overlapped with the select line in a second direction crossing the first direction in the device of Tsutsumi in order to divide the gate stack.
Tsutsumi does not explicitly teach
“wherein the gate insulating layer covers an entire sidewall of the second channel layer”.
In a similar field of endeavor Pachamuthu
wherein the gate insulating layer covers an entire sidewall of the second channel layer (see e.g., dielectric collar structure 501 covers an entire sidewall of the epitaxial channel portion 11, Paras [0057], [0172], [0175], Figure 2K).
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement Pachamuthu’s teachings of wherein the gate insulating layer covers an entire sidewall of the second channel layer in the device of Tsutsumi as it functions as a gate dielectric of a select transistor of a vertical NAND string.
Tsutsumi does not explicitly teach
“wherein a width of the channel structure extending through the first conductive pattern corresponding to the select line is narrower than a width of the channel structure extending through the plurality of conductive patterns other than the first conductive pattern”.
A change in shape is a matter of design choice, which a person within the level of ordinary skill in the art would have found to be obvious absent persuasive evidence that the particular configuration of the side face of the nonmagent is at a nonzero angle with respect wo a side face of the layer stack was significant, and a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
In a similar field of endeavor Choi teaches
wherein a width of the channel structure extending through the first conductive pattern corresponding to the select line is narrower than a width of the channel structure extending through the plurality of conductive patterns other than the first conductive pattern (see e.g., lower electrode Ela serves as the ground selection line. The lower semiconductor pattern LSP penetrates Ela, thus the portion of the channel structure extending through Ela is narrower than the portions of the channel structure extending through the overlying conductive patterns, Para [0023], Figures 1 and 22).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Choi’s teachings of wherein a width of the channel structure extending through the first conductive pattern corresponding to the select line is narrower than a width of the channel structure extending through the plurality of conductive patterns other than the first conductive pattern in the device of Tsutsumi as the tapered or narrowed profile represents a known alternative geometry for forming a vertical channel through a select line. Selection of the particular opening profile would have been a matter of design choice based on the desired channel geometry and etching conditions as the modified opening would perform the same function of accommodating the channel structure through the select line and stacked conductive patterns.
Regarding claims 2 and 10, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 1 and 9 as mentioned above. Tsutsumi further teaches
wherein the upper surface of the channel structure is a surface of the second channel layer (see e.g., the upper surface of the channel structure is a surface of the pedestal channel portion 11 in contact with the semiconductor layer 10, Figures 5 and 10-14).
Regarding claim 3, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 1 as mentioned above. Tsutsumi further teaches further comprising:
Tsutsumi does not explicitly teach
“wherein the gate insulating layer is in contact with the source line structure”
In a similar field of endeavor Pachamuthu teaches
wherein the gate insulating layer is in contact with the source line structure (see e.g., the dielectric collar structure 501 is in contact with the semiconductor well layer 10, Para [0059], Figure 2K).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Pachamuthu’s teachings of wherein the gate insulating layer is in contact with the source line structure in the device of Tsutsumi in order to form the gate dielectric of a SSG transistor.
Regarding claim 4, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 3 as mentioned above. Tsutsumi further teaches
wherein the plurality of conductive patterns further includes word lines (see e.g., Each electrically conductive layer 46 may function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically connecting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer 46 are the control gate electrodes for the vertical memory devices including the memory stack structures 55. In other words, each electrically conductive layer 46 may be a word line that functions as a common control gate electrode for the plurality of vertical memory devices, Para [0213], Figure 14A),
wherein the select line is disposed between the source line structure and the word lines (see e.g., the bottommost electrically conductive layer 46 may comprise a select gate electrode for the field effect transistors and is disposed between the semiconductor material layer 10 and the word lines, Paras [0143], [0168], [0220], Figure 14), and
wherein the memory layer is disposed between the word lines and the first channel layer (see e.g., the memory film 50 is disposed between the plurality of conductive layers 46, other than the bottommost electrically conductive layer 46, and the vertical channel 60, Para [0180], [0187], Figures 5 and 10-14).
Regarding claim 5, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 4 as mentioned above. Tsutsumi further teaches
wherein the memory layer comprises:
a tunnel insulating layer configured to enclose an outer wall of the first channel layer (see e.g., tunneling dielectric layer 56 which encloses an outer wall of the vertical channel 60, Paras [0176], [0180], Figure 5);
a data storage layer configured to enclose an outer wall of the tunnel insulating layer; and (see e.g., charge storage layer 54 which encloses an outer wall of the tunneling insulating layer 56, Paras [0175], [0180], Figure 5)
a blocking insulating layer configured to enclose an outer wall of the data storage layer (see e.g., blocking dielectric layer 52 which encloses an outer wall of the charge storage layer 54, Paras [0172], [0180], Figure 5).
Regarding claim 11, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 9 as mentioned above. Tsutsumi further teaches
wherein the memory layer comprises:
a tunnel insulating layer configured to enclose an outer wall of the first channel layer (see e.g., tunneling dielectric layer 56 which encloses an outer wall of the vertical channel 60, Paras [0176], [0180], Figure 5);
a data storage layer configured to enclose an outer wall of the tunnel insulating layer; and (see e.g., charge storage layer 54 which encloses an outer wall of the tunneling insulating layer 56, Paras [0175], [0180], Figure 5)
a blocking insulating layer configured to enclose an outer wall of the data storage layer (see e.g., blocking dielectric layer 52 which encloses an outer wall of the charge storage layer 54, Paras [0172], [0180], Figure 5).
Regarding claim 19, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 1 as mentioned above. Tsutsumi further teaches
wherein the gate insulating layer is disposed only along the sidewall of the second channel layer and is absent from an upper surface of the gate stacked body (see e.g., tubular dielectric spacer 216 is disposed only along the sidewall of the pedestal channel portion 11 and is absent from an upper surface of the gate stacked body, Para [0220], Figures 10-14).
Regarding claim 20, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 9 as mentioned above. Tsutsumi does not explicitly teach
“wherein the gate insulating layer extends continuously along a full vertical length of the second channel layer between the select line and the source line structure”.
In a similar field of endeavor Pachamuthu teaches
wherein the gate insulating layer extends continuously along a full vertical length of the second channel layer between the select line and the source line structure (see e.g., dielectric collar structure 501 continuously along a full vertical length of the epitaxial channel portion 11 between the select line 42 (the top and bottom gate electrodes function as the select gate electrodes) and the semiconductor well layer 10, Paras [0051], [0059], [0172], Figure 2k).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Pachamuthu’s teachings of wherein the gate insulating layer extends continuously along a full vertical length of the second channel layer between the select line and the source line structure in the device of Tsutsumi as it functions as a gate dielectric of a select transistor of a vertical NAND string.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable by Tsutsumi et al. (US 2020/0251489 A1; hereafter Tsutsumi) in view of Pachamuthu et al. (US 2017/0125438 A1; hereafter Pachamuthu), Parekh (US 2021/0398859 A1) and Choi et al. (US 2018/0151672 A1; hereafter Choi) and further in view of Lue et al. (US 2021/0193677 A1; hereafter Lue).
Regarding claim 6, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 1 as mentioned above. Tsutsumi further teaches
wherein the first channel layer is polysilicon layer (see e.g., a semiconductor channel material including the first semiconductor channel layer 601 and the second semiconductor channel layer 602 may include polysilicon, Paras [0177], [0181], [0182], Figures 5 and 10-14).
Tsutsumi does not explicitly teach
“channel layer is an undoped polysilicon layer”.
In a similar field of endeavor Lue teaches
channel layer is an undoped polysilicon layer (see e.g., the material of the channel layer 116 is un-doped polycrystalline silicon, Para [0032], Figure 7B)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lue’s teachings of channel layer is an undoped polysilicon layer in the device of Tsutsumi in order to have precise control over channel’s electrical properties, particularly when minimizing short channel effects.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi et al. (US 2020/0251489 A1; hereafter Tsutsumi) in view of Pachamuthu et al. (US 2017/0125438 A1; hereafter Pachamuthu), Parekh (US 2021/0398859 A1) and Choi et al. (US 2018/0151672 A1; hereafter Choi) and further in view Tsutsumi et al. (US 10,192,878 B1; hereafter Tsutsumi 878’).
Regarding claim 7, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 1 as mentioned above. Tsutsumi further teaches
wherein the second channel layer is a doped silicon layer (see e.g., the pedestal channel portion 11 may comprise a single crystalline silicon and may have a doping of the first conductivity type, Para [0168], Figures 5 and 10-14).
Tsutsumi does not explicitly teach
“wherein the second channel layer is a polycrystalline layer”.
In a similar field of endeavor Tsutsumi 878’ teaches
wherein the second channel layer is a polycrystalline layer (see e.g., the pedestal channel portions maybe polycrystalline, Column 10, Lines 64-65, Figure 5).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tsutsumi 878’s teachings of the second channel layer is a polycrystalline layer in the device of Tsutsumi as this is a well-known material in the art and cheaper to produce.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable by Tsutsumi et al. (US 2020/0251489 A1; hereafter Tsutsumi) in view of Pachamuthu et al. (US 2017/0125438 A1; hereafter Pachamuthu), Parekh (US 2021/0398859 A1) and Choi et al. (US 2018/0151672 A1; hereafter Choi) and further in view of Zhang et al. (US 20220302151 A1; hereafter Zhang).
Regarding claim 8, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 1 as mentioned above. Tsutsumi further teaches
wherein the source line structure comprises:
a first source layer (see e.g., semiconductor layer 10, Para [0143], Figures 10-14) formed along an upper portion of the gate stacked body (see e.g., the semiconductor layer 10 is formed along an upper portion of the gate stacked body including the alternating insulating layer 32 and the conductive layer 46, Para [0143], Figures 10-14) and the surface of the channel structure (see e.g., the semiconductor layer 10 is formed along the upper surface of the pedestal channel portion 11, Figures 5 and 10-14); and
a second source layer formed on the first source layer (see e.g., conductive plate layer 6 provides a high conductivity conduction path for electrical current that flows into, or out of, the in-process source-level material layers 310′ formed in lieu of semiconductor material layer 10, Para [0241], Figure 25A).
Tsutsumi does not explicitly teach
“upper surface of the channel structure”
In a similar field of endeavor Zhang shows that a similar device as Tsutsumi in Figs. 3A to 3F, which is ultimately flipped by Fig. 3G, which would show that the source layer on the upper surface of the channel [the channel cap is already taught by Tsutsumi and Zhang is merely shown for the orientation configuration].
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Zhang’s teachings of a second channel layer configured to enclose a sidewall of the first channel layer adjacent to an uppermost conductive pattern in the device of Tsutsumi in order to flip the memory core so as to shorten the wiring distances and minimize the wiring complexity to connect to the memory core control circuitries.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi et al. (US 2020/0251489 A1; hereafter Tsutsumi) in view of Pachamuthu et al. (US 2017/0125438 A1; hereafter Pachamuthu), Parekh (US 2021/0398859 A1) Choi et al. (US 2018/0151672 A1; hereafter Choi) and further in view Tsutsumi et al. (US 10,192,878 B1; hereafter Tsutsumi 878’) and Lue et al. (US 2021/0193677 A1; hereafter Lue).
Regarding claim 12, Tsutsumi, as modified by Parekh, Pachamuthu and Choi, teaches the limitations of claim 9 as mentioned above. Tsutsumi further teaches
wherein the first channel layer is polysilicon layer (see e.g., a semiconductor channel material including the first semiconductor channel layer 601 and the second semiconductor channel layer 602 may include polysilicon, Paras [0177], [0181], [0182], Figures 5 and 10-14).
and the second channel layer is a doped silicon layer (see e.g., the pedestal channel portion 11 may comprise a single crystalline silicon and may have a doping of the first conductivity type, Para [0168], Figures 5 and 10-14).
Tsutsumi does not explicitly teach
“first channel layer is an undoped polysilicon layer”
In a similar field of endeavor Lue teaches
first channel layer is an undoped polysilicon layer (see e.g., the material of the channel layer 116 is un-doped polycrystalline silicon, Para [0032], Figure 7B)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lue’s teachings of channel layer is an undoped polysilicon layer in the device of Tsutsumi in order to have precise control over channel’s electrical properties, particularly when minimizing short channel effects.
Tsutsumi does not explicitly teach
wherein the second channel layer is a polycrystalline layer.
In a similar field of endeavor Tsutsumi 878’ teaches
wherein the second channel layer is a polycrystalline layer (see e.g., the pedestal channel portions maybe polycrystalline, Column 10, Lines 64-65, Figure 5).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tsutsumi 878’s teachings of the second channel layer is a polycrystalline layer in the device of Tsutsumi as this is a well-known material in the art and cheaper to produce.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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