DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 25-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation “the first insulating layer” in line 6. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “a first electrically insulating layer”, as recited in claim 25, line 1.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 7-10, 12, 25-27 and 29-32, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (2019/0165120) in view of Heo et al. (2021/0083121).
As for claims 1, 12, 25 and 32, Sato shows in Fig. 15 and related text a semiconductor device (field effect transistor) 1G, comprising:
a substrate (bottom portion of) 80;
a first (electrically) insulating layer (top portion of) 80 extending on and in physical contact with the substrate;
a source pattern 50 (electrically coupled to a first end of the channel layer) and a drain pattern 60 (electrically coupled to a second end of the channel layer) at spaced-apart locations on the first insulating layer;
a channel layer 90 having a transition metal therein ([0142]; [0144]), said (the) channel layer extending on (sandwiched between) the first (electrically) insulating layer (and the second electrically insulating layer) from the source pattern to the drain pattern and in physical contact with the first insulating layer;
a second (electrically) insulating layer 31, which extends on the channel layer and has a thickness less than a thickness of the first insulating layer; and
a gate structure 32/10/40 extending on the second insulating layer, and opposite the channel layer, wherein the gate structure includes a gate dielectric layer 32 covering at least a portion of the second insulating layer, the gate dielectric layer comprised of a ferroelectric material film ([0113]-[0114]),
wherein a topmost surface of the first insulating layer is in physical contact with a lower surface of the source pattern and a lower surface of the drain pattern, and
wherein the gate dielectric layer comprises a first material that is different from a second material of the second insulating layer ([0035]; [0152]).
Sato does not disclose the ferroelectric material film having a dopant (claims 1 and 25); the gate dielectric layer comprises at least one of hafnium oxide (HfOx), hafnium aluminum oxide (HfAIOx), hafnium silicon oxide (HfSiOx), hafnium zirconium oxide (HfZrOx), hafnium yttrium oxide (HfYOx), and hafnium gadolinium oxide (HfGdOx) (claim 12); and the dopant comprises at least one of aluminum (AI), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn) (claim 32).
Heo et al. teach in Figs. 4 and related text:
As for claims 1 and 25, the ferroelectric material film 240 having a dopant ([0009]-[0010]; [0054]-[0056]).
As for claim 12, the gate dielectric layer comprises at least one of hafnium oxide (HfOx), hafnium aluminum oxide (HfAIOx), hafnium silicon oxide (HfSiOx), hafnium zirconium oxide (HfZrOx), hafnium yttrium oxide (HfYOx), and hafnium gadolinium oxide (HfGdOx) ([0009]; [0054]-[0055]).
As for claim 32, the dopant comprises at least one of aluminum (AI), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn) ([0010]; [0056]).
Sato and Heo et al. are analogous art because they are directed to a field effect transistor and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sato with the specified feature(s) of Heo et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use the ferroelectric material film having a dopant, as the gate dielectric layer, wherein the gate dielectric layer comprising at least one of hafnium oxide (HfOx), hafnium aluminum oxide (HfAIOx), hafnium silicon oxide (HfSiOx), hafnium zirconium oxide (HfZrOx), hafnium yttrium oxide (HfYOx), and hafnium gadolinium oxide (HfGdOx); and the dopant comprising at least one of aluminum (AI), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn), as taught by Heo et al., in Sato's device, in order to stabilize phase formation, reduce leakage current and improve performance of the device.
As for claim 2, the combined device shows the transition metal comprises a transition metal dichalcogenide (Sato: [0142]; [0144]).
As for claims 3 and 26, the combined device shows the channel layer comprises at least one of MoS2, WS2, MoSe2, WSe2, MoSe2, WTe2, and ZrSe2 (Sato: [0142]; [0144]).
As for claims 4 and 27, Sato and Heo et al. disclosed substantially the entire claimed invention, as applied to claims 1 and 25, respectively, above, the (a) thickness of the first (electrically) insulating layer is 3 angstroms to 30 angstroms thicker than the (a) thickness of the second (electrically) insulating layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the (a) thickness of the first (electrically) insulating layer being 3 angstroms to 30 angstroms thicker than the (a) thickness of the second (electrically) insulating layer, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
As for claim 7, the combined device shows the source pattern is in contact with a first side surface of the channel layer and a first portion of an upper surface of the channel layer; and
wherein the drain pattern is in contact with a second side surface of the channel layer and a second portion of the upper surface of the channel layer (Sato: Fig. 15).
As for claim 8, the combined device shows at least a portion of the second insulating layer is disposed between the source pattern and the drain pattern (Sato: Fig. 15).
As for claim 9, the combined device shows the source pattern and the drain pattern comprise a metal material (Sato: [0089]).
As for claim 10, the combined device shows the source and drain patterns each comprise at least one of gold (Au), copper (Cu), nickel (Ni), silver (Ag), aluminum (AI), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), and tungsten (W) (Sato: [0089]).
As for claim 29, the combined device shows the source pattern contacts the first electrically insulating layer and the second electrically insulating layer; and
wherein the drain pattern contacts the first electrically insulating layer and the second electrically insulating layer (Sato: Fig. 15).
As for claim 30, the combined device shows a first thermal expansion coefficient of the first electrically insulating layer and a second thermal expansion coefficient of the second electrically insulating layer are each greater than a channel thermal expansion coefficient of the channel layer (Sato: [0035]; [0152]; [0142]; and [0144]; note: TEC of each of polymer and Al2O3 is higher than TEC of W).
As for claim 31, the combined device shows the first electrically insulating and the second electrically insulating layer have a planar structure (Sato: Fig. 15).
Claim(s) 5, 6, 11 and 28, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (2019/0165120) and Heo et al. (2021/0083121) in view of Huang et al. (2021/0376133).
As for claims 5, 6, 11 and 28, Sato and Heo et al. disclosed substantially the entire claimed invention, as applied to claims 1 and 25, respectively, above, including the gate structure comprises: a gate electrode layer 10/40 extending on the gate dielectric layer (Sato: Fig. 15); the second insulating layer comprises at least one of silicon oxide, silicon nitride, and silicon oxynitride ([0035]).
Sato and Heo et al. do not disclose the first (electrically) insulating layer and the second (electrically) insulating layer comprise hexagonal boron nitride (h-BN) (claims 5 and 28); the first insulating layer comprises hexagonal boron nitride (h-BN) (claim 6) and the gate structure comprises a gate spacer layer extending on one or more side surfaces of the gate electrode layer (claim 11).
Huang et al. teach in Figs. 14A-14C and related text:
As for claims 5 and 28, the first (electrically) insulating layer 103/105 and the second (electrically) insulating layer (lower portion of) 115 comprise hexagonal boron nitride (h-BN) ([0020]; [0034]).
As for claim 6, the first insulating layer comprises hexagonal boron nitride (h-BN) ([0020]).
As for claim 11, the gate structure comprises:
a gate spacer layer (portion of) 125 extending on one or more side surfaces of the gate electrode layer 117 (Huang: Fig. 14A).
Sato, Heo et al. and Huang et al. are analogous art because they are directed to a field effect transistor and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sato and Heo et al. with the specified feature(s) of Huang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to the first (electrically) insulating layer and the second (electrically) insulating layer comprising hexagonal boron nitride (h-BN); the first insulating layer comprising hexagonal boron nitride (h-BN); and the gate structure comprising a gate spacer layer extending on one or more side surfaces of the gate electrode layer, as taught by Huang et al., in Sato and Heo et al.’s device, in order to reduce leakage current and improve device reliability.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12 and 25-32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MEIYA LI/Primary Examiner, Art Unit 2811