DETAILED ACTION
This office action is in response to amendment filed 9/17/2025.
Claims 1-5 and 7-20 are pending. Claim 6 has been canceled. Claims 8 and 12 have been withdrawn. Claims 1, 4, 7, 13, and 17 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 9-11, and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw US 2019/0348524 A1 in view of Li et al. US 2022/0045198 A1 (Li).
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In re claim 1, Liaw discloses (e.g. FIGs. 2-8) a semiconductor device comprising:
a substrate 16 including a first region 12 and a second region 14;
a first active pattern 32A extending in a first direction Y, on the first region 12;
a first gate structure 50A extending in a second direction X crossing the first direction Y and having a first width in the first direction Y, on the first active pattern 32A;
a first epitaxial pattern 60A disposed in the first active pattern 30A on a side surface of the first gate structure 50A;
a second active pattern 32C extending in a third direction Y, on the second region 14;
a second gate structure 50C extending in a fourth direction X crossing the third direction Y and having a second width greater than the first width (of 50A) in the third direction Y (see FIG. 7A), on the second active pattern 32C;
a second epitaxial pattern 60C disposed in the second active pattern 32C on a side surface of the second gate structure 50C,
on the first region 12, a third gate structure 50B directly adjacent to the first gate structure 50A in the first direction Y without any intervening gate structure, and extending side by side with the first gate structure 50A; and
on the second region 14, a fourth gate structure 50D directly adjacent to the second gate structure 50C in the third direction Y without any intervening gate structure, and extending side by side with the second gate structure 50C,
wherein a first distance by which the first gate structure 50A and the third gate structure 50B are spaced apart from each other in the first direction Y is smaller than a second distance by which the second gate structure 50C and the fourth gate structure 50D are spaced apart from each other in the third direction Y (see FIG. 7A),
wherein each of the first epitaxial pattern 60A and the second epitaxial pattern 60C includes silicon germanium (SiGe, ¶ 26).
Liaw teaches the first epitaxial pattern 60A and the second epitaxial pattern 60C includes silicon germanium for forming p-type source/drain features of FinFETs 13A,15A.
Liaw discloses does not explicitly disclose the second epitaxial pattern 60C has a second Ge concentration that is higher than a first Ge concentration of the first epitaxial pattern 60A.
However, Li teaches (FIGs. 1-2) a p-type FinFET having S/D regions 124 that include an epitaxially-grown stack of SiGe layers 124A-124C, wherein the first SiGe layer 124A has a Ge concentration of about 20% to 30% to reduce crystal defects in overlying layers (¶ 35), the second SiGe layer 124B has a Ge concentration of about 50% to 55% to provide sufficient strain to enhance channel mobility (¶ 36), and the third SiGe layer 124C has a Ge concentration of about 15% to 25% to form a low resistance silicide contact (¶ 37).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Liaw’s SiGe source/drain epitaxial patterns 60A,60C to have a multilayered structure including a 20-30% Ge bottom SiGe layer, a 50-55% Ge middle SiGe layer, and a 15-25% Ge top SiGe layer as taught by Li, to provide epitaxial source/drain patterns with optimized defects reduction, strain induction, and low resistance contact as taught by Li.
As such, the second epitaxial pattern 60C has a second Ge concentration (e.g. 20-30% Ge bottom lower or 50-55% Ge middle layer) that is higher than the first Ge concentration (e.g. 15-25% Ge top layer) of the first epitaxial pattern 60A.
In re claim 2, Liaw discloses (e.g. FIGs. 2-8) wherein each of the first region 12 and the second region 14 includes a plurality of P-channel field effect transistors (PFETs) 13A,15A (¶ 13, 26).
In re claim 3, as detailed above, it would be obvious to form Liaw’s SiGe source/drain epitaxial patterns 60A,60C to have a multilayered structure including a 20-30% Ge bottom SiGe layer, a 50-55% Ge middle SiGe layer, and a 15-25% Ge top SiGe layer as taught by Li. As such, a difference between the first Ge concentration (e.g. 15-25% Ge top layer of first epitaxial pattern 60A) and the second Ge concentration (e.g. 20-30% Ge bottom lower of second epitaxial pattern 60C) is 5% to 20%.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 4, Liaw discloses (e.g. FIG. 2) further comprising:
a third active pattern (another one of 32A) adjacent to the first active pattern (adjacent 32A) in the second direction X and extending side by side with the first active pattern, on the first region 12; and
a fourth active pattern (another one of 32C) adjacent to the second active pattern (adjacent 32C) in the fourth direction X and extending side by side with the second active pattern, on the second region 14,
wherein a third distance S1 by which the first active pattern 32A and the third active pattern 32A are spaced apart from each other is smaller than a fourth distance S3 by which the second active pattern 32C and the fourth active pattern 32C are spaced apart from each other (¶ 19).
In re claim 5, Liaw discloses (FIGs. 2B-2C) further comprising a field insulating film 34 separating the first active pattern 32A and the third active pattern 32A and separating the second active pattern 32C and the fourth active pattern 32C, on the substrate 16.
In re claim 7, Liaw discloses (e.g. FIG. 7A) wherein the first epitaxial pattern 60A is interposed between the first gate structure 50A and the third gate structure 50B, and
wherein the second epitaxial pattern 60C is interposed between the second gate structure 50C and the fourth gate structure 50D.
In re claim 9, Liaw discloses (e.g. FIG. 4) wherein each of the first epitaxial pattern 60A and the second epitaxial pattern 60C pattern is formed by a selective epitaxial growth (SEG) process (¶ 25-26). Furthermore, In regard to the product by process language, since a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao and Sato et al., 190 USPQ 15 at 17 (CCPA 1976) (footnote 3). “[T]he lack of physical description in a product-by-process claim makes determination of the patentability of the claim more difficult, since in spite of the fact that the claim may recite only process limitations, it is the patentability of the product claimed and not of the recited process steps which must be established. We are therefore of the opinion that when the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable. As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith.” In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the final product per se which must be determined for patentability in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not, is not patentable. Note that Applicant has the burden of proof in such cases, as the above case law makes clear. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based upon the product itself. The patentability of a product does not depend on its method of production. If the product in product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product is made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
In re claim 10, Liaw discloses (FIGs. 4B-4C) wherein the first epitaxial pattern 60A and the second epitaxial pattern 60C are formed at the same level in a vertical direction (i.e. both formed at the top surfaces of the recessed fins 32A,32B, ¶ 25).
In re claim 11, Liaw discloses (e.g. FIGs. 2B-2C) wherein each of the first active pattern 32A and the second active pattern 32C includes a fin pattern protruding from the substrate 16.
In re claim 13, Liaw discloses (e.g. FIGs. 2-8) a semiconductor device comprising:
a substrate 16 including a first region 12 and a second region 14;
a first gate structure 50A and a second gate structure 50B arranged along a first direction Y and each extending in a second direction X crossing the first direction Y, on the first region 12;
a first epitaxial pattern 60A disposed on the substrate 16 between the first gate structure 50A and the second gate structure 50B;
a third gate structure 50C and a fourth gate structure 50D arranged along a third direction Y and each extending in a fourth direction X crossing the third direction Y, on the second region 14; and
a second epitaxial pattern 60C disposed on the substrate 16 between the third gate structure 50C and the fourth gate structure 50D,
wherein a first distance by which the first gate structure 50A and the second gate structure 50B are spaced apart from each other in the first direction Y is smaller than a second distance by which the third gate structure 50C and the fourth gate structure 50D are spaced apart from each other in the third direction Y (see FIG. 7A),
wherein each of the first epitaxial pattern 60A and the second epitaxial pattern 60C includes silicon germanium (SiGe, ¶ 26),
wherein each of the first gate structure 50A and second gate structure 50B has a first width in the first direction Y,
wherein each of the third gate structure 50C and fourth gate structure 50D has a second width greater than the first width in the third direction Y (see FIG. 7A), and
wherein, in the first direction Y, the first and second gate structures 50A,50B are directly adjacent to each other without any intervening gate structure, and the third and fourth gate structures 50C,50D are directly adjacent to each other without any intervening gate structure.
Liaw teaches the first epitaxial pattern 60A and the second epitaxial pattern 60C includes silicon germanium for forming p-type source/drain features of FinFETs 13A,15A.
Liaw discloses does not explicitly disclose the second epitaxial pattern 60C has a second Ge concentration that is higher than a first Ge concentration of the first epitaxial pattern 60A.
However, Li teaches (FIGs. 1-2) a p-type FinFET having S/D regions 124 that include an epitaxially-grown stack of SiGe layers 124A-124C, wherein the first SiGe layer 124A has a Ge concentration of about 20% to 30% to reduce crystal defects in overlying layers (¶ 35), the second SiGe layer 124B has a Ge concentration of about 50% to 55% to provide sufficient strain to enhance channel mobility (¶ 36), and the third SiGe layer 124C has a Ge concentration of about 15% to 25% to form a low resistance silicide contact (¶ 37).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Liaw’s SiGe source/drain epitaxial patterns 60A,60C to have a multilayered structure including a 20-30% Ge bottom SiGe layer, a 50-55% Ge middle SiGe layer, and a 15-25% Ge top SiGe layer as taught by Li, to provide epitaxial source/drain patterns with optimized defects reduction, strain induction, and low resistance contact as taught by Li.
As such, the second epitaxial pattern 60C has a second Ge concentration (e.g. 20-30% Ge bottom lower or 50-55% Ge middle layer) that is higher than the first Ge concentration (e.g. 15-25% Ge top layer) of the first epitaxial pattern 60A.
In re claim 14, Liaw discloses (e.g. FIGs. 2-8) wherein each of the first region 12 and the second region 14 includes a plurality of P-channel field effect transistors (PFETs) 13A,15A (¶ 13, 26).
In re claim 15, as detailed above, it would be obvious to form Liaw’s SiGe source/drain epitaxial patterns 60A,60C to have a multilayered structure including a 20-30% Ge bottom SiGe layer, a 50-55% Ge middle SiGe layer, and a 15-25% Ge top SiGe layer as taught by Li. As such, a difference between the first Ge concentration (e.g. 15-25% Ge top layer of first epitaxial pattern 60A) and the second Ge concentration (e.g. 20-30% Ge bottom lower of second epitaxial pattern 60C) is 5% to 20%.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 16, Liaw discloses (e.g. FIG. 1) further comprising:
a first active pattern 32A and a second active pattern 32A extending side by side in the first direction Y and crossing the first gate structure 50A and the second gate structure 50B, on the first region 12; and
a third active pattern 32C and a fourth active pattern 32C extending side by side in the third direction Y and crossing the third gate structure 50C and the fourth gate structure 50D, on the second region 14,
wherein a third distance S1 by which the first active pattern 32A and the second active pattern 32A are spaced apart from each other in the second direction X is smaller than a fourth distance S3 by which the third active pattern 32C and the fourth active pattern 32C are spaced apart from each other in the fourth direction X (¶ 19).
In re claim 17, Liaw discloses (e.g. FIGs. 2-8) a semiconductor device comprising:
a substrate 16 including a first region 12 and a second region 14;
a first active pattern 32A and a second active pattern 32A each extending side by side in a first direction Y, on the first region 12;
a first gate structure 50A extending in a second direction X crossing the first direction Y, on the first active pattern 32A and the second active pattern 32A;
a first epitaxial pattern 60A disposed in the first active pattern 32A on a side surface of the first gate structure 50A;
a third active pattern 32C and a fourth active pattern 32C extending side by side in a third direction Y, on the second region 14;
a second gate structure 50C extending in a fourth direction X crossing the third direction Y, on the third active pattern 32C and the fourth active pattern 32C;
a second epitaxial pattern 60C disposed in the third active pattern 32C on a side surface of the second gate structure 50C;
on the first active pattern and the second active pattern 32A, a third gate structure 50B directly adjacent to the first gate structure 50A in the first direction Y without any intervening gate structure, and extending side by side with the first gate structure 50A; and
on the third active pattern and the fourth active pattern 32C, a fourth gate structure 50D directly adjacent to the second gate structure 50C in the third direction Y without any intervening gate structure, and extending side by side with the second gate structure 50C,
wherein a first distance S1 by which the first active pattern 32A and the second active pattern 32A are spaced apart from each other in the second direction X without any intervening active pattern is smaller than a second distance S3 by which the third active pattern 32C and the fourth active pattern 32C are spaced apart from each other in the fourth direction X without any intervening active pattern (¶ 19),
wherein a third distance by which the first gate structure 50A and the third gate structure 50B are spaced apart from each other in the first direction Y is smaller than a fourth distance by which the second gate structure 50C and the fourth gate structure 50D are spaced apart from each other in the third direction Y (see FIG. 7A),
wherein each of the first epitaxial pattern 60A and the second epitaxial pattern 60C includes silicon germanium (SiGe, ¶ 26).
Liaw teaches the first epitaxial pattern 60A and the second epitaxial pattern 60C includes silicon germanium for forming p-type source/drain features of FinFETs 13A,15A.
Liaw discloses does not explicitly disclose the second epitaxial pattern 60C has a second Ge concentration that is higher than a first Ge concentration of the first epitaxial pattern 60A.
However, Li teaches (FIGs. 1-2) a p-type FinFET having S/D regions 124 that include an epitaxially-grown stack of SiGe layers 124A-124C, wherein the first SiGe layer 124A has a Ge concentration of about 20% to 30% to reduce crystal defects in overlying layers (¶ 35), the second SiGe layer 124B has a Ge concentration of about 50% to 55% to provide sufficient strain to enhance channel mobility (¶ 36), and the third SiGe layer 124C has a Ge concentration of about 15% to 25% to form a low resistance silicide contact (¶ 37).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Liaw’s SiGe source/drain epitaxial patterns 60A,60C to have a multilayered structure including a 20-30% Ge bottom SiGe layer, a 50-55% Ge middle SiGe layer, and a 15-25% Ge top SiGe layer as taught by Li, to provide epitaxial source/drain patterns with optimized defects reduction, strain induction, and low resistance contact as taught by Li.
As such, the second epitaxial pattern 60C has a second Ge concentration (e.g. 20-30% Ge bottom lower or 50-55% Ge middle layer) that is higher than the first Ge concentration (e.g. 15-25% Ge top layer) of the first epitaxial pattern 60A.
In re claim 18, Liaw discloses (e.g. FIGs. 2-8) wherein each of the first region 12 and the second region 14 includes a plurality of P-channel field effect transistors (PFETs) 13A,15A (¶ 13, 26).
In re claim 19, as detailed above, it would be obvious to form Liaw’s SiGe source/drain epitaxial patterns 60A,60C to have a multilayered structure including a 20-30% Ge bottom SiGe layer, a 50-55% Ge middle SiGe layer, and a 15-25% Ge top SiGe layer as taught by Li. As such, a difference between the first Ge concentration (e.g. 15-25% Ge top layer of first epitaxial pattern 60A) and the second Ge concentration (e.g. 20-30% Ge bottom lower of second epitaxial pattern 60C) is 5% to 20%.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 20, Liaw discloses (e.g. FIG. 7A) wherein the first gate structure 50A has a first width in the first direction Y, and
wherein the second gate structure 50C has a second width greater than the first width (of 50A) in the third direction Y (see FIG. 7A).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7, 9-11 and 13-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights