DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for a first oxide semiconductor region including at least one predetermined element selected from the group consisting of silicon (Si) and tin (Sn) does not reasonably provide enablement for the first oxide semiconductor region of claim 5 which states that it includes indium (In), gallium (Ga), and zinc (Zn). The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make or use the invention commensurate in scope with these claims.
In the amendment filed on June 16, 2025, the applicant notably deleted indium as one of the predetermined elements in the first oxide semiconductor region in claim 1 such that claim 1 now reads (emphasis added), “the first oxide semiconductor region including at least one predetermined element selected from the group consisting of silicon (Si) and tin (Sn).” The examiner notes that claim 1 uses “consisting” which is a closed transitional phrase that excludes any element, step, or ingredient not specified in the claim. However dependent claim 5 requires the presence of indium in the first oxide semiconductor region. Therefore the metes and bounds of claim 5 are rendered indefinite. For purposes of examination, the examiner has interpreted claim 5 to mean that the first, second, and third oxide semiconductor regions are formed of gallium oxide or zinc oxide materials either of which are doped with silicon or tin.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (USPN 6,603,168 B1, hereinafter “Choi”) in view of Sugihara et al. (United States Patent Application Publication No. US 2006/0244107 A1, hereinafter “Sugihara”) and further in view of Yamasaki et al. (United States Patent Application Publication No. US 2010/0218822 A1, hereinafter “Yamasaki”) and further in view of Miyanaga et al. (United States Patent Application Publication No. US 2011/0084272 A1, hereinafter “Miyanaga”).
In reference to claim 1, Choi discloses a similar device. Figures 1-13 of Choi disclose a semiconductor device which comprises a first electrode (48), a second electrode (23), and a first semiconductor region (44) provided between the first electrode (48) and the second electrode (23). A second semiconductor region (42) is provided between the first semiconductor region (44) and the second electrode (23). A third semiconductor region (46) is provided between the first semiconductor region (44) and the second semiconductor region (42). The third semiconductor region (46) includes a first portion (left and right portions of 46) and a second portion (central portion of 46) surrounded by the first portion (left and right portions of 46). A gate electrode (52) is provided next to the third semiconductor region (46). A gate insulating layer (51) is provided between the third semiconductor region (46) and the gate electrode (52). A first distance between the first electrode (48) and the first portion (left and right portions of 46) between which the first semiconductor region (44) is sandwiched is larger than a second distance between the first electrode (48) and the second portion (central portion of 46) between which the first semiconductor region (44) is sandwiched. A third distance between the second electrode (23) and the first portion (left and right portions of 46) between which the second semiconductor region (42) is sandwiched is larger than a fourth distance between the second electrode (23) and the second portion (central portion of 46) between which the second semiconductor region (42) sandwiched is larger than a fourth distance between the second electrode (23) and the second portion (central portion of 46) between which the second semiconductor region (42) is sandwiched.
Choi does not disclose that the first (44), second (42), and third (46) semiconductor regions are made of an oxide semiconductor material. However Sugihara discloses the known use of an oxide semiconductor material such as zinc oxide as the semiconductor material in a transistor (p. 1, paragraphs 16-20). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use zinc oxide as the semiconductor material for the first (44), second (42), and third (46) semiconductor regions in the device disclosed by Choi. In the device of Choi constructed in view of Sugihara, the first (44), second (42), and third (46) semiconductor regions are made of zinc oxide.
Sugihara does not disclose that the first/source (44) and second/drain (42) semiconductor regions comprise tin. However Yamasaki discloses that increasing the concentration of tin in zinc oxide lowers its resistance (p. 10, paragraph 179). Furthermore Miyanaga discloses that lowering the resistance of source and drain regions is desirable in the art (p. 1, paragraph 12). In view of Yamasaki and Miyanaga, it would therefore be obvious to lower the resistance of the first/source (44) and second/drain (42) semiconductor regions by increasing their respective tin concentrations. In the device of Choi constructed in view of Sugihara, Yamasaki, and Miyanaga, the third semiconductor region (46) has a tin concentration of zero.
In reference to claim 3, Yamasaki does not disclose the exact tin concentration as that claimed by the applicant. However Yamasaki makes it clear that the tin concentration of zinc oxide directly affects its resistance (p. 10, paragraph 179). Thus Yamasaki makes it clear that the tin concentration is a result effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the indium concentration, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore claim 3 is not patentable over Choi, Sugihara, Yamasaki, and Miyanaga.
With regard to claim 4, in the device of Choi constructed in view of Sugihara, Yamasaki, and Miyanaga, the third oxide semiconductor region (46) and the first electrode (48) are spaced apart from each other. The third oxide semiconductor region (46) and the second electrode (23) are spaced apart from each other.
So far as understood in claim 5, in the device of Choi constructed in view of Sugihara, Yamasaki, and Miyanaga, the first (44), second (42), and third (46) semiconductor regions are made of zinc oxide which includes zinc.
Claims 6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Hergenrother et al. (USPN 6,027,975, hereinafter “Hergenrother”) and further in view of Miki and further in view of Kawashima et al. (United States Patent Application Publication No. US 2019/0378859 A1, hereinafter “Kawashima”).
In reference to claim 6, Choi discloses a similar device. Figures 1-13 of Choi disclose a semiconductor device which comprises a first electrode (48), a second electrode (23), and a first semiconductor region (44) provided between the first electrode (48) and the second electrode (23). A second semiconductor region (42) is provided between the first semiconductor region (44) and the second electrode (23). A third semiconductor region (46) is provided between the first semiconductor region (44) and the second semiconductor region (42). The third semiconductor region (46) includes a first portion (left and right portions of 46) and a second portion (central portion of 46) surrounded by the first portion (left and right portions of 46). A gate electrode (52) surrounds the third semiconductor region (46). A gate insulating layer (51) is provided between the third semiconductor region (46) and the gate electrode (52). A first distance between the first electrode (48) and the first portion (left and right portions of 46) between which the first semiconductor region (44) is sandwiched is larger than a second distance between the first electrode (48) and the second portion (central portion of 46) between which the first semiconductor region (44) is sandwiched. A third distance between the second electrode (23) and the first portion (left and right portions of 46) between which the second semiconductor region (42) is sandwiched is larger than a fourth distance between the second electrode (23) and the second portion (central portion of 46) between which the second semiconductor region (42) sandwiched is larger than a fourth distance between the second electrode (23) and the second portion (central portion of 46) between which the second semiconductor region (42) is sandwiched.
Choi does not disclose that the first (44), second (42), and third (46) semiconductor regions are made of an oxide semiconductor material. However Miki discloses the known use of an oxide semiconductor material comprising indium, zinc, gallium, and tin as the semiconductor material in a transistor (p. 1, paragraph 3, p. 2, paragraph 14). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use an oxide semiconductor material for the first (44), second (42), and third (46) semiconductor regions in the device disclosed by Choi.
In the device of Choi constructed in view of Miki, neither of the references disclose that concentrations of oxide vacancy in the first oxide semiconductor/source region (44) and the second oxide semiconductor/drain region (42) are higher than the concentration of oxide vacancy of the third oxide semiconductor/channel region (46). Choi incorporates Hergenrother by reference (column 4, lines 17-23, column 5, lines 6-10) such that the techniques used to make the transistor in fig. 3P of Hergenrother are also used to make the device in fig. 1-13 of Choi. Hergenrother discloses that the third semiconductor region (260 – fig. 3P of Hergenrother) has a conductivity type that is opposite to that of the first (233) and second (232) semiconductor regions (column 11, lines 46-48). Hergenrother discloses that the first (233) and second (232) semiconductor regions have n-type conductivity (column 8, lines 35-38). Kawashima discloses the known technique of forming oxygen/oxide vacancies in an oxide semiconductor material in order to form n-type source and drain regions (p. 4, paragraph 86, p. 18, paragraph 333). It would be obvious form an n-type first oxide semiconductor/source region (44) and an n-type second oxide semiconductor/drain region (42) by generating oxygen/oxide vacancies in the oxide semiconductor material in the device of Choi constructed in view of Hergenrother and Miki since choosing from a finite number of identified, predictable solutions ("obvious to try") with a reasonable expectation of success have been found to be obvious. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Therefore in the device of Choi constructed in view of Hergenrother, Miki, and Kawashima, the n-type first oxide semiconductor/source region (44) and the n-type second oxide semiconductor/drain region (42) both have a higher concentration of oxygen/oxide vacancies than the p-type third oxide semiconductor/channel region (46).
With regard to claim 8, in the device of Choi constructed in view of Hergenrother, Miki, and Kawashima, the third oxide semiconductor region (46) and the first electrode (48) are spaced apart from each other. The third oxide semiconductor region (46) and the second electrode (23) are spaced apart from each other.
In reference to claim 9, in the device of Choi constructed in view of Hergenrother, Miki, and Kawashima, the first (44) and second (42) oxide semiconductor regions are formed of indium and tin (Miki - p. 2, paragraph 14) thus meeting the claim.
With regard to claim 10, in the device of Choi constructed in view of Hergenrother, Miki, and Kawashima, the first (44), second (42), and third (46) oxide semiconductor regions are formed of indium, gallium, and zinc (Miki - p. 1, paragraph 3).
Response to Arguments
Applicant's arguments filed June 16, 2025 have been fully considered but they are not persuasive. The applicant has amended claim 1 to remove limitations regarding the relative concentration of elements (and which elements) that are in the first, second, and third oxide semiconductor regions. However the above Office action addresses these new limitations with the newly cited Sugihara and Yamasaki references which respectively disclose the use of zinc oxide in a transistor (Sugihara - p. 1, paragraphs 16-20) and tin within a zinc oxide material (Yamasaki - p. 10, paragraph 179). The applicant has amended claim 6 to now describe the concentrations of oxide vacancy in the first, second, and third oxide semiconductor regions. However the above Office action addresses these new limitations with the newly cited Kawashima reference which discloses the known technique of forming n-type regions in an oxide semiconductor material with oxygen/oxide vacancies (Kawashima - p. 4, paragraph 86, p. 18, paragraph 333). Therefore claims 1, 3-6, and 8-10 stand rejected in the above Office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893