DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amendments made to the title describe the inventive concept of the application. The amendments are thus curative. The objection is withdrawn.
Response to Arguments
Applicant’s arguments concerning the amendments made to the claims, with respect to the rejection of claim 9 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of U.S. Pat. Pub. No. US 20080179710 A1 to Yip et al.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9, 11, 13, 15-18, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. US 20140004685 A1 to Chowdhury et al. (hereinafter “Chowdhury”) in view of U.S. Pat. Pub. No. US 20080179710 A1 to Yip et al. (hereinafter “Yip”) as evidenced by Warpage simulation by the CTE mismatch in blanket structured wafer level 3D packaging to Kim et al.
Regarding claim 9, Chowdhury teaches a semiconductor carrier (abstract) in fig. fig. 4E, comprising:
a process carrier (408) [0038];
a plurality of slice units (414a and 414b hereinafter “units”) [0052] connected on a surface (top surface) of the process carrier (408) and tiled (disposed in a grid) with one another, wherein each of the slice units (units) includes a substrate (414a or 414b or 400 depending on grouping hereinafter “substrate”) [0031] & [0056] with an outline (shape of process carrier 408), and a gap (416 and 412) [0052] is formed between adjacent two of the slice units (units); and
a sealing material filled in the gap between the adjacent two of the slice units, wherein the sealing material is a passivation layer, a coefficient of thermal expansion (CTE) of the sealing material approaches a CTE of the substrate,
wherein each of the slice units (units) is made by a wafer (414a or 414b or 400 hereinafter “wafer”), and a CTE of the process carrier (408) approaches a CTE of the substrate (substrate) [0039].
Chowdhury does not teach a sealing material filled in the gap between the adjacent two of the slice units, wherein the sealing material is a passivation layer,
Yip, however, teaches wafer production (abstract) with a sealing material filled (stress absorbing material; claim 1) in the gap (trench; claim 1) between the adjacent two of the slice units (adjacent die areas; claim 1), wherein the sealing material (stress absorbing material) is a passivation layer (stress mitigation),
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor carrier of Chowdhury to comprise a passivating sealing material between adjacent slice units to mitigate stress as taught by Yip in claim 1.
Chowdhury in view of Yip does not teach a coefficient of thermal expansion (CTE) of the sealing material approaches a CTE of the substrate.
It is known to the POSITA, however, that CTE mismatch may expose the substrate i.e., sliced units which may be a final product, to deforming stress, thus resulting in warpage. Such assertions are evidenced by Warpage simulation by the CTE mismatch in blanket structured wafer level 3D packaging to Kim et al., abstract. The POSITA would have sufficient evidence, as it is common knowledge in the art, to choose a material for the sealing material which approaches the CTE of the substrate for this reason. M.P.E.P. 2144.07
Regarding claim 11, Chowdhury in view of Yip teaches the semiconductor carrier of claim 9 in fig. 4E, further comprising an adhesive (406) formed between the slice units (units) and the process carrier (408).
Regarding claim 13, Chowdhury in view of Yip teaches the semiconductor carrier of claim 9 in fig. 4E, wherein the process carrier (408) is made of glass [0039].
Regarding claim 15, Chowdhury in view of Yip teaches the semiconductor carrier of claim 9 in fig. 4F, wherein the substrate (substrate) of each of the slice units (units) is a bare substrate (having no active device; see fig. 4F).
Regarding claim 16, Chowdhury in view of Yip teaches the semiconductor carrier of claim 9 in fig. 4E, wherein tops (402) [0031] of the slice units (units) are planarized (having a flat surface).
Regarding claim 17, Chowdhury in view of Yip teaches the semiconductor carrier of claim 9 in fig. 4E, wherein the slice units (units) are accomplished with circuits (ICs; the units 414a and 414b are initially referred to as portions and later as ICs, see [0052] & [0056]). To further clarify, the units 414a and 414b are interpreted as initially comprising a portion of the structure which are later are used to facilitate the formation of integrated circuits (ICs), thus reading on the phrase “accomplished with circuits.”
Regarding claim 18, Chowdhury in view of Yip teaches the semiconductor carrier of claim 9 in fig. 4E, wherein one or more of the circuited slice units (units) includes a thin film [0032] circuit (414A and 414B disclosed as ICs) [0056].
Regarding claim 20, Chowdhury in view of Yip teaches the semiconductor carrier of claim 17 in fig. 4G & 4H, formed by turning the circuited slice units (units) into pieces individually with each other [0056].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chowdhury’s embodiment in fig. 4A-I in view of Yip and further in view of Chowdhury’s embodiment in fig. 2B
Regarding claim 19, Chowdhury does not teach the semiconductor carrier of claim 9 in fig. 4E, wherein one or more of the circuited slice units (units) include a transistor.
Chowdhury, however, teaches the semiconductor carrier (214) in fig. 2B, wherein one or more of the circuited slice units (208, 206, and 204) [0031], [0033], & [0043] include a transistor [0036].
It would have been obvious to a POSITA before the effective filing date of the invention, to modify the ICs of Chowdhury present in the embodiment of fig. 4E with a transistor as taught by Chowdhury as related to the embodiment of fig. 2B to accomplish a completed CMOS device or other transistor-containing device as taught by Chowdhury in [0036].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chowdhury in view of Yip as evidenced by Polymer Science and Technology to Clair et al.
Regarding claim 12, Chowdhury in view of Yip does not explicitly disclose the semiconductor carrier of claim 11 in fig. 4E, wherein the adhesive (406) is made of PI (Polyimide). Chowdhury teaches that the adhesive (406) may be comprised of a UV sensitive material, but is otherwise silent on composition.
The known art, however, recognizes the suitability of Polyimides as adhesives in semiconductors as evidenced by Polymer Science and Technology, by Clair et al., p. 187-188. M.P.E.P. 2144.07.
It would have been obvious to the POSITA before the effective filing date of the invention, to modify the adhesive of Chowdhury with a polyimide adhesive as the art recognizes the suitability of polyimides for the purpose of a semiconductor adhesive. M.P.E.P. 2144.07.
Claims 10 & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chowdhury in view of Yip and further in view of U.S. Pat. Pub. No. US 20190259675 A1 to Shen et al. (hereinafter “Shen”).
Regarding claim 10, Chowdhury in view of Yip is silent in teaching that the each of the slice units (units) defines a circumscribed circle (circular shape) sharing a co-center (centered at the same point) with the wafer (wafer).
Shen, however, teaches a semiconductor carrier (abstract) in fig. 4A, wherein each of the slice units (separated by 202) defines a circumscribed circle (circular shape) sharing a co-center (centered at the same point) with the wafer (206).
It would have been obvious to the POSITA before the effective filing date of the invention, to modify the slice units of Chowdhury to define a circumscribed circle sharing a co-center with the wafer to allow for larger semiconductor packages to be produced as taught by Shen in [0058].
Regarding claim 14, Chowdhury in view of Yip does not explicitly teach the semiconductor carrier of claim 9 in fig. 4E wherein in the step of providing the slice units (units) on the process carrier (408), wherein the substrate (substrate) of each of the slice units (units) defines a thickness, which is greater than 0.4 mil or is no greater than 100 µm.
Shen, however, teaches the semiconductor carrier fig. 2B, wherein in the step of providing the slice units (separated by 202) on the process carrier (204), wherein the substrate (206) of each of the slice units (separated by 202) defines a thickness, which is greater than 0.4 mil [0032] & [0041] or is no greater than 100 µm.
It thus would have been obvious to the POSITA before the effective filing date of the invention, to modify the substrate of Chowdhury to have a thickness as taught by Shen in [0032] to allow the substrate to comprise “thousands of chips,” thus increasing circuit density as taught by Shen in [0032].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892