DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 02/24/2026 amendments of claims 1, 5, 11 and 29-30 has been noted and entered.
The 02/24/2026 addition of new claims 33-34 has been noted and entered.
The 02/24/2026 cancellation of claims 26-27 has been noted and entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/31/2026 was filed after the mailing date of the application on 05/03/2022. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see Remarks pages 9-10, filed 02/24/2026, with respect to the rejection(s) of claim(s) 1-7,11-13,21-24 and 26-32 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Hsu et al, US 20230215801 A1 (Hsu).
New Grounds of Rejection
New grounds of rejection, prior art reference Hsu et al, US 20230215801 A1 (Hsu), appears below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations indicate limitations that are not explicitly disclosed by the primary references but are disclosed by the secondary reference(s).
Claims 1-2, 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al, US 20210407907 A1 (Yoo) in view of Hsu et al, US 20230215801 A1 (Hsu).
Regarding claim 1; Yoo teaches a connection structure of an integrated circuit (Yoo: Fig (2B): 201), the connection structure comprising:
a lower metal line (210) in a lower metal layer (layer containing the line (210)), the lower metal line (210) extending in a 1st direction (X-direction – left-to-right) on a top surface of a transistor structure (205; 206);
a top via (215) in a 1st layer (220) above the lower metal layer (210), the top via (215) being vertically protruded from the lower metal line (210) in a pillar shape and connected to the lower metal line (210), the top via (215) having a width smaller than the lower metal line (210) in the 1st direction (X-direction – left-to-right); and
a super via on the top via, the super via being connected to the top via, wherein the super via penetrates through a 2nd layer, on the 1st layer, and a 3rd layer on the 2nd layer, wherein each of the 2nd layer and the 3rd layer is a layer where at least one metal line or at least one via is configured to be formed, and wherein the super via comprises a sidewall that extends continuously between an upper end and a lower end of the super via and is free of any stepped portions.
Yoo does not teach a super via on the top via, the super via being connected to the top via, wherein the super via penetrates through a 2nd layer, on the 1st layer, and a 3rd layer on the 2nd layer, wherein each of the 2nd layer and the 3rd layer is a layer where at least one metal line or at least one via is configured to be formed, and wherein the super via comprises a sidewall that extends continuously between an upper end and a lower end of the super via and is free of any stepped portions.
Hsu teaches a super via (Hsu: Fig (2): SV1) on the top via (M1), the super via (SV1) being connected to the top via (M1), wherein the super via (SV1) penetrates through a 2nd layer (24), on the 1st layer (14), and a 3rd layer (34) on the 2nd layer (24), wherein each of the 2nd layer (24) and the 3rd layer (34) is a layer where at least one metal line (M2; M3) or at least one via is configured to be formed, and wherein the super via (SV1) comprises a sidewall that extends continuously between an upper end and a lower end of the super via (SV1) and is free of any stepped portions.
Yoo and Hsu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo by using the super via structure disclosed in Hsu to enable the connection of multiple layers of components within the device leading to a higher density of components which leads to higher performance of the device.
Regarding claim 2; Yoo in view of Hsu teaches all the limitations of the connection structure of claim 1.
However, Yoo does not teach further comprising a metal line or another top via in the 2nd layer, wherein the metal line or the other top via is insulated from the super via, and wherein a height in a vertical direction of the metal line or the other top via is less than a height in the vertical direction of the super via.
Hsu teaches further comprising a metal line (Hsu: Fig (2): M2) or another top via in the 2nd layer (24), wherein the metal line (M2) or the other top via is insulated from the super via (SV1), and wherein a height in a vertical direction (Y-direction) of the metal line (M2) or the other top via is less than a height in the vertical direction (Y-direction) of the super via (SV1).
Yoo and Hsu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo by introducing the other metal line or top via insulated from the super via as disclosed in Hsu to achieve the predictable result of making establishing electrical connections between different components of the device easier leading to a more efficient device production process.
Regarding claim 5; Yoo in view of Hsu teaches all the limitations of the connection structure of claim 1.
However, Yoo does not teach further comprising an upper metal line in an upper metal layer on the 3rd layer, the upper metal line being vertically connected to the super via, wherein an uppermost portion of the sidewall of the super via is substantially aligned with a sidewall of the upper metal line in a vertical direction.
Hsu teaches further comprising an upper metal line (Hsu: Fig (2): M3) in an upper metal layer (the layer that contains (M3)) on the 3rd layer (34), the upper metal line (M3) being vertically connected to the super via (SV1), wherein an uppermost portion of the sidewall of the super via (SV1) is substantially aligned with a sidewall of the upper metal line (M3) in a vertical direction.
Yoo and Hsu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo by adding the upper metal line as disclosed in Hsu to make connecting the different layers of components within the device easier leading to a more efficient device production process.
Regarding claim 7; Yoo in view of Hsu teach all the limitations of the connection structure of claim 1.
However, Yoo does not teach further comprising 1st to 3rd interlayer dielectric (ILD) structures in the 1st to 3rd layers, respectively, wherein the 1st to 3rd ILD structures are on sidewalls of the top via and the super via.
Hsu teaches further comprising 1st to 3rd interlayer dielectric (ILD) structures in the 1st (Hsu: Fig (2): 14) to 3rd (34) layers, respectively, wherein the 1st to 3rd ILD structures are on sidewalls of the top via (M1) and the super via (SV1).
Yoo and Hsu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo by introducing the interlayer dielectric structures disclosed in Hsu to improve the isolation of the vias and different conductive connections of the device to protect against short circuit incidents leading to a more reliable device.
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al, US 20210407907 A1 (Yoo) in view of Hsu et al, US 20230215801 A1 (Hsu) in further view of Xie US, 20230132353 A1 (Xie).
Regarding claim 21; Yoo in view of Hsu teaches all the limitations of the connection structure of claim 1.
However, Yoo in view of Hsu does not teach wherein the top via and the lower metal line are a continuous metal structure without a connection surface therebetween.
Xie teaches wherein the top via (Xie: Annotated Fig (16) shared in this OA: Top Via = VBPR+109) and the lower metal line (105) are a continuous metal structure without a connection surface therebetween.
Yoo in view of Hsu and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo in view of Hsu by making the top via and lower metal line continuous without a separating interface between them as disclosed in Xie to reduce the contact resistance that results from such connection structures leading to a more efficient device.
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Regarding claim 22; Yoo in view of Hsu in further view of Xie teach all the limitations of the connection structure of claim 21.
However, Yoo in view of Hsu does not teach wherein the continuous metal structure is formed of ruthenium (Ru).
Xie teaches wherein the continuous metal structure is formed of ruthenium (Ru) (Xie: Annotated Fig (16) shared in this OA: 105; 107; 109; [0058])
Yoo in view of Hsu and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo in view of Hsu by making the metal line and the contentious metal structure out of ruthenium as disclosed in Xie to improve the conductivity of the connection and protect against effect of high temperatures of operations leading to a more reliable device.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al, US 20210407907 A1 (Yoo) in view of Hsu et al, US 20230215801 A1 (Hsu) in further view of Feild et al, US 6433436 B1 (Feild).
Regarding claim 28; Yoo in view of Hsu teach all the limitations of claim 1.
However, Yoo does not teach further comprising 1st to 3rd interlayer dielectric (ILD) structures in the 1st to 3rd layers, respectively, wherein the 1st ILD structure is on a sidewall of the top via, and wherein a barrier metal line is between the sidewall of the top via and the 1st ILD structure.
Hsu teaches further comprising 1st (Hsu: Fig (2): 14) to 3rd (34) interlayer dielectric (ILD) structures in the 1st (14) to 3rd (34) layers, respectively, wherein the 1st (14) ILD structure is on a sidewall of the top via (M1), and wherein a barrier metal line is between the sidewall of the top via and the 1st ILD structure.
Yoo in view of Hsu teach the limitations of the interlayer dielectric structures and their layout with respect to the top via but fails to disclose a barrier metal line. Thus, Yoo in view of Hsu does not teach wherein a barrier metal line is between the sidewall of the top via and the 1st ILD structure.
Feild teaches wherein a barrier metal line (Field: Fig (4e): 210) is between the sidewall of the top via (204’) and the 1st ILD structure (208).
Yoo in view of Hsu and Feild are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo in view of Hsu by using the barrier layer as disclosed in Feild to reduce the risk of metal particles of the via diffusing into the semiconductor structure and thus leading to a more reliable device.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al, US 20210407907 A1 (Yoo) in view of Hsu et al, US 20230215801 A1 (Hsu) ) in further view of Xie US 20230132353 A1 (Xie) in further view of Zhu et al, US 20210125862 A1 (Zhu).
Regarding claim 23; Yoo in view of Hsu in further view of Xie teaches all the limitations of the connection structure of claim 21.
However, Yoo does not teach further comprising 1st to 3rd interlayer dielectric (ILD) structures in the 1st to 3rd layers, respectively, wherein the 1st to 3rd ILD structures are on a sidewall of the top via and the super via, and wherein no barrier metal line is formed between the sidewall of the top via and the 1st ILD structure.
Hsu teaches further comprising 1st (Hsu: Fig (2): 14) to 3rd (34) interlayer dielectric (ILD) structures in the 1st (14) to 3rd (34) layers, respectively, wherein the 1st (14) to 3rd (34) ILD structures are on a sidewall of the top via (M1) and the super via (SV1), and wherein no barrier metal line is formed between the sidewall of the top via and the 1st ILD structure.
Yoo and Hsu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo by using the dielectric interlayer structure disclosed in Hsu to improve the insulation of the different conductive parts of the device from each other leading to a more reliable device.
Yoo in view of Hsu in further view of Xie teaches the layout of the interlayer dielectric layers and their positions relative to the top via and the super via but fails to disclose explicitly the absence of a barrier layer between these conductive structures and the interlayer dielectric layers. Thus, Yoo in view of Hsu in further view of Xie does not teach wherein no barrier metal line is formed between the sidewall of the top via and the 1st ILD structure.
Zhu teaches wherein no barrier metal line (Zhu: [0007]) is formed between the sidewall of the top via (Fig (2): 221) and the 1st ILD structure (150).
Yoo in view of Hsu in further view of Xie and Zhu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, for a person with ordinary skill in the art, to modify Yoo in view of Hsu in further view of Xie by eliminating the barrier layer as disclosed in Zhu to simplify the production process of the device and make it more efficient.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al, US 20210407907 A1 (Yoo) in view of Hsu et al, US 20230215801 A1 (Hsu) in further view of Lin et al, US 20200098591 A1 (Lin).
Regarding claim 4; Yoo in view of Hsu discloses all the limitations of the connection structure of claim 1.
However, Yoo in view of Hsu does not teach wherein the lower metal line comprises a contact structure connected to a gate electrode or a source/drain region of the transistor structure.
Lin teaches wherein the lower metal line (Lin: Fig (4G): 480) comprises a contact structure (470) connected to a gate electrode or a source/drain region (area to which (430) is connected) of the transistor structure (420).
Yoo in view of Hsu and Lin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to modify Yoo in view of Hsu by constructing the contact structure as disclosed in Lin to connect the metal line to the transistor structure to facilitate establishing electrical connections between the different device components making the device production process more efficient.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al, US 20210407907 A1 (Yoo) in view of Hsu et al, US 20230215801 A1 (Hsu) in further view of Xie US 20230132353 A1 (Xie) in further view of Lin et al, US 20200098591 A1 (Lin).
Regarding claim 6; Yoo in view of Hsu disclose all the limitations of the connection structure of claim 5.
However, Yoo in view of Hsu does not teach wherein the upper metal line comprises a power line connected to a voltage source, and wherein the upper metal layer is directly on the 3rd layer.
Xie teaches wherein the upper metal line (Xie: Fig (16): M4) comprises a power line connected to a voltage source ([0035]) and wherein the upper metal layer (M4) is directly on the 3rd layer (141).
Yoo in view of Hsu and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoo in view of Hsu by introducing the upper metal line being connected to a voltage source as disclosed in Xie to simplify power delivery to the device components.
Yoo in view of Hsu in further view of Xie teach all the above claimed subject matter regarding the connection structure, the layout of the different elements and the role that the upper metal line plays but fails to disclose the details pertaining to the lower metal line. Thus, Yoo in view of Hsu in further view of Xie does not teach wherein the lower metal line comprises a contact structure connected to a gate electrode or a source/drain region of the transistor structure.
Lin teaches teach wherein the lower metal line (Lin: Fig (4G): 480) comprises a contact structure (470) connected to a gate electrode or a source/drain region (area to which (430) is connected) of the transistor structure (420).
Yoo in view of Hsu in further view of Xie and Lin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to modify Yoo in view of Hsu in further view of Xie by constructing the contact structure as disclosed in Lin to connect the metal line to the transistor structure to facilitate establishing electrical connections between the different device components making the device production process more efficient.
Allowable Subject Matter
Claims 11-13, 24 and 29-34 are allowed over prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11; Yoo in view of Hsu in further view of Lin in further view of Feild disclose a semiconductor device comprising: a transistor structure; a 1st layer on a top surface of the transistor structure; a 1st metal line extending in a 1st direction, in the 1st layer, connected to the transistor structure; a top via, in a 2nd layer on the 1st layer, connected to the 1st metal line, the top via being vertically protruded from the 1st metal line in a pillar shape, the top via having a width smaller than the 1st metal line in the 1st direction; a super via comprising a lower portion in a 3rd layer on the 2nd layer and an upper portion in a 4th layer on the 3rd layer, the super via being connected to the top via; a 2nd metal line, in a 5th layer on the 4th layer, connected to the super via; and 1st, 2nd, 3rd, and 4th interlayer dielectric (ILD) structures in the 2nd 3rd 4th and 5th layers, respectively, wherein the 1st ILD structure is on a sidewall of the top via, the 2nd ILD structure is on a sidewall of the lower portion of the super via, and the 3rd ILD structure is on a sidewall of the upper portion of the super via.
However, Yoo alone or in combination with any other available art dies not disclose wherein a barrier metal line extends on a top surface of the top via between the top via and the super via, extends on the sidewall of the lower portion of the super via between the super via and the 2nd ILD structure, and extends on the sidewall of the upper portion of the super via between the super via and the 3rd ILD structure, and wherein no barrier metal line is formed between the sidewall of the top via and the 1st ILD structure in combination with the above listed limitations.
Claims 12-13, 24 and 33-34 are allowable for their dependence on an allowable base claim (claim 11)
Regarding claim 29; Yoo in view of Hsu in further view of Lin in further view of Field teaches a semiconductor device comprising: a transistor structure; a 1st metal line in a 1st layer on a top surface of the transistor structure and connected to the transistor structure, the 1st metal line extending in a 1st direction; a top via in a 2nd layer on the 1st layer and connected to the 1st metal line, the top via vertically protruding from the 1st metal line and having a width in the 1st direction smaller than that of the 1st metal line; a super via comprising a lower portion in a 3rd layer on the 2nd layer and an upper portion in a 4th layer on the 3rd layer; and a 2nd metal line or a 2nd via in the 3rd layer and spaced apart from the super via, wherein the super via is on a top surface of the top via and is connected to the top via.
However, Yoo alone or in combination with any other available art does not teach and wherein a bottom surface of the 2nd metal line or the 2nd via is substantially coplanar with a bottom surface of the super via, and a top surface of the 2nd metal line or the 2nd via is non- coplanar with a top surface of the super via in combination with the rest of the limitations detailed above.
Claims 30-32 are allowable for their dependence on an allowable base claim (claim 29).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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