DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/13/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on the same interpretation of the prior art in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s assertions (Applicant’s Remarks pages 8-9) that the silicide layer 262 of US 20220165848 A1 (Lin et al) does not have a first and second portion consistent with the amended claim limitations are acknowledged. However, the Examiner respectfully disagrees: when the first portion is considered as the portion of the silicide layer on sidewalls of the uppermost row of channel layers, and the second portion is considered as the portion of the silicide layer on sidewalls of the middle row of channel layers, the prior art is consistent with the limitations of claim 1.
Applicant’s arguments, see Applicant’s Remarks pages 10-11, filed 4/13/2026, with respect to claims 10 and 21 have been fully considered and are persuasive. The rejections of those claims and their dependent claims have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20220165848 A1 (Lin et al hereinafter Lin) in view of US 20220199797 A1 (Naskar et al hereinafter Naskar).
Regarding claim 1, Lin discloses a method of forming a nanosheet field effect transistor (FET) device (the disclosed method illustrated in FIGS. 1-16 for forming workpiece/device 200 ¶ [0005-0006]), comprising: etching a nanosheet stack of the nanosheet FET device (FIG. 3, layers 206/208 are etched to form separate stacks at channel regions 204C ¶ [0018]) to form a source/drain region (FIG. 3, the 204S source region ¶ [0014]), the nanosheet stack comprising alternating layers of a plurality of nanosheet channel layers (FIG. 2, channel layers 208 ¶ [0014]) and a plurality of sacrificial nanosheet layers (FIG. 2, sacrificial layers 206 ¶ [0014]); forming inner spacers (FIGS. 1-3, inner spacers 218 are formed adjacent to sacrificial layers 206 ¶ [0019]) adjacent to the plurality of sacrificial nanosheet layers.
Lin does not explicitly show the forming of a plurality of first source/drain regions and a plurality of second source/drain regions (their illustrations are limited to a single instance of the pertinent structure). However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to duplicate the structure shown in workpiece 200 (¶ [0013-0014]) in a device since the possibility is suggested by Lin (“Two dummy gate stacks 210 are shown in FIG. 2 but the workpiece 200 may include more dummy gate stacks 210” ¶ [0014]), in order to multiplicatively increase the device’s functionality. For example, four instances of the illustrated structure of workpiece 200 could be arranged in the device wherein the first two instances include a plurality of first source/drain regions (FIGS. 2-16, the two 204S regions of the first two instances of workpiece 200), and the second two instances include a plurality of second source/drain regions (FIGS. 2-16, the two 204S regions of the second two instances of workpiece 200). It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co , 193 USPQ 8. (See also MPEP 2144 VI. B).
In view of the described duplication of parts, Lin further discloses depositing a silicide layer (FIG. 11, silicide layer 262 is deposited ¶ [0031]) in the plurality of first source/drain regions (the first two instances of the illustrated structure workpiece 200 have the silicide layer deposited), wherein a first portion of the silicide layer is deposited on sidewalls of the plurality of nanosheet channel layers (FIG. 11, silicide layers 262 are in the first source/drain regions 204S and at sidewalls of uppermost row of channel members 2080, which are the channel layers ¶ [0026]) via a selective silicidation process (the silicidation process is selective to the regions where the metal layer contacts the epitaxial 226 to form the silicide layer 262 by the annealing process ¶ [0031]; the present application has not detailed a more specific interpretation of the term “selective silicidation” for a person of ordinary skill in the art) to control a channel length of the plurality of nanosheet channel layers between adjacent first source/drain regions (the structure of the channel and silicide inherently controls the channel length); and a second portion of the silicide layer (FIG. 11, silicide layers 262 at sidewalls of middle row of channel members 2080 form a second portion separate from the first portion), separate from the first portion, is deposited horizontally across respective first source/drain regions over a lowermost surface of the plurality of first source/drain regions (FIG. 11, silicide layers 262 at sidewalls of middle row of channel members 2080 extend horizontally across the source/drain regions 204S and are located over the lowermost surface of regions 204S), wherein the second portion of the silicide layer is entirely disposed above a lowermost surface of the nanosheet stack (FIG. 11, silicide layers 262 at sidewalls of middle row of channel members 2080 are entirely above the lowermost surface of nanosheet stack including channel members 2080); and performing a metal fill process (FIG. 11, a metal fill process forms source contact 260 in the first two instances of the illustrated structure of workpiece 200 ¶ [0030]) to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer of the plurality of nanosheet channel layers (FIG. 11, contact 260 extends to lowermost nanosheet channel 2080) to above an uppermost nanosheet channel layer of the plurality of nanosheet channel layers (FIG. 11, contact 260 extends to uppermost nanosheet channel 2080).
Lin does not disclose that adjacent to the plurality of first source/drains regions, the inner spacers extend into the plurality of first source/drain regions beyond sidewalls of the plurality of nanosheet channel layers. In the disclosure of Lin, the inner spacers are flush with the sidewalls of the plurality of nanosheet channel layers (FIGS. 1-3, inner spacers 218 and channel layers 208).
However, Naskar discloses a method of forming a nanowire transistor device (the device of FIGS. 1A-1F ¶ [0003-0008]) comprising a plurality of first source/drain regions (FIGS. 1A and 1C, epitaxial source/drain structures 108, 110, 122, and 124 ¶ [0060-0061, 0078]) wherein inner spacers (FIG. 1A, spacers 114 ¶ [0060]) extend into the plurality of first source/drain regions beyond sidewalls of a plurality of nanosheet channel layers (FIG. 1A, spacers 114 extend past sidewalls of channel layers 104/106 ¶ [0060]). Naskar also discloses an embodiment wherein the convex sidewalls of the inner spacers extend less far into the plurality of source/drain regions than the channel layers (FIG. 1C, sidewalls of spacers 114 extend less far into drain 110 than channel layer 104, ¶ [0068]). Naskar also teaches that the spacers prevent shorting between the gate and the source/drain structures (¶ [0001]), demonstrating a recognized need in the art. Therefore, the prior art having shown each of the finite, predictable solutions to the need of providing inner spacers with a given width relative to the positions of the channel layers (Lin FIG. 3 demonstrates the option of flush sidewalls for the inner spacers and channel layers, and Naskar demonstrates the options where spacer sidewalls extend past the channel layers in FIG. 1A, and where spacer sidewalls extend not as far as the channel layers in FIG. 1C). Since a person of ordinary skill in the art before the effective filing date of the claimed invention would have found that any of the three potential options could be pursued with a reasonable expectation of success, it would have been obvious to try having the inner spacers extend into the plurality of first source/drain regions beyond sidewalls of the plurality of nanosheet channel layers. (MPEP 2143 I. (E))
Lin and Naskar both pertain to the field of nanosheet/nanowire transistors, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to try having the inner spacers extend into the plurality of first source/drain regions beyond sidewalls of the plurality of nanosheet channel layers, since such a configuration and its alternatives have all been taught as viable options by the prior art, in order to form a spacer which prevents shorting between the gate and the source/drain structures.
Regarding claim 2, Lin in view of Naskar discloses the limitations of claim 1 as detailed above and further discloses that prior to depositing the silicide layer (as of FIGS. 4-5, silicide layer 262 is not yet present), performing a controlled epitaxial growth process (FIG. 5, epitaxial source features 226 are grown ¶ [0021]) to deposit silicon or silicon germanium (silicon or doped silicon are suitable materials for an n-type source feature, and doped silicon germanium is a suitable material for a p-type source feature ¶ [0021]) on exposed sidewalls of the plurality of nanosheet channel layers (FIG. 5, epitaxial source features 226 are on exposed sidewalls of channel layers 208 ¶ [0021]) and only partially fill the plurality of first source/drain regions (FIG. 5, epitaxial source features 226 do not fully fill the source region 204S).
Regarding claim 3, Lin in view of Naskar discloses the limitations of claim 2 as detailed above and further discloses that the controlled epitaxial growth process prevents epitaxial merge in the plurality of first source/drain regions (FIG. 5, the portions of epitaxial source features 226 at opposite sidewalls of source opening 2220 do not merge with each other ¶ [0021]; epitaxial merge is therefore prevented).
Regarding claim 6, Lin in view of Naskar discloses the limitations of claim 1 as detailed above and further discloses applying a hard mask (FIG. 7, second mask 230 is a hard mask ¶ [0023]) on the plurality of second source/drain regions (when four instances of the illustrated structure of workpiece 200 are formed as described above, the third and fourth instances being the plurality of second source/drain regions would have the hard mask formed on them) prior to depositing the silicide layer in the plurality of first source/drain regions (the silicide layer is deposited in the plurality of first source/drain regions in the step shown in FIG. 11; the application of the hard mask 230 to the plurality of second source/drain regions occurs before that, in the step shown in FIG. 7).
Regarding claim 7, Lin in view of Naskar discloses the limitations of claim 1 as detailed above and further discloses that the silicide layer includes at least one of titanium, nickel, palladium, molybdenum, platinum, osmium, or iridium (titanium or nickel may be included in silicide layer 262, Lin ¶ [0031]).
Regarding claim 8, Lin in view of Naskar discloses the limitations of claim 1 as detailed above and further discloses depositing a second silicide layer (FIG. 11, silicide layer 262 is deposited ¶ [0031]) in the plurality of second source/drain regions (the second two instances of the illustrated structure workpiece 200 have the silicide layer deposited) on sidewalls of the plurality of nanosheet channel layers (FIG. 11, silicide layers 262 are in the second source/drain regions 204S and at sidewalls of channel members 2080, which are the channel layers ¶ [0026]) disposed in the plurality of second source/drain regions via a selective silicidation process; and performing a second metal fill process (FIG. 11, a second metal fill process forms source contact 260 in the second two instances of the illustrated structure of workpiece 200 ¶ [0030]; as currently claimed, it is not required that the second metal fill be performed at a different time than the metal fill of claim 1, and is considered “second” in the sense that it fills the second source/drain regions whereas the metal fill of claim 1 filled the first source/drain regions) to fill the plurality of second source/drain regions, wherein the second metal fill extends from the lowermost nanosheet channel layer (FIG. 11, contact 260 extends to lowermost nanosheet channel 2080) to above the uppermost nanosheet channel layer (FIG. 11, contact 260 extends to uppermost nanosheet channel 2080).
Regarding claim 9, Lin in view of Naskar discloses the limitations of claim 8 as detailed above and further discloses that prior to depositing the second silicide layer in the plurality of second source/drain regions (as of FIGS. 4-5, silicide layer 262 is not yet present in the second source/drain regions), performing a controlled epitaxial growth process (FIG. 5, epitaxial source features 226 are grown ¶ [0021]) to deposit silicon or silicon germanium (silicon or doped silicon are suitable materials for an n-type source feature, and doped silicon germanium is an option for a p-type source feature ¶ [0021]) on exposed sidewalls of the plurality of nanosheet channel layers disposed in the plurality of second source/drain regions (FIG. 5, epitaxial source features 226 are on exposed sidewalls of channel layers 208 in the second source/drain regions ¶ [0021]) and only partially fill the plurality of second source/drain regions (FIG. 5, epitaxial source features 226 do not fully fill the source region 204S of the second source/drain regions).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Naskar as applied to claim 1 above, and further in view of US patent publication US 20210066137 A1 (Hsu et al hereinafter Hsu).
Lin in view of Naskar discloses the limitations of claim 1 as detailed above, but does not explicitly teach that the plurality of first source/drain regions correspond to pMOS areas of the nanosheet FET device and the plurality of second source/drain regions correspond to nMOS areas of the nanosheet FET device. Lin does teach that the transistors formed by their method may use either n-type or p-type epitaxial source features 226 (¶ [0021]), and that the gate electrode layers may be formed separately for n-type transistors and p-type transistors (¶ [0028]).
Further, Hsu discloses a device (FIGS. 2-20B, integrated circuit 200 and the method of making it ¶ [0004-0008, 0014]) wherein a plurality of first source/drain regions (FIG. 3, S/D regions 207 for nanosheet stacks 210 of the 201P and 202P devices ¶ [0021, 0024-0025]) correspond to pMOS areas of a nanosheet FET device (FIGS. 3-4B, p-type devices 201P and 202P ¶ [0016]) and a plurality of second source/drain regions (FIG. 3, S/D regions 207 for nanosheet stacks 210 of the 201N and 202N devices ¶ [0021, 0024-0025]) correspond to nMOS areas of the nanosheet FET device (FIGS. 3-4B, n-type devices 201N an 202N ¶ [0016]).
Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to try having the plurality of first source/drain regions correspond to pMOS areas (a metal oxide semiconductor transistor structure is present, ¶ [0027-0028]) of the nanosheet FET device and the plurality of second source/drain regions correspond to nMOS areas of the nanosheet FET device in the device of Lin since doing so would require no more than selecting one of the two finite conductivity types (n-type or p-type) for each of the source/drain regions of the first and second pluralities of source/drain regions when solving the problem of selecting a suitable conductivity type to apply in the device of Lin. A person of ordinary skill in the art would also have had a reasonable expectation of success, since it has been demonstrated both by Lin (¶ [0028], detailing the gate electrode layers may be formed separately n-type and p-type transistors) and Hsu (¶ [0016, 0021, 0024-0025], n-type and p-type structures may be formed in the same device) that a combination of n-type and p-type structures is known in the art (MPEP 2143 I. (E)).
Allowable Subject Matter
Claims 10-13 and 21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The invention of claim 10 is directed to a method of forming a nanosheet field effect transistor (FET) device, comprising: forming a nanosheet stack on a substrate, the nanosheet stack comprising alternating layers of nanosheet channel layers and sacrificial nanosheet layers; etching the nanosheet stack of the nanosheet FET device to form a plurality of first source/drain regions and a plurality of second source/drain regions; applying a hard mask on the plurality of second source/drain regions; depositing a silicide layer in the plurality of first source/drain regions at sidewalls of the nanosheet channel layers via a selective silicidation process to control a channel length of the nanosheet channel layers between the first source/drain regions;
performing a metal fill process to fill the plurality of first source/drain regions, wherein the metal fill extends from above an uppermost nanosheet channel layer to a lowermost nanosheet channel layer without extending below a lowermost surface of the nanosheet stack; depositing a silicide layer in the plurality of second source/drain regions at sidewalls of the nanosheet channel layers exposed to the plurality of second source/drain regions via a selective silicidation process to control a length of the nanosheet channel layers between adjacent second source/drain regions; and performing a second metal fill process to fill the plurality of second source/drain regions, wherein the second metal fill extends from the lowermost nanosheet channel layer to above the uppermost nanosheet channel layer.
The claimed material is detailed and specific. The prior art of record discloses the following: US 20220165848 A1 (Lin et al hereinafter Lin) discloses a method of forming a nanosheet field effect transistor (FET) device (the disclosed method illustrates in FIGS. 1-16 ¶ [0005-0006]), comprising: forming a nanosheet stack (FIG. 2, the stack of sacrificial layers 206 and channel layers 208 is formed ¶ [0014]) on a substrate (FIG. 2, substrate 202 ¶ [0014]), the nanosheet stack comprising alternating layers of nanosheet channel layers (FIG. 2, channel layers 208 ¶ [0014]) and sacrificial nanosheet layers (FIG. 2, sacrificial layers 206 ¶ [0014]); etching the nanosheet stack of the nanosheet FET device (FIG. 3, layers 206/208 are etched to form separate stacks at channel regions 204C ¶ [0018]) to form source/drain region (FIG. 3, the 204S source region ¶ [0014]). Lin also suggests a plurality of first source/drain regions and a plurality of second source/drain regions (“Two dummy gate stacks 210 are shown in FIG. 2 but the workpiece 200 may include more dummy gate stacks 210” ¶ [0014]), and further discloses applying a hard mask on the plurality of second source/drain regions (FIG. 8, second mask film 230 is applied onto the second two instances, being the plurality of second source/drain regions ¶ [0023]); depositing a silicide layer (FIG. 11, silicide layer 262 is deposited ¶ [0031]) in the plurality of first source/drain regions at sidewalls of the nanosheet channel layers (FIG. 11, silicide layers 262 are at sidewalls of channel members 2080, which are the channel layers ¶ [0026]) via a selective silicidation process (the silicidation process is selective to the regions where the metal layer contacts the epitaxial 226 to form the silicide layer 262 by the annealing process ¶ [0031]; the present application has not detailed a more narrow interpretation of the term “selective silicidation” for a person of ordinary skill in the art) to control a channel length of the nanosheet channel layers between the first source/drain regions (the structure of the channel and silicide inherently controls the channel length); performing a metal fill process (FIG. 11, a metal fill process forms source contact 260 ¶ [0030]) to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer (FIG. 11, contact 260 extends from lowermost channel member 2080) to above an uppermost nanosheet channel layer (FIG. 11, contact 260 extends above uppermost channel member 2080);
depositing a silicide layer (FIG. 11, silicide layer 262 is deposited ¶ [0031]) in the plurality of second source/drain regions at sidewalls of the nanosheet channel layers (FIG. 11, silicide layers 262 are at sidewalls of channel members 2080, which are the channel layers ¶ [0026]) exposed to the plurality of second source/drain regions via a selective silicidation process (the silicidation process is selective to the regions where the metal layer contacts the epitaxial 226 to form the silicide layer 262 by the annealing process ¶ [0031]; the present application has not detailed a more narrow interpretation of the term “selective silicidation” for a person of ordinary skill in the art) to control a length of the nanosheet channel layers between adjacent second source/drain regions (the structure of the channel and silicide inherently controls the channel length); and performing a second metal fill process (FIG. 11, a metal fill process forms source contact 260 ¶ [0030]) to fill the plurality of second source/drain regions, wherein the second metal fill extends from the lowermost nanosheet channel layer (FIG. 11, contact 260 extends from lowermost channel member 2080) to above the uppermost nanosheet channel layer.
US patent US 9985023 B1 (Liu et al hereinafter Liu) further discloses a configuration of a semiconductor device (the semiconductor device formed by steps illustrated in FIGS. 3A-3J Col. 1 lines 41-43) wherein a hard mask (FIG. 3E, hard mask 250 Col. 8 lines 1-5) is applied directly on top of the metal fill (FIG. 3E, metal fill layer 240 Col. 8 lines 1-5). Further, Huang discloses a nanostructure transistor device (workpiece 200, steps for forming it are shown in FIGS. 2-25) wherein a hard mask (FIG. 18, patterned hard mask 252 ¶ [0039]) is applied over a metal fill (FIG. 18, drain contact 248 ¶ [0037]) in a plurality of first source/drain regions (FIG. 18, drain contact 248 is in regions having electrical contact with drain feature 232D ¶ [0029]). US 20240363705 A1 (Huang et al hereinafter Huang) also teaches that the hard mask applied over the metal fill allows for a gate contact to later be formed in the device since the hard mask is used as an etch mask to form the gate contact opening (¶ [0039]), allowing a gate via to later be formed (FIG. 19, gate via 254 ¶ [0039]) and for an interconnect structure for the gate via to be subsequently formed over the gate via (FIG. 20, interconnect structure 256 ¶ [0040]).
However, the prior art of record does not disclose, alone or in obvious combination, the combined limitations of the claims. In particular, the limitation “the metal fill extends from above an uppermost nanosheet channel layer to a lowermost nanosheet channel layer without extending below a lowermost surface of the nanosheet stack” is not taught or obviously suggested by the prior art of record.
By virtue of their dependence on claim 10, claims 11-13 are also allowed on this basis.
The invention of claim 21 is directed to a method of forming a nanosheet field effect transistor (FET) device, comprising: etching a nanosheet stack of the nanosheet FET device to form a plurality of first source/drain regions and a plurality of second source/drain regions, the nanosheet stack comprising alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers; depositing a silicide layer in the plurality of first source/drain regions at sidewalls of the plurality of nanosheet channel layers via a selective silicidation process to control a channel length of the plurality of nanosheet channel layers between adjacent first source/drain regions;
growing epitaxial material from a lower surface of each of the plurality of first source/drain regions that terminates at a location vertically between a lowermost one of the plurality of sacrificial nanosheet layers and an uppermost one of the plurality of sacrificial nanosheet layers; and performing a metal fill process to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer of the plurality of nanosheet channel layers to above an uppermost nanosheet channel layer of the plurality of nanosheet channel layers.
The claimed material is detailed and specific. The prior art of record discloses the following:
Lin discloses a method of forming a nanosheet field effect transistor (FET) device (the disclosed method illustrated in FIGS. 1-16 for forming workpiece/device 200 ¶ [0005-0006]), comprising: etching a nanosheet stack of the nanosheet FET device (FIG. 3, layers 206/208 are etched to form separate stacks at channel regions 204C ¶ [0018]) to form a source/drain region (FIG. 3, the 204S source region ¶ [0014]), the nanosheet stack comprising alternating layers of a plurality of nanosheet channel layers (FIG. 2, channel layers 208 ¶ [0014]) and a plurality of sacrificial nanosheet layers (FIG. 2, sacrificial layers 206 ¶ [0014]); forming inner spacers (FIGS. 1-3, inner spacers 218 are formed adjacent to sacrificial layers 206 ¶ [0019]) adjacent to the plurality of sacrificial nanosheet layers. Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to duplicate the structure shown in workpiece 200 (¶ [0013- 0014]) in a device since the possibility is suggested by Lin (“Two dummy gate stacks 210 are shown in FIG. 2 but the workpiece 200 may include more dummy gate stacks 210” ¶ [0014]), in order to multiplicatively increase the device’s functionality. For example, four instances of the illustrated structure of workpiece 200 could be arranged in the device wherein the first two instances include a plurality of first source/drain regions (FIGS. 2-16, the two 204S regions of the first two instances of workpiece 200), and the second two instances include a plurality of second source/drain regions (FIGS. 2-16, the two 204S regions of the second two instances of workpiece 200). It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co, 193 USPQ 8. (See also MPEP 2144 VI. B).
In view of the described duplication of parts, Lin further discloses depositing a silicide layer (FIG. 11, silicide layer 262 is deposited ¶ [0031]) in the plurality of first source/drain regions (the first two instances of the illustrated structure workpiece 200 have the silicide layer deposited) at sidewalls of the plurality of nanosheet channel layers (FIG. 11, silicide layers 262 are in the first source/drain regions 204S and at sidewalls of channel members 2080, which are the channel layers ¶ [0026]) via a selective silicidation process (the silicidation process is selective to the regions where the metal layer contacts the epitaxial 226 to form the silicide layer 262 by the annealing process ¶ [0031]; the present application has not detailed a more specific interpretation of the term “selective silicidation” for a person of ordinary skill in the art) to control a channel length of the plurality of nanosheet channel layers between adjacent first source/drain regions (the structure of the channel and silicide inherently controls the channel length); growing epitaxial material from a lower surface of each of the plurality of first source/drain regions (FIG. 6, bottom epitaxial feature 226B and sacrificial epitaxial layer 228 are epitaxial materials which are grown from a lower surface of the 204S regions ¶ [0022]) to a location vertically between a lowermost one of the plurality of sacrificial nanosheet layers and an uppermost one of the plurality of sacrificial nanosheet layers (FIG. 6, a central portion of sacrificial epitaxial layer 228 is grown to a location vertically between a lowermost sacrificial nanosheet 206 and uppermost sacrificial nanosheet 206; the claim did not state that the growth that begins at the lower surface of the source/drain region terminates at the claimed vertical location ¶ [0022]); and performing a metal fill process (FIG. 11, a metal fill process forms source contact 260 in the first two instances of the illustrated structure of workpiece 200 ¶ [0030]) to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer of the plurality of nanosheet channel layers (FIG. 11, contact 260 extends to lowermost nanosheet channel 2080) to above an uppermost nanosheet channel layer of the plurality of nanosheet channel layers (FIG. 11, contact 260 extends to uppermost nanosheet channel 2080).
However, the prior art of record does disclose, alone or in obvious combination, the combined limitations of the claim. In particular, the limitation “growing epitaxial material from a lower surface of each of the plurality of first source/drain regions that terminates at a location vertically between a lowermost one of the plurality of sacrificial nanosheet layers and an uppermost one of the plurality of sacrificial nanosheet layers” is not taught or obviously suggested by the prior art. This finding is based on the assumption that the claimed “location” being “vertically between a lowermost one of the plurality of sacrificial nanosheet layers and an uppermost one of the plurality of sacrificial nanosheet layers” is implied to be above the uppermost surface of the lowermost one of the plurality of sacrificial nanosheet layers.
If it is the case that the “location” may be below the uppermost surface of the lowermost one of the plurality of sacrificial nanosheet layers, then Lin would obviously suggest this feature is included in their disclosure on account of the implication of manufacturing tolerances which would prevent the upper surface of the epitaxial material from being planar as drawn, and likely would extend partially upward along a sidewall of the lowermost one of the plurality of sacrificial nanosheet layers simply on account of the aforementioned limitations to manufacturing precision.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publication US 20200058801 A1 and US patent US 12604501 B2.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813 See attached updated search history for additional information
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