DETAILED ACTION
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-4, and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. PGPub 2021/0035993) in view of Leng (U.S. PGPub 2022/0399352) and Then (U.S. PGPub 2020/0119138).
Regarding claim 1, Chen teaches a method of manufacturing a ferroelectric random-access memory device (Fig. 54, [0097], 350), said method comprising:
forming a first electrode (Fig. 46, 255 in region 120, [0098]), forming a first etch stop layer over and in direct contact with the first electrode (Figs. 49-50, 505/505a, [0099]-[0100]),
forming an intermetal dielectric layer over and in direct contact with the first etch stop layer, said intermetal dielectric layer having a first surface on a first side of the intermetal dielectric layer which is distal from the first electrode (Figs. 48-49, layers 505b and 510, [0100]-[0101]),
creating a first via extending through a thickness of the intermetal dielectric layer, said first via being aligned with the first electrode there beneath and having a side wall which extends from the first surface of the intermetal dielectric layer to an upper surface of the first electrode (Fig. 49, [0101]),
depositing a ferroelectric material over the intermetal dielectric layer such that a ferroelectric layer is formed, including a first part arranged within the first via upon the sidewall and a second part extending laterally out from the first via over the first surface of the intermetal dielectric layer (Fig. 51, 530, [0103]), and
removing the second part of the ferroelectric layer from over the first surface of the intermetal dielectric layer (Fig. 53, [0105]); forming an electrically conductive material layer over the ferroelectric layer including a first part arranged within and filling the first via and a second part extending laterally out from the via over the first surface of the intermetal dielectric layer (Figs. 51-52, 540, [0104]);
applying CMP to remove the second part of the ferroelectric layer and the second part of the electrically conductive material layer from over the first surface of the intermetal dielectric layer such that ends of the ferroelectric layer and the electrically conductive material layer are made co-planar with the first surface of the intermetal dielectric layer (Fig. 53, [0105]).
The embodiment of Fig. 54 is completed with the method of Figs. 35-39 ([0106]). Therefore the method continues, forming a second etch stop layer over the intermetal dielectric layer (Fig. 36, 460, [0086]), forming a low-k material layer over and in direct contact with the second etch stop layer, the low-k material being formed from a material different from the intermetal dielectric layer (IMD 260, [0085], formed by the same materials as low-k IMD 250, [0063]; etch stop materials [0095]), forming a trench and a second via in the low-k material layer, the second via extending through the second etch stop layer to an upper surface of the electrically conductive material layer, and filling the trench and the second via to form a second electrode and an electrically conductive path from the electrically conductive material layer to the second electrode (Figs. 35-39, trench/second via 265o/263o, [0085]-[0086]; second electrode 265, Figs. 38-39, [0087]-[0088]/Fig. 54), wherein the second etch stop layer is formed from a material that is different from the first etch stop layer ([0100], first etch stop layer, silicon carbide, silicon oxide, silicon oxynitride; [0078], second etch stop layer, metal oxide).
Chen does not explicitly teach the first via having a lateral width of about 20 to about 50 nm, and wherein the trench has a lateral width of about 100nm to about 300nm.
Chen teaches the first via having a lateral width of about 5 nm to about 50 nm ([0105], 350; [0112]), wherein the trench width is formed according to the routing design, including widths that are greater than the first via width ([0028], [0032], M5, [0106], Fig. 57, [0112]),
In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05.
Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Chen such that the first via has a lateral width of about 20 to about 50 nm and wherein the trench has a lateral width of about 100nm to about 300nm for the purpose of providing appropriate routing design ([0028]).
Chen further does not explicitly teach the low-k material layer being formed from an SiOC material and the second etch stop layer over and in direct contact with the intermetal dielectric layer and the filled first via.
Chen teaches wherein the low-k material is formed of a carbon-containing low-k dielectric material ([0063]).
Leng teaches wherein an etch stop layer directly contacts an intermetal dielectric and an MFM structure embedded in a via (Fig. 1A, 182, [0055]; 102, [0048]) and wherein the dielectric layer is formed of organosilicate glass ([0077]; OSG is an SiOC material with low-k).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Leng with Chen such that the second etch stop layer directly contacts both the intermetal dielectric layer and the filled first via for the purpose of providing an etch stop layer for forming the metallization layers (Leng, [0055]) for a MFM structure embedded in a dielectric layer (Leng, Fig. 1A; Chen, Fig. 54) and forming the low-k material from an appropriate carbon-containing low-k dielectric material (Chen, [0063]; Leng, [0077]).
Chen and Leng do not explicitly teach where the second electrode is formed of a material different from the first electrode.
Then teaches a MIM capacitor (Fig. 5) comprising a first electrode (132, [0017]), an insulating layer and electrically conductive filling layer deposited in a via (140, V2, [0017]), and a second electrode formed in a trench over the electrically conductive filling layer (M3, [0017]), wherein the second electrode is formed of a material different from the first electrode ([0020] first electrode, TiN, TaN, Al, W, Ni, Pt, etc; [0027] second electrode, Cu, Co, Mo, Ag, Ti, etc).
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date to combine the teachings of Then with Chen and Leng such that the second electrode is formed of a material different from the first electrode for the purpose of choosing appropriate known conductive materials for the electrodes (Then, [0020], [0027]; Chen, [0064], [0028]).
Regarding claim 3, Chen teaches forming a barrier metal layer interposed between at least the first part of the ferroelectric layer and the side wall of the first via formed in the intermetal dielectric layer, said barrier metal layer contacting a first surface of the first electrode (Fig. 51, [0102], 520). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Leng, and Then for the reasons set forth in the rejection of claim 1.
Regarding claim 4, Chen teaches wherein the electrically conductive material layer comprises titanium nitride or tungsten ([0104]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Leng, and Then for the reasons set forth in the rejection of claim 1.
Regarding claim 6, Chen teaches wherein application of the chemical mechanical polishing also makes ends of the barrier metal layer co-planar with the first surface of the intermetal dielectric layer (Fig. 53, [0105]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Leng, and Then for the reasons set forth in the rejection of claim 1.
Regarding claim 7, Chen teaches wherein the ferroelectric material includes hafnium-zirconium oxide ([0103]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Leng, and Then for the reasons set forth in the rejection of claim 1.
Regarding claim 8, Chen teaches wherein the barrier metal layer comprises at least one of tantalum, tantalum nitride, titanium, titanium nitride, and cobalt ([0102]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Leng, and Then for the reasons set forth in the rejection of claim 1.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. PGPub 2021/0035993) in view of Leng (U.S. PGPub 2022/0399352) and Then (U.S. PGPub 2020/0119138) and further in view of Noack (U.S. PGPub 2022/0139933).
Regarding claim 9, Chen does not explicitly teach wherein the method comprises establishing an electrically conductive interconnect between the first electrode and a gate electrode of a field-effect transistor. Chen teaches wherein the method comprises establishing an electrically conductive interconnect between the first electrode and a field-effect transistor on another metallization level (Fig. 1).
Noack teaches wherein a ferroelectric memory device comprises an electrically conductive interconnect between the first electrode of a ferroelectric capacitor and a gate electrode of a field effect transistor (Fig. 3C, 322, 344, 308; [0065], one or more metallization structures; [0066], [0069]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Noack with Chen, Leng, and Then such that the method comprises establishing an electrically conductive interconnect between the first electrode and a gate electrode of a field-effect transistor for the purpose of utilizing the cup-shaped ferroelectric capacitor of Chen in the FeFET memory element of Noack (Chen, [0097]; Noack, [0025]).
Claims 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. PGPub 2021/0035993) in view of Then (U.S. PGPub 2020/0119138) and Avci (U.S. PGPub 2020/0006346).
Regarding claim 10, Chen teaches a method of manufacturing a ferroelectric random-access memory cell (Fig. 54, [0097], 350) comprising:
depositing a first etch stop layer over and in direct contact with a bottom electrode (Fig. 46, bottom electrode 255 in region 120, [0098]; Fig. 49, 505/505a, [0099]-[0100]),
depositing an electrically insulating oxide layer over the first etch stop layer, said oxide layer having a first surface on a first side of the oxide layer which is distal from the bottom electrode and a second surface on a second side of the oxide layer which is proximate to the bottom electrode (Figs. 48-49, oxide layer 510, [0100]-[0101]);
creating a hole extending through a thickness of the oxide layer and through the first etch stop layer, said hole being aligned with the bottom electrode and having a side wall which extends between the first side of the oxide layer and the second side of the oxide layer (Fig. 49, [0101]);
depositing a barrier metal layer over the oxide layer on the first side thereof such that at least a first portion of the barrier metal layer is arranged upon the side wall within the hole and contacts the bottom electrode (Fig. 51, [0102], 520);
depositing a ferroelectric layer over the barrier metal layer such that at least a first portion of the ferroelectric layer is arranged within the hole with the first portion of the barrier metal layer being interposed between the side wall of the hole and the first portion of the ferroelectric layer (Fig. 51, 530, [0103]); and
depositing a metal layer over the ferroelectric layer such that at least a first portion of the metal layer fills a portion of the hole not occupied by the barrier metal and ferroelectric layers (Figs. 51-52, metal layer 540, [0104]),
planarizing down to the first side of the oxide layer (Fig. 53, [0105]),
forming a second etch stop layer over the oxide layer, forming a low-k material layer over the second etch stop layer, the low-k material being different form the electrically insulating oxide layer, and forming a second electrode in a trench and an electrically conductive path and an electrically conductive path through the low-k material layer and the second etch stop layer to the metal layer ([0106], forming IMD 260 and second electrode 263/265 by the method of Figs. 35-39; [0086] etch stop layer 460; IMD 260, [0080] same material as low-k IMD 250, [0063]; etch stop layer materials [0095]; Figs. 35-39, trench/second via 265o/263o, [0085]-[0086]; second electrode 265, Figs. 38-39, [0085]-[0088]/Fig. 54), wherein the second etch stop layer is formed from a material that is different from the first etch stop layer ([0100], first etch stop layer, silicon carbide, silicon oxide, silicon oxynitride; [0078], second etch stop layer, metal oxide).
Chen does not explicitly teach wherein the hole through which the barrier metal layer contacts the bottom electrode has a lateral width W1 and the trench has a lateral width W2 which is greater than W1, where W1 is about 20 to about 50 nm and W2 is about 100nm to about 300nm.
Chen teaches wherein the hole through which the barrier metal layer contacts the bottom electrode has a lateral width of about 5 nm to about 50 nm ([0105], 350; [0112]), wherein the trench width is formed according to the routing design, including widths that are greater than the first via width ([0028], [0032], M5, [0106], Fig. 57, [0112]),
In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05.
Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Chen such that the hole through which the barrier metal layer contacts the bottom electrode has a lateral width W1 and the trench has a lateral width W2 which is greater than W1, where W1 is about 20 to about 50 nm and W2 is about 100nm to about 300nm for the purpose of providing appropriate routing design ([0028]).
Chen does not explicitly teach where the second electrode is formed of a material different from the first electrode.
Then teaches a MIM capacitor (Fig. 5) comprising a first electrode (132, [0017]), an insulating layer and electrically conductive filling layer deposited in a via (140, V2, [0017]), and a second electrode formed in a trench over the electrically conductive filling layer (M3, [0017]), wherein the second electrode is formed of a material different from the first electrode ([0020] first electrode, TiN, TaN, Al, W, Ni, Pt, etc; [0027] second electrode, Cu, Co, Mo, Ag, Ti, etc).
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date to combine the teachings of Then with Chen such that the second electrode is formed of a material different from the first electrode for the purpose of choosing appropriate known conductive materials for the electrodes (Then, [0020], [0027]; Chen, [0064], [0028]).
Chen further does not explicitly teach wherein the metal layer is formed from a material that is different from the barrier metal layer.
Avci teaches a ferroelectric capacitor comprising a bottom electrode (130, [0032]), a barrier metal layer within a hole and contacting the bottom electrode (113, [0038]), a ferroelectric layer over the barrier metal layer and within the hole (115, [0039]), a metal layer over the ferroelectric layer such that the metal layer fills the hole (117, [0039]), and forming a second electrode in a trench connected to the metal layer (152, [0040]), wherein the metal layer is formed from a material that is different from the barrier metal layer ([0040]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Avci with Chen such that the metal layer is formed from a material that is different from the barrier metal layer for the purpose of helping with the different requirements of the top and bottom electrodes of the capacitor (Avci, [0040]).
Regarding claim 11, Chen teaches wherein: the deposited barrier metal layer includes a second portion extending laterally from the hole over the first side of the oxide layer; the deposited ferroelectric layer includes a second portion extending laterally from the hole over the second portion of the barrier metal layer; and the deposited metal layer includes a second portion extending laterally from the hole over the second portion of the ferroelectric layer (Fig. 52). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Then, and Avci for the reasons set forth in the rejection of claim 10.
Regarding claim 12, Chen teaches wherein the planarizing is performed by applying chemical mechanical polishing on the first side of the oxide layer, wherein the second portion of the barrier metal layer, the second portion of the ferroelectric layer and the second portion of the metal layer are removed by the planarizing (Fig. 53, [0105]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Then, and Avci for the reasons set forth in the rejection of claim 10.
Regarding claim 13, Chen does not explicitly teach wherein the thickness of the oxide layer is in a range of between 80 nm and 120 nm, inclusive. Chen teaches wherein the thickness of layer 510 is 5-20 nm but not limited to that range, and wherein the oxide layer may further include layer 505b, with a thickness of 3-10 nm but not limited to that range. Chen further teaches wherein the layer 510 provides vertical spacing based on the thicknesses of the layers of the capacitor ([0100]-[0101]). It has long been held that mere changes in size or shape are prima facie obvious absent a teaching of unexpected results (See MPEP 2144.04). In this case, there is no teaching in the specification regarding any criticality or unexpected result arising from the relative thicknesses of the layers. Applicant’s specification teaches only that “In some non-limiting illustrative embodiments … the IMD or OX layer 108 may have a height or thickness T1 … in a range between about 80 nanometers (nm) and about 120 nm” (Spec, [0014]). Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Chen such that the thickness of the oxide layer is in a range of between 80 nm and 120 nm, inclusive.
Regarding claim 14, Chen teaches wherein a thickness of the deposited barrier metal layer is 20 A - 300 A ([0102]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05. Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Chen, Then, and Avci such that a thickness of the deposited barrier metal layer is 30 A.
Regarding claim 15, Chen teaches wherein a thickness of the deposited ferroelectric metal layer is 10 A - 150 A ([0102]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05. Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Chen, Then, and Avci such that a thickness of the deposited ferroelectric layer is less than 50 A.
Regarding claim 16, Chen teaches wherein the ferroelectric material includes hafnium-zirconium oxide ([0103]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Then, and Avci for the reasons set forth in the rejection of claim 10.
Regarding claim 17, Chen teaches wherein the barrier metal layer comprises at least one of tantalum, tantalum nitride, titanium, titanium nitride, and cobalt ([0102]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Then, and Avci for the reasons set forth in the rejection of claim 10.
Claims 21 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. PGPub 2021/0035993) in view of Leng (U.S. PGPub 2022/0399352), Then (U.S. PGPub 2020/0119138), and Avci (U.S. PGPub 2020/0006346).
Regarding claim 21, Chen teaches a method of forming a ferroelectric random-access memory device, the method comprising:
forming a first electrode (Fig. 46, 255 in region 120, [0098]);
forming a first etch stop layer over and in direct contact with the first electrode (Figs. 49-50, 505/505a, [0099]-[0100]),
forming an intermetal dielectric layer over and in direct contact with the first etch stop layer (Figs. 48-49, layer 510, [0100]-[0101]), forming a first via through a thickness of the intermetal dielectric layer and the first etch stop layer, said first via being aligned with the first electrode and having a side wall which extends between an upper surface of the first electrode and a second surface of the intermetal dielectric layer distal from the first electrode (Fig. 49, [0101]);
arranging a first barrier metal layer within the first via to contact the first electrode and the side wall of the first via (Fig. 51, [0102], 520); arranging a ferroelectric layer within the first via such the first barrier metal layer is interposed between the side wall of the first via and the ferroelectric layer (Fig. 51, 530, [0103]); and
disposing a metal within a portion of the first via not occupied by the first barrier metal and ferroelectric layers to form an MFM structure within the first via (Figs. 51-52, 540, [0104]-[0105]),
applying chemical mechanical polishing to expose the second surface of the intermetal dielectric layer (Fig. 53, [0105]),
forming a second etch stop layer over the intermetal dielectric layer and the MFM structure, arranging a low-k material layer over the second etch stop layer, the low-k material being different from the intermetal dielectric layer, forming a trench and a second via in the low-k material layer, the second via extending through the second etch stop layer to the metal, forming a second barrier metal layer upon a side wall of the second via, and filling the trench and the second via to form a second electrode and an electrically conductive path from the metal to the second electrode ([0106], forming IMD 260 and second electrode 263/265 by the method of Figs. 35-39; [0086] etch stop layer 460; IMD 260, [0080] same material as low-k IMD 250, [0063]; etch stop materials [0095]; Figs. 35-39, trench/second via 265o/263o, [0085]-[0086]; second barrier layer 465, Fig. 37, [0081], second electrode 265, same as 415, [0068]-[0069], Figs. 38-39, [0087]-[0088]), wherein the second etch stop layer is formed from a material that is different from the first etch stop layer ([0100], first etch stop layer, silicon carbide, silicon oxide, silicon oxynitride; [0078], second etch stop layer, metal oxide), and wherein the second electrode is formed of a material different from the second barrier metal layer ([0081], [0087], second barrier metal layer 465 and second electrode 265 formed by same materials as 415/420; [0069], via 420 may be a different material from layer 415).
Chen does not explicitly teach wherein the intermetal dielectric layer has a thickness of about 80 nm to about 120 nm, the first via has a lateral width of about 20 nm to about 50 nm at an upper surface of the first electrode, the low-k material has a thickness of about 150 nm to about 250 nm, and the trench has a lateral width of about 100 nm to about 300 nm.
Chen teaches the first via having a lateral width of about 5 nm to about 50 nm ([0105], 350; [0112]), the low-k material has a thickness of about 50 nm to about 200 nm ([0085]), and wherein the trench width is formed according to the routing design, including widths that are greater than the first via width ([0028], [0032], M5, [0106], Fig. 57, [0112]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05.
Regarding the intermetal dielectric layer, Chen teaches wherein the thickness of layer 510 is 5-20 nm but not limited to that range, and wherein the intermetal dielectric layer may further include layer 505b, with a thickness of 3-10 nm but not limited to that range. Chen further teaches wherein the layer 510 provides vertical spacing based on the thicknesses of the layers of the capacitor ([0100]-[0101]). It has long been held that mere changes in size or shape are prima facie obvious absent a teaching of unexpected results (See MPEP 2144.04). In this case, there is no teaching in the specification regarding any criticality or unexpected result arising from the relative thicknesses of the layers. Applicant’s specification teaches only that “In some non-limiting illustrative embodiments … the IMD or OX layer 108 may have a height or thickness T1 … in a range between about 80 nanometers (nm) and about 120 nm” (Spec, [0014]).
Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Chen such that the intermetal dielectric layer has a thickness of about 80 nm to about 120 nm, the first via has a lateral width of about 20 nm to about 50 nm at an upper surface of the first electrode, the low-k material has a thickness of about 150 nm to about 250 nm, and the trench has a lateral width of about 100 nm to about 300 nm for the purpose of providing appropriate routing design ([0028]).
Chen further does not explicitly teach wherein the low-k material is formed from an SiOC material and the second etch stop layer directly contacts both the intermetal dielectric layer and the MFM structure.
Chen teaches wherein the low-k material is formed of a carbon-containing low-k dielectric material ([0063]).
Leng teaches wherein an etch stop layer directly contacts an intermetal dielectric and an MFM structure embedded in a via (Fig. 1A, 182, [0055]; 102, [0048]) and wherein the dielectric layer is formed of organosilicate glass ([0077]; OSG is an SiOC material with low-k).
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Leng with Chen such that the second etch stop layer directly contacts both the intermetal dielectric layer and the MFM structure for the purpose of providing an etch stop layer for forming the metallization layers (Leng, [0055]) for a MFM structure embedded in a dielectric layer (Leng, Fig. 1A; Chen, Fig. 54) and forming the low-k material from an appropriate carbon-containing low-k dielectric material (Chen, [0063]; Leng, [0077]).
Chen and Leng do not explicitly teach wherein the metal is different from the first barrier metal layer.
Chen further does not explicitly teach wherein the metal layer is formed from a material that is different from the barrier metal layer.
Avci teaches a ferroelectric capacitor comprising a bottom electrode (130, [0032]), a barrier metal layer within a hole and contacting the bottom electrode (113, [0038]), a ferroelectric layer over the barrier metal layer and within the hole (115, [0039]), a metal layer over the ferroelectric layer such that the metal layer fills the hole (117, [0039]), and forming a second electrode in a trench connected to the metal layer (152, [0040]), wherein the metal layer is formed from a material that is different from the barrier metal layer ([0040]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Avci with Chen such that the metal layer is formed from a material that is different from the barrier metal layer for the purpose of helping with the different requirements of the top and bottom electrodes of the capacitor (Avci, [0040]).
Chen and Leng further do not explicitly teach wherein the second electrode is formed from a material that is different from the first electrode.
Then teaches a MIM capacitor (Fig. 5) comprising a first electrode (132, [0017]), an insulating layer and electrically conductive filling layer deposited in a via (140, V2, [0017]), and a second electrode formed in a trench over the electrically conductive filling layer (M3, [0017]), wherein the second electrode is formed of a material different from the first electrode ([0020] first electrode, TiN, TaN, Al, W, Ni, Pt, etc; [0027] second electrode, Cu, Co, Mo, Ag, Ti, etc).
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date to combine the teachings of Then with Chen and Leng such that the second electrode is formed of a material different from the first electrode for the purpose of choosing appropriate known conductive materials for the electrodes (Then, [0020], [0027]; Chen, [0064], [0028]).
Regarding claim 24, Chen teaches wherein the metal disposed within the first via is tungsten ([0104]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Leng, Then, and Avci for the reasons set forth in the rejection of claim 21.
Regarding claim 25, Chen teaches wherein the ferroelectric material includes hafnium-zirconium oxide ([0103]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Leng, Then, and Avci for the reasons set forth in the rejection of claim 21.
Regarding claim 26, Chen teaches wherein the barrier metal layer comprises at least one of tantalum, tantalum nitride, titanium, titanium nitride, and cobalt ([0102]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Leng, Then, and Avci for the reasons set forth in the rejection of claim 21.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. PGPub 2021/0035993) in view of Leng (U.S. PGPub 2022/0399352), Then (U.S. PGPub 2020/0119138), and Avci (U.S. PGPub 2020/0006346) and further in view of Noack (U.S. PGPub 2022/0139933).
Regarding claim 23, Chen does not explicitly teach wherein the method comprises electrically connecting the gate electrode of a field-effect transistor to the first electrode. Chen teaches wherein the method comprises establishing an electrically conductive interconnect between the first electrode and a field-effect transistor on another metallization level (Fig. 1).
Noack teaches wherein a ferroelectric memory device comprises an electrically conductive interconnect between the first electrode of a ferroelectric capacitor and a gate electrode of a field effect transistor (Fig. 3C, 322, 344, 308; [0065], one or more metallization structures; [0066], [0069]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Noack with Chen and Leng such that the method comprises electrically connecting the gate electrode of a field-effect transistor to the first electrode for the purpose of utilizing the cup-shaped ferroelectric capacitor of Chen in the FeFET memory element of Noack (Chen, [0097]; Noack, [0025]).
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812