Prosecution Insights
Last updated: April 19, 2026
Application No. 17/737,486

Semiconductor Module with Liquid Dielectric Encapsulant

Final Rejection §103
Filed
May 05, 2022
Examiner
CHEN, DAVID Z
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
4 (Final)
44%
Grant Probability
Moderate
5-6
OA Rounds
3y 9m
To Grant
94%
With Interview

Examiner Intelligence

Grants 44% of resolved cases
44%
Career Allow Rate
299 granted / 675 resolved
-23.7% vs TC avg
Strong +49% interview lift
Without
With
+49.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
63 currently pending
Career history
738
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.4%
+7.4% vs TC avg
§102
26.4%
-13.6% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 675 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This Office Action is in response to Amendments/Remarks filed on December 08, 2025. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2012-109451 A to Obara et al. (“Obara”) in view of U.S. Patent Application Publication No. 2018/0323120 A1 to Harada et al. (“Harada”), U.S. Patent Application Publication No. 2018/0166363 A1 to Heppner et al. (“Heppner”), and U.S. Patent Application Publication No. 2009/0008800 A1 to Nakatani et al. (“Nakatani”). As to claim 1, although Obara discloses a semiconductor module, comprising: a power electronics carrier (30) comprising a metallization layer (32) disposed on an electrically insulating substrate (31); a power semiconductor die (20) mounted on the power electronics carrier (30); a housing (10) that surrounds an interior volume (under 51) over the power electronics carrier (30); a volume of electrically insulating encapsulant (50) that fills the interior volume (under 51) and encapsulates the power semiconductor die (20); and a pressure compensation element (51, 55) disposed on or within the electrically insulating encapsulant (50), wherein the electrically insulating encapsulant (50) is a liquid (50), wherein the semiconductor module forms an impermeable seal that contains the volume of electrically insulating encapsulant (50), and wherein the pressure compensation element (51, 55) is configured to maintain the electrically insulating encapsulant (50) at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant (50), wherein the semiconductor module comprises an elastic membrane (51) disposed on an upper surface of the encapsulant (50) that is opposite from the power electronics carrier (30), wherein the elastic membrane (51) extends between sidewalls of the housing (10) and is disposed below a roof section (top 10, top 60 supported by 10 to be part of the housing) of the housing (10), and wherein the elastic membrane (51) forms a sealant layer (51) that forms part of the impermeable seal and forms at least part of the pressure compensation element (51, 55) (See Fig. 1, Fig. 2, Fig. 3, First/Second Embodiment, Page 2-Page 5) (Notes: the pressure compensation element of silicone gel/resin comprises a certain degree of flexibility via volume change), Obara does not further disclose a three-dimensional grid of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant, wherein the three-dimensional grid is any one of the following: a foam, a sponge, and a three-dimensional textile. Harada also discloses wherein the elastic membrane (8) extends between sidewalls of the housing (6) and is disposed below a roof section (7) of the housing (6) (See Fig. 1, ¶ 0033, ¶ 0040) such that the roof section separates the inside and outside of the semiconductor module to prevent dust and the like from entering the semiconductor module. Further, Heppner discloses a three-dimensional grid (320) of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant (50/330) (See Obara Fig. 1, Fig. 3 and Heppner Fig. 1, Fig. 3, ¶ 0026, ¶ 0030, ¶ 0031, ¶ 0036) and Nakatani discloses wherein the three-dimensional grid (205) is a foam metal (See Fig. 5, ¶ 0113). In view of the teachings of Heppner and Nakatani, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Obara to have a three-dimensional grid of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant, wherein the three-dimensional grid is any one of the following: a foam, a sponge, and a three-dimensional textile because the three-dimensional grid of a foam metal provides a shield effect for preventing the noises from outside (See Heppner ¶ 0036 and Nakatani ¶ 0113). Further regarding claim 1, the claim limitation “wherein the pressure compensation element is configured to maintain the electrically insulating encapsulant at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant” specifies an intended use or field of use, and is met by the prior art since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987). As to claim 9, Obara further discloses wherein the electrically insulating encapsulant (50) is a liquid at temperatures between −40°C and 200°C (See Page 2) (Notes: the disclosed silicone oil is met by Obara). As to claim 10, Obara further discloses wherein the electrically insulating encapsulant (50) is a silicon-based oil (See Page 2). Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over JP 2012-109451 A to Obara et al. (“Obara”) in view of U.S. Patent Application Publication No. 2018/0323120 A1 to Harada et al. (“Harada”), U.S. Patent Application Publication No. 2018/0166363 A1 to Heppner et al. (“Heppner”), and U.S. Patent Application Publication No. 2019/0357347 A1 to Kim (“Kim”). As to claim 20, although Obara discloses a semiconductor module, comprising: a power electronics carrier (30) comprising a metallization layer (32) disposed on an electrically insulating substrate (31); a power semiconductor die (20) mounted on the power electronics carrier (30); a housing (10) that surrounds an interior volume (under 51) over the power electronics carrier (30); a volume of electrically insulating encapsulant (50) that fills the interior volume (under 51) and encapsulates the power semiconductor die (20); and a pressure compensation element (51, 55) disposed on or within the electrically insulating encapsulant (50), wherein the electrically insulating encapsulant (50) is a liquid (50), wherein the semiconductor module forms an impermeable seal that contains the volume of electrically insulating encapsulant (50), and wherein the pressure compensation element (51, 55) is configured to maintain the electrically insulating encapsulant (50) at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant (50), wherein the semiconductor module comprises an elastic membrane (51) disposed on an upper surface of the encapsulant (50) that is opposite from the power electronics carrier (30), wherein the elastic membrane (51) extends between sidewalls of the housing (10) and is disposed below a roof section (top 10, top 60 supported by 10 to be part of the housing) of the housing (10), and wherein the elastic membrane (51) forms a sealant layer (51) that forms part of the impermeable seal and forms at least part of the pressure compensation element (51, 55) (See Fig. 1, Fig. 2, Fig. 3, First/Second Embodiment, Page 2-Page 5) (Notes: the pressure compensation element of silicone gel/resin comprises a certain degree of flexibility via volume change), Obara does not further disclose a three-dimensional grid of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant, wherein the three-dimensional grid comprises a polymer or resin material. Harada also discloses wherein the elastic membrane (8) extends between sidewalls of the housing (6) and is disposed below a roof section (7) of the housing (6) (See Fig. 1, ¶ 0033, ¶ 0040) such that the roof section separates the inside and outside of the semiconductor module to prevent dust and the like from entering the semiconductor module. Further, Heppner discloses a three-dimensional grid (320) of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant (50/330) (See Obara Fig. 1, Fig. 3 and Heppner Fig. 1, Fig. 3, ¶ 0021, ¶ 0026, ¶ 0030, ¶ 0031, ¶ 0036) and Kim discloses an electromagnetic shielding layer (80) comprises a polymer or resin material (83) (See Fig. 4 ¶ 0047-¶ 0051). In view of the teachings of Heppner and Kim, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Obara to have a three-dimensional grid of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant, wherein the three-dimensional grid comprises a polymer or resin material because the three-dimensional grid comprising a metal thin film coated with polymer or resin material maximizes the protection and performance of a shield effect for preventing the noises to/from the semiconductor die (See Heppner ¶ 0021, ¶ 0036, and Kim ¶ 0051). Further regarding claim 20, the claim limitation “wherein the pressure compensation element is configured to maintain the electrically insulating encapsulant at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant” specifies an intended use or field of use, and is met by the prior art since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987). Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over JP 2012-109451 A to Obara et al. (“Obara”) in view of U.S. Patent Application Publication No. 2018/0323120 A1 to Harada et al. (“Harada”), U.S. Patent Application Publication No. 2018/0166363 A1 to Heppner et al. (“Heppner”), U.S. Patent Application Publication No. 2019/0357347 A1 to Kim (“Kim”), and WO-2011016408-A1 to Kageyama et al. (“Kageyama”). As to claim 21, although Obara discloses a semiconductor module, comprising: a power electronics carrier (30) comprising a metallization layer (32) disposed on an electrically insulating substrate (31); a power semiconductor die (20) mounted on the power electronics carrier (30); a housing (10) that surrounds an interior volume (under 51) over the power electronics carrier (30); a volume of electrically insulating encapsulant (50) that fills the interior volume (under 51) and encapsulates the power semiconductor die (20); and a pressure compensation element (51, 55) disposed on or within the electrically insulating encapsulant (50), wherein the electrically insulating encapsulant (50) is a liquid (50), wherein the semiconductor module forms an impermeable seal that contains the volume of electrically insulating encapsulant (50), and wherein the pressure compensation element (51, 55) is configured to maintain the electrically insulating encapsulant (50) at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant (50), wherein the semiconductor module comprises an elastic membrane (51) disposed on an upper surface of the encapsulant (50) that is opposite from the power electronics carrier (30), wherein the elastic membrane (51) extends between sidewalls of the housing (10) and is disposed below a roof section (top 10, top 60 supported by 10 to be part of the housing) of the housing (10), and wherein the elastic membrane (51) forms a sealant layer (51) that forms part of the impermeable seal and forms at least part of the pressure compensation element (51, 55) (See Fig. 1, Fig. 2, Fig. 3, First/Second Embodiment, Page 2- Page 5) (Notes: the pressure compensation element of silicone gel/resin comprises a certain degree of flexibility via volume change), Obara does not further disclose a three-dimensional grid of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant, wherein the three-dimensional grid absorbs the electrically insulating encapsulant. Harada also discloses wherein the elastic membrane (8) extends between sidewalls of the housing (6) and is disposed below a roof section (7) of the housing (6) (See Fig. 1, ¶ 0033, ¶ 0040) such that the roof section separates the inside and outside of the semiconductor module to prevent dust and the like from entering the semiconductor module. Further, Heppner discloses a three-dimensional grid (320) of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant (50/330) (See Obara Fig. 1, Fig. 3 and Heppner Fig. 1, Fig. 3, ¶ 0026, ¶ 0030, ¶ 0031, ¶ 0036) and Kim discloses an electromagnetic shielding layer (80) comprises a polymer or resin material (83) (See Fig. 4 ¶ 0047-¶ 0051), where the polymer or resin material is known to absorb a certain degree of moisture. Lastly, Kageyama discloses a hygroscopic metal oxide is provided in the resin composition to improve moisture permeation resistance and adhesive strength (See Page 1, Page 6, Page 7). In view of the teachings of Heppner, Kim, and Kageyama, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Obara to have a three-dimensional grid of material that is substantially rigid at room temperature and is immersed within the volume of electrically insulating encapsulant, wherein the three-dimensional grid absorbs the electrically insulating encapsulant because the three-dimensional grid comprising a metal thin film coated with polymer or resin material maximizes the protection and performance of a shield effect for preventing the noises to/from the semiconductor die, where the polymer or resin material is known to absorb a certain degree of moisture of the fluid electrically insulating encapsulant. Lastly, the hygroscopic metal oxide that absorbs moisture is provided in the resin composition to improve moisture permeation resistance and adhesive strength (See Heppner ¶ 0021, ¶ 0036, Kim ¶ 0051, and Kageyama Page 6, Page 7). Further regarding claim 21, the claim limitation “wherein the pressure compensation element is configured to maintain the electrically insulating encapsulant at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant” specifies an intended use or field of use, and is met by the prior art since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987). Response to Arguments Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
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Prosecution Timeline

May 05, 2022
Application Filed
Dec 14, 2024
Non-Final Rejection — §103
Mar 17, 2025
Response Filed
Apr 30, 2025
Final Rejection — §103
Jun 25, 2025
Response after Non-Final Action
Jul 30, 2025
Request for Continued Examination
Jul 31, 2025
Response after Non-Final Action
Sep 06, 2025
Non-Final Rejection — §103
Dec 08, 2025
Response Filed
Mar 13, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
44%
Grant Probability
94%
With Interview (+49.2%)
3y 9m
Median Time to Grant
High
PTA Risk
Based on 675 resolved cases by this examiner. Grant probability derived from career allow rate.

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