Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claims 1-5, 7-12, 25-26, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Nasiri (PGPub No. 20140210019) in further view of Jaducana (PGPub No. 20090127690) Foughi (PGPub No. 20190383676), and Lobianco (PGPub No. 20180233423).
Regarding claim 1, Nasiri teaches a sensor package, comprising: a first semiconductor die; a second semiconductor die that is attached to the first semiconductor die to form a monolithic die (Fig. 1A and [0016-17] points to a MEMS package 100 comprising a CMOS die 106 (first semiconductor die) and a MEMs die 105 (second semiconductor die), which are bonded (monolithic die) through wafer bonding techniques such as fusion bonding, which are better discussed in Nasiri2 (US Patent No. 7104129 B2) which is incorporated by reference in Nasiri.); and a substrate comprising a top portion and a bottom portion (Fig. 1A points to a substrate 102.), wherein the monolithic die is directly attached to the top portion of the substrate via a room-temperature-vulcanizing (RTV) material that is disposed in a defined area of the top portion of the substrate corresponding to a die bottom portion of the monolithic die (Fig. 1A and [0016] point to an adhesive material 112, which refers to any low stress adhesive material such as Room Temperature Vulcanizing (RTV) silicone elastomer.).
Nasiri fails to teach a substrate comprising solder resist, copper, and a non-conductive material that contacts the solder resist and the copper, wherein the top portion comprises a plurality of solder resist dams comprising respective portions of the solder resist; wherein the RTV material is fully enclosed within a cavity defined by the plurality of solder resist dams, the die bottom portion of the monolithic die, and the top portion of the substrate, and wherein the bottom portion of the substrate comprises electrical terminals that comprise respective portions of the copper and that facilitate attachment and electrical coupling of signals of the sensor package to a printed circuit board.
Jaducana teaches a substrate comprising solder resist, wherein the top portion comprises a plurality of solder resist dams comprising respective portions of the solder resist (Figs. 3 and 4b, along with [0038], point to a dam 44 comprising a top layer of solder resist.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Nasiri and Jaducana, such that a solder resist is formed on top of the substrate in order to influence the shape of the RTV material as it is applied to the substrate and monolithic die.
Nasiri et al. still fails to teach a substrate comprising copper, and a non-conductive material that contacts the solder resist and the copper, wherein the RTV material is fully enclosed within a cavity defined by the plurality of solder resist dams, the die bottom portion of the monolithic die, and the top portion of the substrate, and wherein the bottom portion of the substrate comprises electrical terminals that comprise respective portions of the copper and that facilitate attachment and electrical coupling of signals of the sensor package to a printed circuit board.
Nasiri et al. in combination with Foughi teaches a substrate comprising copper, and a non-conductive material that contacts the solder resist and the copper (Fig. 3, [0052], and [0056] of Foughi point to a MEMS force sensor comprising a base 11 (substrate) made of silicon and electrical terminals 19 which can be copper pillars.), wherein the bottom portion of the substrate comprises electrical terminals that comprise respective portions of the copper and that facilitate attachment and electrical coupling of signals of the sensor package to a printed circuit board (Fig. 1A and [0017] of Nasiri point to bond pads 118b (electrical terminals), which are used to connect to a PCB substrate.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri et al. and Foughi, such that the substrate further comprises electrical terminals made of copper and a non-conductive material separating the terminals from the solder resist in order to create stable signal paths that can be routed to the PCB and other external components.
Nasiri et al. still fails to teach wherein the RTV material is fully enclosed within a cavity defined by the plurality of solder resist dams, the die bottom portion of the monolithic die, and the top portion of the substrate.
Lobianco teaches wherein the RTV material is fully enclosed within a cavity defined by the plurality of solder resist dams, the die bottom portion of the monolithic die, and the top portion of the substrate (Fig. 3 points to a cavity 110 formed between dams 135, a die 100, and a PCB 105.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri et al. and Lobianco, such that the solder resist dams, monolithic die, and substrate are positioned to form a cavity in order to better control the application of the RTV material and by extension optimize bonding between the die and substrate.
Regarding claim 2, Nasiri teaches wherein the first semiconductor die or the second semiconductor die comprises redistribution layer circuitry or complementary metal-oxide- semiconductor circuitry (Fig. 1A points to a CMOS die 106).
Regarding claim 3, Nasiri teaches wherein the first semiconductor die or the second semiconductor die comprises a micro-electromechanical systems device (Fig. 1A points to a MEMS die 105).
Regarding claim 4, Nasiri teaches a third semiconductor die that is attached to the monolithic die (Fig. 4A points to an alternative embodiment of a MEMS package 400 comprising a CMOS die 404 (third semiconductor die) that is attached to the combined CMOS die 402 and MEMS die 414 (monolithic die).).
Regarding claim 5, Nasiri teaches a third semiconductor die that is disposed on the top portion of the substrate (Fig. 4A points to an alternative embodiment of a MEMS package 400 comprising the CMOS die 404 (third semiconductor die) attached onto a substrate 406.).
Regarding claim 7, Nasiri teaches wherein the RTV material has been cured, after the monolithic die has been attached to the defined area of the top portion of the substrate corresponding to the die bottom portion of the monolithic die, to obtain a solid state of the RTV material (Fig. 1A points to the CMOS die 106 and MEMS die 105 (monolithic die) bonded to the substrate 102 via the adhesive material 112, which is a Room Temperature Vulcanizing (RTV) silicone elastomer. It is considered obvious the adhesive material would undergo a curing process resulting in a solid state due to the inherent properties of RTV silicone elastomer.).
Regarding claim 8, Nasiri teaches wherein the RTV material has been cured, after the monolithic die has been attached to the defined area of the top portion of the substrate corresponding to the die bottom portion of the monolithic die, based on a defined bond line thickness of the RTV material that is greater than or equal to 21 microns and less or equal to 29 microns ([0019] points to the RTV silicone bond line being typically 25µm thick.).
Regarding claim 9, Jaducana in combination with Lobianco teaches wherein the plurality of solder resist dams prevents the RTV material from flowing above and beyond the die bottom portion of the monolithic die and the respective top surfaces of the plurality of solder resist dams during a viscous state of the RTV material (Figs. 3 and 4b, along with [0032] of Jaducana point to a dam 44 (plurality of solder resist dams) that influences the shape of a glob material 30 (RTV material). Fig. 3 of Lobianco points to dams 135 which are positioned entirely beneath the die 100.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri et al., Jaducana, and Lobianco, such that the solder resist dams are formed to prevent both the horizontal and vertical flow of the RTV material beyond a defined area in order to influence the shape of said matter/material and, for example, limit overuse that could impact the corresponding region(s).
Regarding claim 10, Jaducana teaches wherein the plurality of solder resist dams comprises a pair of solder resist dams that are arranged in a two-column pattern ([0038] points to the dam 44 comprising a rectangular shape. It is considered obvious that one of ordinary skill in the art could remove two sides to create a two-column pattern in an attempt to change the shape of the encapsulation material/RTV material/etc.), and wherein the monolithic die is attached between the pair of solder resist dams (Fig. 3 points to a microelectronic component 20 (monolithic die).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri et al. and Jaducana, such that the solder resist dams are shaped in a two-column pattern in order to influence the flowing matter/material into a different shape which may impact the corresponding region(s) differently.
Regarding claim 11, Jaducana teaches wherein the plurality of solder resist dams is arranged in a rectangular pattern ([0038] points to the dam 44 comprising a rectangular shape.), and wherein the monolithic die is attached within the rectangular pattern (Fig. 3 points to a microelectronic component 20 (monolithic die).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri et al. and Jaducana, such that the solder resist dams are shaped in a rectangular pattern in order to contain the flowing matter/material and better influence its shape.
Regarding claim 12, Jaducana teaches wherein a defined height of the plurality of solder resist from the top portion of the substrate is greater than or equal to 15 microns and less than or equal to 25 microns (Fig. 3 and [0036] point to height h of the dam 44, which ranges from 20µm – 30µm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri et al. and Jaducana, such that the solder resist dams are of an adequate height in order to properly contain the flowing matter/material and better influence its shape.
Regarding claim 25, Nasiri teaches a sensor package, comprising: a semiconductor die comprising a semiconductor die bottom portion (Fig. 1A points to a MEMS package 100 comprising a CMOS die 106.); and a substrate comprising a substrate top portion and a substrate bottom portion (Id. points to a substrate 102.), wherein the semiconductor die is directly attached to the substrate top portion via a room-temperature-vulcanizing (RTV) material that is disposed in a defined area of the substrate top portion corresponding to the semiconductor die bottom portion (Fig. 1A and [0016] point to an adhesive material 112, which refers to any low stress adhesive material such as Room Temperature Vulcanizing (RTV) silicone elastomer.), and wherein the substrate bottom portion comprises electrical terminals that facilitate attachment and electrical coupling of signals of the sensor package to a printed circuit board (Fig. 1A and [0017] point to bond pads 118b (electrical terminals), which are used to connect to a PCB substrate.).
Nasiri fails to teach wherein the substrate top portion comprises a plurality of solder resist dams, and wherein the plurality of solder resist dams comprises a rectangular solder resist dam comprising a continuous boundary comprising the defined area of the substrate top portion corresponding to the semiconductor die bottom portion, wherein the RTV material is fully enclosed within a cavity defined by the rectangular solder resist dam, the semiconductor die bottom portion, and the substrate top portion.
Jaducana teaches wherein the substrate top portion comprises a plurality of solder resist dams, and wherein the plurality of solder resist dams comprises a rectangular solder resist dam comprising a continuous boundary comprising the defined area of the substrate top portion corresponding to the semiconductor die bottom portion (Figs. 3 and 4b, along with [0038], point to a dam 44 comprising a rectangular shape.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri and Jaducana, such that a solder resist dam is formed on top of the substrate in order to influence the shape of the RTV material as it is applied to the substrate and monolithic die.
Nasiri et al. still fails to teach wherein the RTV material is fully enclosed within a cavity defined by the rectangular solder resist dam, the semiconductor die bottom portion, and the substrate top portion.
Lobianco teaches wherein the RTV material is fully enclosed within a cavity defined by the plurality of solder resist dams, the die bottom portion of the monolithic die, and the top portion of the substrate (Fig. 1A and [0016] of Nasiri point to an adhesive material 112 (RTV material). Fig. 3 of Lobianco points to a cavity 110 formed between dams 135, a die 100, and a PCB 105.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri et al. and Lobianco, such that the solder resist dam(s), monolithic die, and substrate are positioned to form a cavity in order to better control the application of the RTV material and by extension optimize bonding between the die and substrate.
Regarding claim 26, Jaducana teaches wherein an encapsulant material is formed over the semiconductor die (Fig. 3 points to an encapsulation material 30 formed over a microelectronic component 20 (semiconductor die).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri and Jaducana, such that an encapsulant material is formed over the semiconductor die in order to provide protection against external stresses.
Regarding claim 32, Nasiri teaches a wire that electrically couples the semiconductor die to the substrate (Fig. 1A points to a bond wire 116.).
Claim(s) 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Nasiri et al in further view of Brioschi (PGPub No. 20200299127).
Regarding claim 27, Nasiri in combination with Jaducana teaches wherein the plurality of solder resist dams is a first plurality of solder resist dams, wherein the RTV material is a first RTV material, wherein the defined area is a first defined area, and wherein the top portion comprises a second plurality of solder resist dams, and wherein a second semiconductor die is directly attached to the substrate top portion via a second RTV material that is disposed in a second defined area of the substrate top portion (Fig. 1A of Nasiri points to a CMOS die 106 attached to a top surface of a substrate 102 via an adhesive material 112 (RTV material). Figs. 3 and 4b of Jaducana further point to a dam 44 (plurality of solder resist dams). It is considered obvious that one of ordinary skill in the art could duplicate this structure and create a second set (second plurality of resist dams; second semiconductor die; second RTV material) in a different area within the top portion of the substrate in order to, for example, lower the height profile of the overall sensor package while still maintaining two semiconductor dies.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri and Jaducana, such that a second instance of a semiconductor die surrounded by a plurality of solder resist dams and bonded to the top portion of the substrate via a RTV material is formed in order to avoid vertical fabrication methods and create a lower profile for the sensor package.
Nasiri et al. fails to teach wherein the sensor package further comprises: a second semiconductor die that is disposed over a port in the substrate top portion.
Brioschi teaches wherein the sensor package further comprises: a second semiconductor die that is disposed over a port in the top portion of the substrate (Fig. 6 points to a package 300 comprising a MEM microphone transducer die 100 (second semiconductor die) mounted over a hole 34 (port) in a substrate 30.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Nasiri et al. and Brioschi, such that the second semiconductor die that is disposed over a port in the substrate in order to create an acoustic port of the package and allow the ingress of acoustic pressure waves.
Regarding claim 28, Nasiri teaches wherein the first semiconductor die or the second semiconductor die comprises redistribution layer circuitry or complementary metal-oxide- semiconductor circuitry (Fig. 1A points to a CMOS die 106).
Regarding claim 29, Nasiri teaches wherein the first semiconductor die or the second semiconductor die comprises a micro-electromechanical systems device (Fig. 1A points to a MEMS die 105).
Regarding claim 30, Nasiri teaches a lid that is attached to the substrate top portion, wherein the lid encompasses the first semiconductor die and the second semiconductor die (Fig. 1A points to a lid 110.).
Regarding claim 31, Nasiri teaches wherein the semiconductor die is a monolithic die comprising a first semiconductor die and a second semiconductor die (Fig. 1A and [0016-17] points to a CMOS die 106 (first semiconductor die) and a MEMs die 105 (second semiconductor die), which are bonded (monolithic die) through wafer bonding techniques.), wherein the RTV material is cured, after the monolithic die has been attached to the defined area of the substrate top portion corresponding to the semiconductor die bottom portion, to obtain a solid state of the RTV material that is elastic (Fig. 1A points to the CMOS die 106 and MEMS die 105 (monolithic die) bonded to the substrate 102 via the adhesive material 112, which is a Room Temperature Vulcanizing (RTV) silicone elastomer. It is considered obvious the adhesive material would undergo a curing process resulting in a certain solid state and elasticity due to the inherent properties of RTV silicone elastomer.).
Response to Arguments
Applicant’s arguments, see Remarks, filed 02/06/2026, with respect to the rejections of claims 7, 9, and 31 under 35 U.S.C. 112(b) have been fully considered and are persuasive. The rejections of said claims have been withdrawn.
Applicant’s arguments, see Remarks, filed 02/06/2026, with respect to the rejection(s) of claim(s) 1 and 25 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lobianco (PGPub No. 20180233423).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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