DETAILED ACTION
This correspondence is in response to the communications received December 18, 2025. Claims 1-20 are pending.
Response to Arguments
Applicant’s arguments have been considered, however in light of the Baenninger reference based rejections of limitations discussed, the newly presented rejection discloses the features which the Nam reference fails to disclose.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
A species restriction was considered in view of the embodiment of a single contact segment (for example Fig. 2) versus the embodiment of plural contact segments (for example Fig. 4), however the entirety of the claim set appears to be directed to the disclosed embodiment captured by the plural contact segments (Fig. 4, for example). The language of claim 1, “a plurality of plate line contact segments” and in claim 13, “plurality of alternatively arranged dielectric layers and conductive layers” point to the plural contact segment embodiment. For purposes of examination, the originally filed claim set and this identified invention has been constructively elected by original presentation for prosecution on the merits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 13, and the claims that depend therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term [1]“a word line contact” and [2]“word line” in claim 1 is used by the claim to mean [1] a contact via for an access gate, and [2] an access gate. The purpose of 34 of Baenninger and for this type of vertical memory device is to “open” the channel so that electrical access may be granted to the memory sites of the vertical memory device. The term “word line” is used in the art to reflect the gate electrode at the actual memory site, where the charges are held and represent the memory information, the word line, in part, operates the memory site. The term is indefinite because the specification does not clearly redefine the term.
Related Prior Art
Nishikawa et al. (US 9,911,748) Fig. 22B, where “source regions 61” (col. 17, line 32) are formed below the plate regions (46, etc.).
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 4, 9H and 9I, a memory structure, comprising:
a memory cell (200) comprising:
a cylindrical body (210, 924, 1124) having a cylindrical shape,
an insulating layer (412, 1121) surrounding the cylindrical body (1124) and in contact with the cylindrical body (412 surrounds 210),
a word line contact (top most 947, Fig. 9G, top most 1108) surrounding a first portion of the insulating layer (top most 947 surrounds 1121), the word line contact (top most 947, Fig. 9G, top most 1108) coupled to a word line (“Via 973 electrically coupled to top gate electrode layer 945 can be used as the word line”, ¶ 0151), and
a plurality of plate line contact segments (248 or “the top conductive layer 1108 can be used as the WL contact, and the other conductive layers 1108 below the top conductive layer 1108 can be used as a plurality of PL contact segments.”, ¶ 0158, this also could be the lower 947) surrounding a second portion of the insulating layer, the plurality of plate line contact segments (lower 1108 or 947) coupled to a plurality of plate lines respectively (975 are the “plate lines”, see ¶ 0151, “Vias 975 electrically coupled to other gate electrode layers 945 respectively can be used as the plate lines”) and each of the plurality of plate line contact segments separated from other of the plurality of plate line segments by the insulating layer (1106 separate 1108 from each other as can be seen in Fig. 11A) and in contact with the insulating layer (448 in contact with 412);
a bit line contact (222 or in the cross-cut view of Figs. 9+, element 962 is the analogous “bit line contact”) coupled to a first end of the cylindrical body of the memory cell, the bit line contact coupled to a bit line (220 or Via 971 in Fig. 9I);
a source line contact (232 or in the cross cut view in Figs. 9H, the analogous element to the “source line contact” is described to be “The gate line conductive structure 956 is in contact with the bottom conductive layer 902 at the bottom of each gate line silt 930, and can be used as a common source contact of the multiple SGTs.”, ¶ 0149) coupled to a source line (230, and analogous “source line” 902); and
a source cap (234, 922 in Fig. 9D) coupled between the source line contact (956 in Fig. 9H) and a second end of the cylindrical body (lower end of 924) of the memory cell to increase a distance between the source line contact and the plurality of plate line contact segments (between the “source line contact” 956 and the “plate line contact segments” 947).
Claim Objections
The amendments to claim 1 and 13 have overcome the previous claim objections, and are hereby withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Baenninger et al. (US 9,419,135) in view of Izumi et al. (US 9,401,309) in view of Nam et al. (US 9,461,061).
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Regarding claim 1, Baenninger discloses in Figs. 1A-1C, a memory structure (col. 4, lines 17-22, describes Fig. 1C being a “memory device”), comprising:
a memory cell (entirety of device components shown in Fig. 1C) comprising:
a cylindrical body (1, “the semiconductor channel 1 may be hollow, for example a hollow substantially cylindrical shape (e.g., tapered cylinder with increasing diameter, such as a hollow truncated cone, or a cylinder with a substantially uniform diameter as a function of height throughout most of the channel”, col. 6, lines 35-11) having a cylindrical shape (as discussed in col. 6, lines 35-11),
an insulating layer (2, “insulating fill material 2”, col. 6, line 42, and “insulating layers 19”, col. 4, lines 19-20) surrounding the cylindrical body and contact with the cylindrical body (portions of 2/19 surrounds and contacts 1),
a word line contact (“drain side select gate electrode 34”, col. 11, line 51) surrounding a first portion of the insulating layer (34 surrounds top portion of 2),
a plurality of plate line contact segments (elements 3, which are 3a, 3b, etc. of 70, “a plurality of control gate electrodes 3 separated by a plurality of insulating layers 19”, col. 4, lines 18-20) surrounding a second portion of the insulating layer (plural 3 surround a lower section of 2),
and each of the plurality of plate line contact segments (3) separated from other of the plurality of plate line contact segments by the insulating layer (3 are separated by portion 19 of 2/19) and in contact with the insulating layer (3 are in contact with portion 2 of 2/19);
a bit line contact (103, col. 5, lines 61-62) coupled to a first end of the cylindrical body of the memory cell (103 connects to top end of 206), the bit line contact (103) coupled to a bit line (103 connected to 203, where “bit line 203”, col. 6, lines 25-30);
a source line contact (302, “The p-well 302”, col. 10, 61-64) coupled to a source line (302 connects to 206, “the source electrode 202 (e.g., 202a, 202b, etc.) comprises electrically conductive pillars comprising at least one first trench material, as shown in FIGS. 1A and 1B.”); and
a source cap (102a, “source region 102a”, col. 3, line 21) coupled between the source line contact (302) and a second end of the cylindrical body (lower end of 1) of the memory cell to increase a distance between the source line contact and the plurality of plate line contact segments (102a is in a region that spaces lowest 3 from 302),
wherein the source cap (102a) is located lower than all plate line contact segments in the memory cell (102a is lower than all horizontal metals of 3 and also 33).
The features of “word line contact”, “word line”, “source line contact” and “source line”, of Baenninger which are in positions that are identical to that of Applicant’s memory device. The features are not labeled in the same manner, but perform the same function and are considered to satisfy each of their respective limitations. It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the “word line contact”, “word line”, “source line contact” and “source line” of Baenninger would inherently have the same functionality as that of the Applicant’s similarly arranged memory device construction as disclosed. See MPEP 2112.01.
Baenninger does not disclose the contact arrangement to the “drain side select gate electrode 34”, and therefore does not disclose,
“the word line contact coupled to a word line”, and
“the plurality of plate line contact segments coupled to a plurality of plate lines respectively”.
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Izumi discloses in Fig. 26,
the word line contact (46A) coupled to a word line (66F),
the plurality of plate line contact segments (46B, 46C, 46D, 46E) coupled to a plurality of plate lines respectively (66E, 66D, 66C, 66B),
a source line contact (76) coupled to a source line (12 and part of 14)”.
Then by the now included “source line contact”, the modification of the Izumi reference to the system shown by Baenninger, then would satisfy the limitation of, “a source cap coupled between the source line contact and a second end of the cylindrical body of the memory cell to increase a distance between the source line contact and the plurality of plate line contact segments”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“the word line contact coupled to a word line …
the plurality of plate line contact segments coupled to a plurality of plate lines respectively …
a source line contact coupled to a source line; and
a source cap coupled between the source line contact and a second end of the cylindrical body of the memory cell to increase a distance between the source line contact and the plurality of plate line contact segments”, as disclosed by Izumi in the system of Baenninger, for the purpose of allowing for electrical signal to reach each of the word line contact, plate line contact segments, and the source line. G. TSM: Teaching, Suggestion, Motivation Test.
Baenninger does not disclose that the top contact of the cylinder is specifically called a “bit line contact”, and therefore does not disclose, “a bit line contact coupled to a first end of the cylindrical body of the memory cell”.
Nam discloses in Fig. 1A, wherein, a bit line contact (“bit line contact 190”, col. 5, line 7) coupled to a first end (top end) of the cylindrical body of the memory cell (equivalent “channel 135”, col. 5, line 57).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“a bit line contact coupled to a first end of the cylindrical body of the memory cell”, as disclosed by Nam in the system of Baenninger, for the purpose of allowing for electrical signal to reach the cylindrical body as a bit line access point. G. TSM: Teaching, Suggestion, Motivation Test.
Regarding claim 6, the prior art of Baenninger et al. disclose the memory structure of claim 1, and Izumi discloses in Fig. 26, wherein:
the cylindrical body extends in a first direction (the equivalent cylindrical body 55 with channel 60, extends vertically);
the word line contact (46A) and the plurality of plate line contact segments (46B, 46C, 46D, 46E) each surrounds the cylindrical body (55, where the cylindrical aspect disclosed earlier by the Baenninger reference, where 46A-46E surround 60 laterally) in a corresponding plane perpendicular to the first direction (horizontal direction); and
the word line contact (46A) and the plurality of plate line contact segments (46B, 46C, 46D, 46E) are arranged in a sequence along the first direction (they are arranged in sequence vertically).
Regarding claim 7, the prior art of Baenninger et al. disclose the memory structure of claim 6, wherein each of the word line contact and the plurality of plate line contact segments has a substantially same first height along the first direction (Izumi Fig. 26 elements 46A-46E show the equivalent word line contact and plurality of plate line contact segments have substantially the same height).
Regarding claim 8, the prior art of Baenninger et al. disclose the memory structure of claim 6, wherein each pair of adjacent plate line contact segments has a substantially same first distance along the first direction (Izumi Fig. 26 elements 46B-46E show the equivalent word line contact and plurality of plate line contact segments have separation by the same distance in a vertical direction).
Regarding claims 10-12, each of the claim limitations is reliant upon the structural configuration that is satisfied in the rejection of claim 1. Therefore, if the structural configuration of the device is satisfied, then the functional outcomes of the limitations of claims 10-12 will be satisfied. It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). See MPEP 2112.01. Regarding claim 10, the prior art of Baenninger et al. disclose the memory structure of claim 1, wherein the source cap is configured to eliminate a parasitic leakage channel between the source line and the plurality of plate lines. Regarding claim 11, the prior art of Baenninger et al. disclose the memory structure of claim 10, wherein the source cap is further configured to suppress a breakdown leakage current between the source line and the plurality of plate lines. Regarding claim 12, the prior art of Baenninger et al. disclose the memory structure of claim 12, wherein the source cap is further configured to reduce a parasitic capacitance between the source line and the plurality of plate lines and to increase an operating speed of the memory structure.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Baenninger et al. (US 9,419,135) in view of Izumi et al. (US 9,401,309) in view of Nam et al. (US 9,461,061) in view of Kinney (US 10,790,304).
Regarding claims 2, Nam et al. disclose the memory structure of claim 1, however Baenninger does not disclose,
“wherein the plurality of plate lines are connected to a common voltage source”,
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Kinney discloses in Fig. 2, wherein the plurality of plate lines (equivalent elements are 36, 38) are connected to a common voltage source (“FIG. 2, the gates 36 and 38 of the non-ferroelectric transistors 30 and 32 are coupled with a common voltage source V, and the transistor gate 34 of the ferroelectric transistor 28 is coupled with a wordline WL.”, col. 7, lines 4-7).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use, “wherein the plurality of plate lines are connected to a common voltage source”, as disclosed by Kinney in the system of Baenninger, for the purpose of providing the electrical signals required to operate the memory devices. G. TSM: Teaching, Suggestion, Motivation Test.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Baenninger et al. (US 9,419,135) in view of Izumi et al. (US 9,401,309) in view of Nam et al. (US 9,461,061) in view of Zhang et al. (US 10,038,005).
Regarding claim 3, Baenninger et al. disclose the memory structure of claim 1, and Baenninger does not specify,
“wherein: the plurality of plate lines are connected to a plurality of independent voltage sources respectively”.
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Zhang discloses in Fig. 3, where each of the memory sites in the NAND string are independently controlled by each of WL0, WL1, WL2, WL3.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“wherein: the plurality of plate lines are connected to a plurality of independent voltage sources respectively”, as disclosed by Zhang in the system of Baenninger, for the purpose of providing the electrical signals required to operate the memory devices. G. TSM: Teaching, Suggestion, Motivation Test.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Baenninger et al. (US 9,419,135) in view of Izumi et al. (US 9,401,309) in view of Nam et al. (US 9,461,061) in view of Naruke et al. (US 11,569,256).
Regarding claim 4, the prior art of Baenninger et al. disclose the memory structure of claim 1, and Baenninger does not discloses wherein,
the word line contact (Baenninger does not disclose this aspect), the source line contact (Baenninger does disclose that 302 is potentially n-type, col. 12, lines 39-42) and the source cap (“the source contact 102 comprises single crystal silicon or polysilicon having a second conductivity type (e.g., n-type)”, col. 7, lines 21-23 ) have a same first type dopant (n-type dopant).
Again, Baenninger does not disclose, “where the word line contact … has a same first type dopant [e.g. the n-type dopant]”.
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Naruke discloses in Fig. 50, provided above, where the word line contact has a same first type dopant (“The semiconductor layer 501A is, for example, an n-type polysilicon layer. An n-type dopant concentration of the n-type polysilicon layer 501A serving as the word line WL is, for example, equal to or greater than an n-type dopant concentration of the source/drain region.”, col. 31, lines 51-55, where 501A is equivalent to Nam’s “word line contact”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“the word line contact, the source line contact and the source cap have a same first type dopant”, as disclosed by Naruke in the system of Baenninger, for the purpose of providing ohmic compatible conductor which can improve the signal path by removing a minute potential junction barrier. G. TSM: Teaching, Suggestion, Motivation Test.
Regarding claim 5, the prior art of Baenninger et al. disclose the memory structure of claim 4, and Baenninger discloses wherein, the cylindrical body (1) has a second type dopant (p-type) opposite from the first type dopant (1, “the semiconductor channel 1 comprises amorphous silicon or polysilicon having a first conductivity type (e.g., p-type)”, col. 7, lines 19-21).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Baenninger et al. (US 9,419,135) in view of Izumi et al. (US 9,401,309) in view of Nam et al. (US 9,461,061) in view of Nishikawa et al. (US 9,911,748).
Regarding claim 9, Baenninger et al. disclose the memory structure of claim 7, where Baenninger et al. do not disclose, “wherein a second height of the source cap along the first direction is no less than about 10 nm”.
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Nishikawa discloses in Fig. 12A, “wherein a second height of the source cap along the first direction is no less than about 10 nm”, since Nishikawa discloses, “The thickness of the gate dielectric layer 12 can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.”, col. 5, lines 37-40. Element “epitaxial channel portion 11”, col. 8, lines 34, which neighbors element 12, and has a lesser thickness than element 11. If element 12 has a thickness of 30 nm, and element 12 is about half or three times as thin as element 11, then it can be understood that element 11 has a thickness that is greater than two to three times greater than the thicknesses of 4 to 30 nm. This thickness for equivalent “source cap” then satisfies the claimed thickness.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“wherein a second height of the source cap along the first direction is no less than about 10 nm”, as disclosed by Nishikawa in the system of Baenninger, for the purpose of providing the dimensions that are required to achieve the device density of a three dimensional memory array. G. TSM: Teaching, Suggestion, Motivation Test.
Claims 13, 16, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 9,461,061) in view of Izumi et al. (US 9,401,309) in view of Baenninger et al. (US 9,419,135).
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Claim 13 element listing:
Nam’s claim 1 analogous features
Instant Application’s features
1. bottom conductive layer (BCL)
101, 100
902, 1102
2. (plurality of alternately arranged) insulating layer (DL)
106a through 106g and 129
906, 1106
3. (plurality of alternately arranged) conductive layers (CL)
175a through 175e
908, 1108 (not top most)
4. cylindrical body (CB)
135
924, 1124
5. cap layer (CapL)
120
922, 1122
6. top contact (TC)
150
926, 1126
7. bit line (BL)
190, 195
971, 1171
8. top conductive layer (TCL)
not shown
973, 1173
9. word line (WL)
175f
top most 908, 1108
10. plurality of plate lines (PL)
not shown
975
11. source line (SL)
not shown
956, 1156
Regarding claim 13, the prior art of Nam discloses in Fig. 1A (annotated and provided above), a memory structure (see title, “Vertical Memory Devices …”), comprising:
a bottom conductive layer (101, 100) having a first type dopant (“The impurity region 101 may include n-type impurities, e.g., phosphorous or arsenic”, col. 6, line 65 to col. 7, line 2);
a memory stack (“the substrate 100 may include a cell region I … Memory cells may be stacked in the cell region I”, col. 5, lines 12-14) on the bottom conductive layer (on 101, 100), the memory stack comprising a plurality of conductive layers (175a through 175e) alternatingly arranged with alternating portions of an insulating layer (insulating layers are plural 106 and 129, where portion of the plural 106 are between plural 175) which is contact with the cylindrical body (129 surrounds 135);
a cylindrical body (Element 135, where “The channel 135 may be formed on the semiconductor pattern 120 and have a hollow cylindrical shape or a cup shape.”, col. 5, lines 24-26, hereinafter referred to as ‘CB’) embedded in the memory stack (135 are in the memory stacks), the cylindrical body having a second type dopant opposite from the first type dopant (“The channel 135 may further include, e.g., p-type impurities such as boron (B).”, col. 5, lines 27-28), and the cylindrical body surrounded by the insulating layer (portion 129 surrounds the 135) ;
a cap layer (120) between the bottom conductive layer (101, 100) and the cylindrical body (135), the cap layer having the first type dopant (“the semiconductor pattern 120 may further include, e.g., n-type impurities such as phosphorous (P) or arsenic (As).”, col. 5, lines 21-23); and
a top contact (150) on the cylindrical body (on 135), the top contact having the first type dopant (“The pad 150 may further include, e.g., n-type impurities such as phosphorus or arsenic.”, col. 6, lines 6-8);
wherein:
the top contact (150) is coupled to a bit line (190, 195),
the cap layer (120) is in contact with the bottom conductive layer (in contact with 101, 100) and the cylindrical body (and in contact with 135).
Nam does not disclose,
“a top conductive layer of the memory stack is coupled to a word line
the plurality conductive layers other than the top conductive layer of the memory stack are coupled to a plurality of plate lines respectively,
the bottom conductive layer is coupled to a source line.”
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Izumi discloses in Fig. 26,
a top conductive layer (46A) of the memory stack is coupled to a word line (66F)
the plurality conductive layers (46B, 46C, 46D, 46E) other than the top conductive layer (not 46A) of the memory stack are coupled to a plurality of plate lines (66E, 66D, 66C, 66B) respectively,
the bottom conductive layer (equivalent elements 12 and portion of 14) is coupled to a source line (76).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“a top conductive layer of the memory stack is coupled to a word line
the plurality conductive layers other than the top conductive layer of the memory stack are coupled to a plurality of plate lines respectively,
the bottom conductive layer is coupled to a source line”, as disclosed by Izumi in the system of Nam, for the purpose of allowing for electrical signal to reach each of the word line contact, plate line contact segments, and the source line. G. TSM: Teaching, Suggestion, Motivation Test.
Nam does not disclose, “the cap laver is located lower in the memory structure than the plurality of conductive layers”. It is noted that Izumi appears to show the same in Fig. 26 as well.
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Baenninger discloses in Figs. 1A-1C, wherein the cap laver (102a) is located lower in the memory structure (120) than the plurality of conductive layers (33 being the lowest conductive layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“the cap laver is located lower in the memory structure than the plurality of conductive layers”, as disclosed by Baenninger in the system of Nam et al., for the purpose of minimizing leakage current at the low end of the channel. G. TSM: Teaching, Suggestion, Motivation Test.
Regarding claim 16, the prior art of Nam et al. disclose the memory structure of claim 13, and Nam discloses in Fig. 1A, wherein:
a top surface of the cap layer (top surface of 120) is lower than a bottom surface of a lowest conductive layer of the memory stack (175b is the lowest conductive layer that functions as a memory site, where 175a is a “ground selection line”, col. 6, lines 23-24), and is higher than a top surface of the bottom conductive layer (120 is higher than 101, 100).
Regarding claim 17, Nam et al. disclose the memory structure of claim 13, and Nam discloses in Fig. 1A, wherein:
a bottom surface of the top contact is higher than a top surface of a top conductive layer of the memory stack (lower surface of 150 is higher than all 175 conductors).
Regarding claim 20, Nam et al. disclose the memory structure of claim 13, and Nam discloses in Fig. 1A, further comprising:
an insulating layer (129) between the cylindrical body (135) and the plurality of conductive layers of the memory stack (175e -175b).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 9,461,061) in view of Izumi et al. (US 9,401,309) in view of Baenninger et al. (US 9,419,135) in view of Kinney (US 10,790,304).
Regarding claim 14, Nam et al. disclose the memory structure of claim 13, however Nam does not disclose,
“wherein the plurality of plate lines are connected to a common voltage source”,
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Kinney discloses in Fig. 2, wherein the plurality of plate lines (equivalent elements are 36, 38) are connected to a common voltage source (“FIG. 2, the gates 36 and 38 of the non-ferroelectric transistors 30 and 32 are coupled with a common voltage source V, and the transistor gate 34 of the ferroelectric transistor 28 is coupled with a wordline WL.”, col. 7, lines 4-7).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use, “wherein the plurality of plate lines are connected to a common voltage source”, as disclosed by Kinney in the system of Nam, for the purpose of providing the electrical signals required to operate the memory devices. G. TSM: Teaching, Suggestion, Motivation Test.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 9,461,061) in view of Izumi et al. (US 9,401,309) in view of Baenninger et al. (US 9,419,135) in view of Zhang et al. (US 10,038,005).
Regarding claim 15, Nam et al. disclose the memory structure of claim 13, and Nam does not specify, “wherein: the plurality of plate lines are connected to a plurality of independent voltage sources respectively”.
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Zhang discloses in Fig. 3, where each of the memory sites in the NAND string are independently controlled by each of WL0, WL1, WL2, WL3.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“wherein: the plurality of plate lines are connected to a plurality of independent voltage sources respectively”, as disclosed by Zhang in the system of Nam, for the purpose of providing the electrical signals required to operate the memory devices. G. TSM: Teaching, Suggestion, Motivation Test.
Claim 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 9,461,061) in view of Izumi et al. (US 9,401,309) in view of Baenninger et al. (US 9,419,135) in view of Ahn (US 11,276,703).
Regarding claim 18, Nam et al. disclose the memory structure of claim 13, however they do not disclose, “wherein:
the memory stack comprises a staircase structure including a plurality of steps each including a corresponding one of the plurality of conductive layers of the memory stack”.
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Ahn discloses in Fig. 2, provided above, wherein:
the memory stack comprises a staircase structure including a plurality of steps each including a corresponding one of the plurality of conductive layers of the memory stack (as shown in Fig. 2, the circled region shown the stack of conductors formed in a staggered “staircase” shape).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“wherein:
the memory stack comprises a staircase structure including a plurality of steps each including a corresponding one of the plurality of conductive layers of the memory stack”, as disclosed by Ahn in the system of Nam, for the purpose of providing easier access to the horizontal plate conductors during the manufacturing step of providing the vertical electrical contacts. G. TSM: Teaching, Suggestion, Motivation Test.
Regarding claim 19, Nam et al. disclose the memory structure of claim 18, and Izumi discloses in Fig. 26, further comprising:
a plurality of interconnect structures (66E to 66B) each electrically connected to the corresponding one of the plurality of conductive layers (46B to 46E) of the memory stack on the staircase structure (staircase feature already disclosed in the rejection of claim 18 by Ahn).
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893