DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/26/2025 has been entered.
Drawings
Prior objection to drawings is withdrawn in view of corrected drawings.
Specification
Prior objection to specification is withdrawn in view of amendments to the specification.
Claim Rejections - 35 USC § 112
Prior rejection of Claim 2 under 35 U.S.C. 112(d) or 35 U.S.C. 112 (pre-AIA ), 4th paragraph, is withdrawn in view of cancellation of claim 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3 and 14-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Konno et al. (US 2023/0062835 A1, of record).
Re Claim 1, Konno teaches a semiconductor device (Fig. 20) comprising:
a 1st carrier wafer (210, Figs. 8 and 20, para [0037], Examiner notes that a “carrier wafer” can be a substrate/support over which other devices/components are disposed, similar to the applicant, and the claim language does not preclude this treatment); and
a 1st semiconductor chip (200+201+202+203+204, Fig. 20, para [0030], Examiner notes that a “semiconductor chip” can be a substrate with devices and interconnection structures, similar to the applicant) comprising a substrate (200, Fig. 20, para [0030]) and a transistor structure (TR, Fig. 20, para [0030]) thereon, the substrate being on the 1st carrier wafer (210),
wherein the 1st carrier wafer (210) comprises at least one 1st pattern (220, Fig. 20, paras [0058] and [0106]),
wherein the at least one 1st pattern (220) comprises therein a 1st stress material (220 is made of aluminum nitride, para [0067]) which is different from a material forming the 1st carrier wafer (210 is made of silicon, para [0037]), and configured to expand or shrink by thermal processing (different materials having different coefficient-of-thermal-expansion, CTEs, are used for 210 and 220, paras [0037] and [0067]), and
wherein the 1st semiconductor chip (200+201+202+203+204) is on a 1st surface of the 1st carrier wafer (bottom surface of 210), and the at least one 1st pattern is on a 2nd surface (pattern 220 is on the top surface of 210), opposite to the 1st surface, of the 1st carrier wafer (bottom surface of 210).
Re Claim 3, Konno teaches the semiconductor device of claim 1, wherein the 1st stress material (220 is made of aluminum nitride) is a compressive stress material or a tensile stress material having a thermal expansion coefficient different from the material forming the 1st carrier wafer (different materials having different coefficient-of-thermal-expansion, CTEs, are used for 210 and 220, paras [0037] and [0067]).
Re Claim 14, Konno teaches a carrier wafer (210, Figs. 8 and 20, para [0037], Examiner notes that a “carrier wafer” can be a substrate/support over which other devices/components are disposed, similar to the applicant, and the claim language does not preclude this treatment) comprising:
a 1st surface (bottom surface of 210, Fig. 20) on which an integrated circuit (200+201+202+203+204, Fig. 20, para [0030], Examiner notes that a “integrated circuit” can be a substrate with devices and interconnection structures, similar to the applicant) is attached; and
a 2nd surface (top surface of 210, Fig. 20) opposite to the 1st surface (bottom surface of 210), wherein at least one pattern is formed on the 2nd surface (pattern 220 is formed on top surface of 210), and a stress material is included in the at least one pattern (220 is made of aluminum nitride, para [0067]),
wherein the stress material (220 is made of aluminum nitride, para [0067]) is different from a material forming the carrier wafer (210 is made of silicon, para [0037]), and configured to expand or shrink subject to thermal processing (different materials having different coefficient-of-thermal-expansion, CTEs, are used for 210 and 220, paras [0037] and [0067]), and
wherein the 1st surface does not include a pattern including the stress material (bottom surface of 210 does not have any pattern, see Fig. 20).
Re Claim 15, Konno teaches the carrier wafer of claim 14, wherein the stress material (220 is made of aluminum nitride) is a compressive stress material or a tensile stress material having a thermal expansion coefficient different from the material forming the carrier wafer (different materials having different coefficient-of-thermal-expansion, CTEs, are used for 210 and 220, paras [0037] and [0067]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2020/0006145 A1, of record), and further in view of Ait-Mani et al. (US 2018/0366389 A1, of record).
Re Claim 1 (Rejection-2), Li teaches a semiconductor device (Fig. 2) comprising:
a 1st carrier wafer (102e, Fig. 2, para [0033], Examiner notes that a “carrier wafer” can be a substrate/support over which other devices/components are disposed, similar to the applicant, and the claim language does not preclude this treatment); and
a 1st semiconductor chip (marked “1st chip” in annotated Fig. 2 below, Examiner notes that a “semiconductor chip” can be a substrate with devices and interconnection structures, similar to the applicant) comprising a substrate (102d, Fig. 2, para [0033]) and a transistor structure thereon (104a, Fig. 2, para [0029]), the substrate (102d) being on the 1st carrier wafer (102e),
a material forming the 1st carrier wafer (102e is made of silicon, para [0039]), and
wherein the 1st semiconductor chip (102d) is on a 1st surface of the 1st carrier wafer (top surface of 102e).
Li does not teach the following:
wherein the 1st carrier wafer comprises at least one 1st pattern,
wherein the at least one 1st pattern comprises therein a 1st stress material which is different from a material forming the 1st carrier wafer, and configured to expand or shrink by thermal processing, and
and the at least one 1st pattern is on a 2nd surface, opposite to the 1st surface, of the 1st carrier wafer.
However, as disclosed by Ait-Mani, one of ordinary skill in the art of semiconductor devices would recognize that bowing can be generated when a layer is formed on the wafer at a given temperature, the layer having a different coefficient of thermal expansion (CTE) than that of the wafer at a given temperature (para [0006]). Therefore, one would try to reduce or eliminate bowing as it would lead to defects, such as cracking or delamination and is detrimental to the semiconductor device (para [0007]).
Ait-Mani teaches a method for compensating bow, generated in a wafer comprising opposite first and second surfaces, where a patterned trenches are formed on both surfaces and are filled with materials such that it enables the bow to be compensated (Fig. 5, paras [0019] - [0021]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor wafers of Li (102a-e, para [0035]) by incorporating the bow-compensating pattern on the wafers as disclosed by Ait-Mani, where the patterned trenches are on both sides of the wafers (Fig. 5, paras [0019] - [0021], Ait-Mani). This would protect the semiconductor device from defects, such as cracking or delamination by reducing or eliminating bowing (para [0007], Ait-Mani).
Thus, Li modified by Ait-Mani discloses:
the 1st carrier wafer (102e, Li) comprises at least one 1st pattern (110, Fig. 5, paras [0090] – [0092], Ait-Mani),
wherein the at least one 1st pattern (110, Ait-Mani) comprises therein a 1st stress material (M2, which can be nitride, Fig. 5, paras [0093] - [0094], Ait-Mani) which is different from a material forming the 1st carrier wafer (102e is made of silicon, para [0039], Li), and configured to expand or shrink by thermal processing (different materials having different CTEs are used for the wafer and the stress material), and
and the at least one 1st pattern (110, Fig. 5, Ait-Mani) is on a 2nd surface (bottom surface of 102e, Li, similar to Fig. 5 of Ait-Mani), opposite to the 1st surface, of the 1st carrier wafer (top surface of 102e, Li).
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Re Claim 3, Li modified by Ait-Mani teaches the semiconductor device of claim 1, wherein the 1st stress material (M2, which can be nitride, Fig. 5, paras [0093] - [0094], Ait-Mani) is a compressive stress material or a tensile stress material having a thermal expansion coefficient different from the material forming the 1st carrier wafer (different materials having different CTEs are used for the wafer and the stress material, paras [0019]-[0054], [0081], [0089], [0097], Ait-Mani).
Re Claim 4, Li modified by Ait-Mani teaches the semiconductor device of claim 1, further comprising a 2nd semiconductor chip (marked “1st chip” in annotated Fig. 2 of Li above) vertically bonded (see annotated Fig. 2 of Li above) to the 1st semiconductor chip (“1st chip”).
Re Claim 5, Li modified by Ait-Mani teaches the semiconductor device of claim 4, wherein the 2nd semiconductor chip (“2nd chip”) is on a 2nd carrier wafer (102b, Fig. 2, para [0033], Li),
wherein the 2nd carrier wafer (102b, Li) comprises at least one 2nd pattern (100b, Fig. 5, paras [0084] – [0087], Ait-Mani), and
wherein the at least one 2nd pattern (100b, Ait-Mani) comprises therein a 2nd stress material (M1, which can be polyimide, Fig. 5, paras [0086] – [0087], Ait-Mani) which is different from a material forming the 2nd carrier wafer (102b is made of silicon, para [0039], Li), and configured to expand or shrink by the thermal processing (different materials having different CTEs are used for the wafer and the stress material).
Re Claim 6, Li modified by Ait-Mani teaches the semiconductor device of claim 5, wherein the 2nd semiconductor chip (“2nd chip”, Li) is on a 1st surface of the 2nd carrier wafer (bottom surface of 102b, Li), and the at least one 2nd pattern (100b, Ait-Mani) is formed on a 2nd surface (top surface of 102b, Li, similar to Fig. 5 of Ait-Mani), opposite to the 1st surface, of the 2nd carrier wafer (bottom surface of 102b, Li).
Re Claim 7, Li modified by Ait-Mani teaches the semiconductor device of claim 5, wherein the 1st stress material (M2 can be nitride, Alt-Mani) is a compressive stress material or a tensile stress material having a thermal expansion coefficient different from the material forming the 1st carrier wafer (102e is made of silicon, Li, and different materials having different CTEs), and
wherein the 2nd stress material (M1, can be polyimide, Ait-Mani) is the compressive stress material or the tensile stress material having a thermal expansion coefficient different from the material forming the 2nd carrier wafer (102b is made of silicon, Li, and different materials having different CTEs).
Re Claim 8, Li modified by Ait-Mani teaches the semiconductor device of claim 5, wherein the at least one 1st pattern (110, Ait-Mani) comprises a plurality of 1st patterns (set of trenches 110, paras [0090] – [0092], Ait-Mani), and the at least one 2nd pattern (100b, Ait-Mani) comprise a plurality of 2nd patterns (trenches 100b, paras [0084] – [0085], Ait-Mani), and wherein the plurality of 1st patterns are different from the plurality of 2nd patterns (pattern 100b is different from pattern 110, see Fig. 5, para [0092], Alt-Mani).
Re Claim 9, Li modified by Ait-Mani teaches the semiconductor device of claim 8, wherein the 1st stress material (M2 can be nitride, Alt-Mani) is different from the 2nd stress material (M1, can be polyimide, Ait-Mani).
Re Claim 10, Li modified by Ait-Mani teaches the semiconductor device of claim 5, wherein a bonding surface of the 1st semiconductor chip (top surface of “1st chip”, see annotated Fig. 2 of Li above) comprises a surface of a back-end-of-line (BEOL) layer of the 1st semiconductor chip (see Fig. 2, Li), and wherein a bonding surface of the 2nd semiconductor chip (bottom surface of “2nd chip”, see annotated Fig. 2 of Li above) bonded to the bonding surface of the 1st semiconductor chip (top surface of “1st chip”, see annotated Fig. 2 of Li above) comprises a surface of a BEOL layer of the 2nd semiconductor chip (see Fig. 2, Li).
Re Claim 11, Li modified by Ait-Mani teaches the semiconductor device of claim 10, wherein the at least one 1st pattern (110, Ait-Mani) is different from the at least one 2nd pattern (100b, Ait-Mani), and the 1st stress material (M2 can be nitride, Alt-Mani) is different from the 2nd stress material (M1, can be polyimide, Ait-Mani).
Response to Arguments
Applicant's arguments filed 09/26/2025 have been fully considered but they are not persuasive.
Applicant argued that “the Office action's reliance upon a prior-art "wafer" to teach a "semiconductor chip" is not consistent with the ordinary and customary meaning of the term “chip”.” Examiner respectfully disagrees with the applicant. The examiner respectfully points out that there is no specific definition of “carrier wafer” in the original specification of the applicant. Examiner notes that a “carrier wafer” can be a substrate/support over which other devices/components are disposed, similar to the applicant, and the claim language does not preclude this treatment. On the definition of semiconductor chip, Examiner notes that a “semiconductor chip” can be a substrate with devices and interconnection structures, similar to the applicant. Applicant is advised to further elaborate on the structural features of the applicant’s device that would differentiate it from the cited references, and include them into the limitations of the claim.
Regarding applicant’s argument on how the device of Fig. 20 of Konno et al. (US 2023/0062835 A1, of record) was prepared, the examiner would like to respectfully point out that the associated claims are device claims and not process claims. The patentability of a product does not depend on its method of production. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985).
Regarding 2nd rejection of claim 1, applicant argued that “Office action at pages 7-8 misconstrues the wafer 102d of Li et al. (US 2020/0006145 A1, of record) as teaching the claimed “1st semiconductor chip”.” The examiner respectfully disagrees with the applicant and would like to point out that the applicant has mistaken the examiner’s notation in the office action dated 5/29/2025. As also reiterated in this office action (see 2nd rejection of claim 1 above), the 1st carrier wafer is element 102e in Fig. 2 of Li. The 1st semiconductor element is defined by the whole block (see black rectangle marked “1st chip”, in annotated Fig. 2 of Li above) which includes the substrate 102d, IC elements 104a/b/c (paras [0029], Li) and support structures 110 (para [0030], Li). On the definition of semiconductor chip, Examiner again notes that a “semiconductor chip” can be a substrate with devices and interconnection structures, similar to the applicant.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898