Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15, 21-25 is rejected under 35 U.S.C. 102 as being anticipated by Yew et al. (US 20150041987 A1).
Regarding Claim 1, Yew et al. discloses an electronic package, comprising:
An electronic structure (100) including an electronic device (103) electrically connected to the first circuit pattern structure (by metallization layers 108, [0021]) having a top surface (103A) and a bottom surface (103B) opposite to the top surface;
A second circuit pattern structure (200, FIG. 6) disposed over the top surface of the electronic structure;
A plurality of first solders (116, 118, FIG. 5) disposed on the bottom surface of the electronic structure, and an encapsulant (122, molding material) which contacts a top surface, a bottom surface and a lateral surface of the first circuit structure (100, FIG. 6), and encapsulates the electronic structure, wherein at least a portion of the encapsulant is disposed between at least two of the plurality of first solders (FIG. 10A).
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Regarding Claim 2, Yew et al. discloses an electronic structure wherein the electronic device (120) is disposed between the first circuit pattern structure and the second circuit pattern structure, a thickness of the first circuit pattern structure (100) is greater than a thickness of the second circuit pattern structure (200).
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Regarding Claim 3, Yew et al. discloses a plurality of first solders (116) wherein at least one of the plurality of first solders vertically overlaps the electronic device:
“molding material 122 is molded on and around the connectors 116 and the die 120 (step 504 in FIG. 14).” [0029]
Regarding Claim 4, Yew et al. discloses a cross-sectional view (FIG. 7A) where the elevation of a bottom surface of the encapsulant (103) is lower than an elevation of the bottom surface of the first circuit pattern structure (100).
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Regarding Claim 5, Yew et al. discloses wherein in a cross-sectional view, a portion of the encapsulant (122) covering a lateral end of the second circuit pattern structure has different thickness at different elevations between a top edge (210) of the second circuit pattern structure and a bottom edge (103) of the second circuit pattern structure:
“In this embodiment, the gap G.sub.2 in the middle region is smaller than the gaps G.sub.1 and G.sub.3 at the edge regions of the packages 100 and 200 as illustrated in the cross-sectional view of FIG. 7C.”
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Regarding Claim 6, Yew et al. discloses a portion of the encapsulant (FIG. 10) covering the lateral end of the second circuit pattern structure has a first thickness at a higher level (at width Wa2) and a second thickness at a lower level (beyond width Wa1), where the second thickness is greater than the first thickness.
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Regarding Claim 7, Yew et al. discloses a second circuit pattern structure (200, FIG. 6); a second solder (118, FIG. 5) disposed between the first circuit pattern structure and the second circuit pattern structure; a core portion (120) disposed in the second solder where the core portion is closer to the first circuit pattern structure than the second, wherein the core portion is in a ball shape (FIG. 5).
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Regarding Claim 8, Yew et al. discloses an electronic package wherein in a cross-sectional view, the second solder has a first outer surface and a second outer surface opposite to the first outer surface, a first distance is between an outer surface of the core portion and a first outer surface of the second solder at an elevation, a second distance is between the outer surface of the core portion and the second outer surface of the second solder at an elevation, wherein the elevation of the first distance is the same as the elevation of the second distance, and the first distance is different from the second distance.
Regarding Claim 9, Yew et al. discloses second circuit pattern structure (200);
A plurality of second solders (within 124) electrically connecting the second circuit pattern structure and the first circuit pattern structure (100, 200, FIG. 12C);
A plurality of core portions disposed in the plurality of second solders respectively where the plurality of core portions are located at different elevations and wherein a plurality of core portions is in a ball shape (FIG. 10A).
“The die 120 is a logic die having core circuits, and may be, for example, a central processing unit (CPU) die. In some embodiments, the die 120 includes multiple stacked dies like a memory stacking.”
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Regarding Claim 10, Yew et al. discloses a plurality of core portions including a first core portion (206B, FIG. 6) and a second core portion (206A), the first core portion is closer to the electronic device than the second core portion, and an elevation of the first core portion is higher than an elevation of the second core portion.
“In some embodiments, the dies 206A and 206B are device dies having integrated circuit devices, such as transistors, capacitors, inductors, resistors (not shown), and the like, therein.”
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Regarding Claim 11, Yew et al. discloses a first circuit pattern structure (200) and second circuit pattern structure (100) disposed over the electronic structure; wherein a bottom surface of the second circuit pattern structure defines at least one indentation portion (intersection at 125 and 103A in FIG. 9A), wherein a gap (G2) is between the first circuit pattern structure and the second circuit pattern structure, and includes a first and second region (300A, 300B, 300C) with the first region being closer to a lateral surface of the second circuit pattern structure than the second region, and a height of the first region (300B) is less than a height of the second (300A). “In this embodiment, the gap G.sub.2 in the middle region is smaller than the gaps G.sub.1 and G.sub.3 at the edge regions of the packages 100 and 200 as illustrated in the cross-sectional view of FIG. 7A.”
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Regarding Claim 12, Yew et al. discloses an encapsulant (122) encapsulating the electronic structure, wherein a portion of the encapsulant fills the at least one indentation portion.
Regarding Claim 13, Yew et al. discloses an engagement structure (125) with at least one indentation portion (intersection at 125 and 103A in FIG. 9A) defined by two lateral surfaces of a bottom dielectric layer (108, [0021]) of the second circuit pattern structure (116), wherein a bottommost circuit layer is embedded in the bottom dielectric layer, wherein a top surface of the bottommost circuit layer is substantially aligned with a top surface of the bottom dielectric layer.
defined by a bottom surface of the second circuit pattern structure (116) and a portion of the encapsulant (122A) extends into at least one indentation portion.
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Regarding Claim 14, Yew et al. discloses a first indentation portion (125, FIG. 9A) and a second indentation portion (122A), the second indentation is closer to a lateral end of the second circuit pattern structure than the first indentation portion, and a width of the second indentation portion is less than a width of the first indentation portion.
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Regarding Claim 15, Yew et al. discloses a second circuit pattern structure which includes a top dielectric layer and a topmost circuit layer embedded in the top dielectric layer, wherein a top surface of the top dielectric layer and a top surface of the topmost circuit layer are substantially aligned with each other and collectively form a top surface of the second circuit pattern structure.
“Redistribution lines (RDLs) 112 and 113 are formed in the passivation layers 104 and 106, respectively, and are coupled to the metallization layers 108. In some embodiments, RDLs 112 and 113 are formed by depositing metal layers, patterning the metal layers, and forming the passivation layers 104 and 106 over the RDLs 112 and 113, respectively.” [0023]
Regarding Claim 21, Yew et al. discloses a second indentation portion (122A) disposed at a corner of the second circuit pattern structure (FIG. 9A).
Regarding Claim 22, Yew et al. discloses a first circuit pattern structure; an electronic device electrically connected to a top surface of the first circuit pattern structure (100); a second circuit pattern structure (200) disposed over the electronic device, wherein a bottom surface of the second circuit pattern structure defines at least one indentation portion facing the electronic device; and an encapsulant (122) encapsulating the electronic structure, and including at least one protrusion, wherein the at least one protrusion extends beyond the bottom surface of the second circuit pattern structure and fills the at least one indentation portion, and is configured to engage with the second circuit pattern structure (FIG.10B).
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Regarding Claim 23, Yew et al. discloses an encapsulant which continuously extends from at least one protrusion to a bottom surface (128) of the first circuit pattern structure (100).
Regarding Claim 24, Yew et al. discloses a second pattern structure (200) which includes a first dielectric layer (104) disposed on a top surface of a second dielectric layer (106), wherein the encapsulant has a lateral surface laterally overlapping a lateral surface of the second dielectric layer, wherein the lateral surface of the encapsulant is substantially aligned with a lateral surface of the first dielectric layer (FIG. 6).
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Regarding Claim 25, Yew et al. discloses a periphery portion of the second circuit pattern structure (200) horizontally overlaps the electronic device (FIG. 7C).
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Response to Arguments
Applicants' arguments filed August 20, 2025 have been fully considered but they are not persuasive.
Applicants amendment with regards to Claim 1 " wherein the encapsulant contacts a top surface, a bottom surface and a lateral surface of the first circuit pattern structure, wherein at least a portion of the encapsulant is disposed between at least two of the plurality of first solders." has been acknowledged.
Applicant argues that “as shown in Yew's FIGs. 5, 6, 10A (reproduced below) and relative description, the encapsulant 122 does not contact the bottom surface 103B and the lateral surface of the first circuit pattern structure 130. Thus, Yew fails to disclose that the encapsulant contacts a top surface, a bottom surface and a lateral surface of the first circuit pattern structure.”, however, Yew et al. does in fact meet this claim when the encapsulant is considered as 122, 122A, 125, and the molding materials of the first and second circuit pattern structures (see FIG. 6 below). A “top surface" does not necessarily suggest a topmost surface, and "a bottom surface" does not necessarily suggest "a bottommost surface", and the encapsulant 122 shown in Fig. 6 of Yew et al. contacts a top surface of the layer 104 of the first circuit pattern structure, and a bottom surface of the circuit element having solders of the first circuit pattern structure.
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Applicant further argues that “Applicant respectfully submits that, as shown in Yew's FIG. 6 (reproduced below) and relative description, the bottom surface of the second circuit pattern structure 200 is a flat surface, and does not define any indentation. Thus, Yew fails to disclose that a bottom surface of the second circuit pattern structure defines at least one indentation portion.” While FIG. 6 does show the bottom surface of the second circuit pattern structure 200 as a flat surface, FIG. 7A shows the bottom surface as not flat but with a radius of curvature.
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All amended claims have been addressed in the 102 rejection sections above.
Conclusion
Applicants' amendment did not necessitate a new ground of rejection in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joshua S Wyatt whose telephone number is (703) 756-1937. The examiner can normally be reached 7:00 AM - 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached on (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSHUA SCOTT WYATT/Examiner, Art Unit 2815
/JAY C KIM/Primary Examiner, Art Unit 2815