Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 12/15/2025, has been entered.
Claims 1-20 are pending and claims 17-20 are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 5-6, 9-10 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iizuka (US Pub. No. 2009/0040824 A1) in view of Ishibashi (US Pub. No. 2008/0158964 A1).
As to claim 1, Iizuka discloses an apparatus (fig 4) comprising:
a plurality of memory cells in a memory cell array region (fig 4, region R1; [0027]);
a plurality of word lines (WL0-6) extending across the memory cell array region (R1) and a peripheral region (peripheral region) in which no memory cell is arranged ([0027]), the plurality of word lines comprising a plurality of even-numbered word lines (even numbered word lines of WL0-6) and a plurality of odd-numbered word lines (odd numbered word lines of WL0-6), the odd-numbered word lines each disposed between a respective pair of the even-numbed word lines (WL0-6); and
a plurality of contact plugs (plugs VC), each contact plug (VC) of the plurality of contact plugs (VC) disposed on a respective even-numbered word line (even numbered word lines of WL0-6) of the plurality of even-numbered word lines in the peripheral region, each even-numbered word line having disposed thereon a respective one of the plurality of contact plugs (VC).
Iizuka does not disclose wherein an upper surface of each even-numbed word line is below a lowest surface of the respective one of the plurality of contact plugs; and
a plurality of insulating walls, each insulating wall of the plurality of insulating walls disposed above a respective odd-numbered word line of the plurality of odd-numbered word lines in the peripheral region, each odd-numbered word line having disposed above it a respective one of the plurality of insulating walls.
Nonetheless, Ishibashi discloses wherein an upper surface of each even-numbed word line is below a lowest surface of the respective one of the plurality of contact plugs (fig 2 and cross-section 5-5’ shown in fig 5, with contact plugs CP3, word lines WL0-31); and
a plurality of insulating walls (insulating layer 17 includes walls that are formed between integrally formed contacts CP3), each insulating wall of the plurality of insulating walls disposed above a respective odd-numbered word line of the plurality of odd-numbered word lines in the peripheral region (insulating layer 17 includes walls that are formed between integrally formed contacts CP3), each odd-numbered word line having disposed above it a respective one of the plurality of insulating walls (insulating layer 17 includes walls that are formed between integrally formed contacts CP3).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the contact plugs of Iizuka in the insulating layer as taught by Ishibashi since this will provide electrical connection to the word lines while preventing electrical connection do any adjacent electrical components.
As to claim 2, Iizuka in view of Ishibashi disclose the apparatus of claim 1 (paragraphs above),
Ishibashi further discloses an insulating film (17) over the plurality of word lines (WL) in the peripheral region (contact region), the insulating film (17) surrounding the plurality of contact plugs (CP3) and the plurality of insulating walls (portions of 17 between CP3) in the peripheral region (contact region).
As to claim 5, Iizuka in view of Ishibashi disclose the apparatus of claim 1 (paragraphs above),
Ishibashi further discloses a plurality of additional insulating walls on the even numbered word lines of the plurality of word lines in the peripheral region, respectively (insulating wall portions of 17 on even numbered word lines WL in contact region);
wherein each of the plurality of additional insulating walls is divided into two portions by an associated one of the plurality of contact plugs (contact plugs CP3 dividing two portions of additional insulating walls of 17 on the even numbered word lines WL in contact region).
As to claim 6, Iizuka in view of Ishibashi disclose the apparatus of claim 5 (paragraphs above),
Ishibashi further discloses wherein each of the plurality of insulating walls and each of the plurality of additional insulating walls extend from the memory cell array region to the peripheral region (wall portions of 17).
As to claim 9, Iizuka discloses an apparatus (fig 4) comprising:
a plurality of memory cells in a memory cell array region (fig 4, region R1; [0027]);
a plurality of word lines extending across a first peripheral region, the memory cell array region, and a second peripheral region, wherein the first and second peripheral regions have no memory cell, the plurality of word lines comprising even-numbered word lines and odd-numbered word lines, the odd-numbered word lines each disposed between a respective pair of the even-numbered word lines (fig 4, word lines WL);
a plurality of first contact plugs (VC) each disposed on a respective even-numbered word line of the even-numbered word lines in the first peripheral region (R2), each even-numbered word line having disposed thereon a respective one of the plurality of first contact plugs (VC);
a plurality second contact plugs each disposed on odd-numbered word line of the odd-numbered of word lines in the second peripheral region (VC), each odd-numbered word line having disposed thereon a respective one of the plurality of second contact plugs (VC).
Iizuka does not disclose wherein an upper surface of each even-numbed word line is below a lowest surface of the respective one of the plurality of contact plugs; and
a plurality of insulating walls, each insulating wall of the plurality of insulating walls disposed above a respective odd-numbered word line of the plurality of odd-numbered word lines in the peripheral region, each odd-numbered word line having disposed above it a respective one of the plurality of insulating walls.
Nonetheless, Ishibashi discloses wherein an upper surface of each even-numbed word line is below a lowest surface of the respective one of the plurality of contact plugs (fig 2 and cross-section 5-5’ shown in fig 5, with contact plugs CP3, word lines WL0-31); and
a plurality of insulating walls (insulating layer 17 includes walls that are formed between integrally formed contacts CP3), each insulating wall of the plurality of insulating walls disposed above a respective odd-numbered word line of the plurality of odd-numbered word lines in the peripheral region (insulating layer 17 includes walls that are formed between integrally formed contacts CP3), each odd-numbered word line having disposed above it a respective one of the plurality of insulating walls (insulating layer 17 includes walls that are formed between integrally formed contacts CP3).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the contact plugs of Iizuka in the insulating layer as taught by Ishibashi since this will provide electrical connection to the word lines while preventing electrical connection do any adjacent electrical components.
As to claim 10, Iizuka in view of Ishibashi disclose the apparatus of claim 9 (paragraphs above),
Ishibashi further discloses an insulating film (17) over the plurality of word lines (WL) in the first and second peripheral regions (contact region), the insulating film surrounding the plurality of first contact plugs (CP3), the plurality of second contact plugs (CP3), the plurality of first insulating walls (wall portions of 17) and the plurality of second insulating walls (17) in the first and second peripheral regions.
As to claim 13, Iizuka in view of Ishibashi disclose the apparatus of claim 9 (paragraphs above),
Ishibashi further discloses a plurality of third insulating walls each disposed on a respective even-numbered word line of the even-numbered word lines in the first peripheral region, respectively (wall portions of 17); and
a plurality of fourth insulating walls each disposed on a respective odd-numbered word line of the odd-numbered word lines in the second peripheral region, respectively (wall portions of 17);
wherein each of the plurality of third insulating walls is divided into two portions by an associated one of the plurality of first contact plugs, respectively (contact plugs CP3 dividing two portions of additional insulating walls of 17 on the even numbered word lines WL in contact region); and
wherein each of the plurality of fourth insulating walls is divided into two portions by an associated one of the plurality of second contact plugs, respectively (contact plugs CP3 dividing two portions of additional insulating walls of 17 on the even numbered word lines WL in contact region).
As to claim 14, Iizuka in view of Ishibashi disclose the apparatus of claim 9 (paragraphs above),
Ishibashi further discloses wherein each of the first insulating walls and each of the second insulating walls extend across the first peripheral region, the memory cell array region and the second peripheral region (wall portions of 17).
Claim(s) 3-4 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iizuka in view of Ishibashi and further in view of Takesako (US Pub. No. 2014/0377934 A1).
As to claim 3, Iizuka in view of Ishibashi disclose the apparatus of claim 2 (paragraphs above),
Iizuka in view of Ishibashi do not disclose the insulating film comprises a different insulating material than each of the plurality of insulating walls.
Nonetheless, Takesako discloses wherein the insulating film (19’) comprises a different insulating material than each of the plurality of insulating walls ([0121] insulating film 19’ is silicon dioxide; and [0120] film 19 is silicon nitride).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the walls and insulating layer of Iizuka in view of Ishibashi from different materials as taught by Takesako since this will provide improved electrical insulating properties.
As to claim 4, Iizuka in view of Ishibashi and Takesako disclose the apparatus of claim 3 (paragraphs above),
Takesako further discloses wherein the insulating film comprises silicon dioxide ([0121]) and each of the plurality of insulating walls comprises silicon nitride ([0120]).
As to claim 11, Iizuka in view of Ishibashi disclose the apparatus of claim 10 (paragraphs above),
Iizuka in view of Ishibashi do not disclose the insulating film comprises a different insulating material than each of the plurality of insulating walls.
Nonetheless, Takesako discloses wherein the insulating film (19’) comprises a different insulating material than each of the plurality of insulating walls ([0121] insulating film 19’ is silicon dioxide; and [0120] film 19 is silicon nitride).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the walls and insulating layer of Iizuka in view of Ishibashi from different materials as taught by Takesako since this will provide improved electrical insulating properties.
As to claim 12, Iizuka in view of Ishibashi and Takesako disclose the apparatus of claim 11 (paragraphs above),
Takesako further discloses wherein the insulating film comprises silicon dioxide and each of the plurality of first insulating walls and the plurality of second insulating walls comprises silicon nitride ([0121] insulating film 19’ is silicon dioxide; and [0120] film 19 is silicon nitride).
Claim(s) 7-8 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iizuka in view of Ishibashi and further in view of Kim et al. (US Pub. No. 2022/0189967 A1), hereafter referred to as Kim.
As to claim 7, Iizuka in view of Ishibashi disclose the apparatus of claim 1 (paragraphs above).
Iizuka in view of Ishibashi do not disclose wherein each of the plurality of the word lines has a first electrode portion and a second electrode portion on the first electrode portion in the memory cell array region, and
wherein each of the plurality of the word lines in the peripheral region has the first electrode portion.
Nonetheless, Kim discloses a similar apparatus comprising word lines (fig 3B, word lines 120) wherein each of the plurality of the word lines has a first electrode portion and a second electrode portion on the first electrode portion in the memory cell array region (first electrode portion 120a and second portion 120b), and
wherein each of the plurality of the word lines in the peripheral region has the first electrode portion (fig 3E, word lines including first portion 120a in the peripheral region).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the word lines of Iizuka in view of Ishibashi with the first and second electrode portions as taught by Kim since this will improve the electrical properties of the gate contact.
As to claim 8, Iizuka in view of Ishibashi and Kim disclose the apparatus of claim 7 (paragraphs above).
Kim further discloses wherein the first electrode portion comprises titanium nitride, and the second electrode portion comprises polysilicon doped with impurities ([0041]).
As to claim 15, Iizuka in view of Ishibashi disclose the apparatus of claim 9 (paragraphs above).
Iizuka in view of Ishibashi do not disclose wherein each of the plurality of the word lines has a first electrode portion and a second electrode portion on the first electrode portion in the memory cell array region, and
wherein each of the plurality of the word lines in the first and second peripheral regions has the first electrode portion.
Nonetheless, Kim discloses a similar apparatus comprising word lines (fig 3B, word lines 120) wherein each of the plurality of the word lines has a first electrode portion and a second electrode portion on the first electrode portion in the memory cell array region (first electrode portion 120a and second portion 120b), and
wherein each of the plurality of the word lines in the peripheral region has the first electrode portion (fig 3E, word lines including first portion 120a in the peripheral region).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the word lines of Iizuka in view of Ishibashi with the first and second electrode portions as taught by Kim since this will improve the electrical properties of the gate contact.
As to claim 16, Iizuka in view of Ishibashi and Kim disclose the apparatus of claim 15 (paragraphs above).
Kim further discloses wherein the first electrode portion comprises titanium nitride, and the second electrode portion comprises polysilicon doped with impurities ([0041]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2016/0233297A1 and US Patent No. 8,743,580B2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 1/5/2026