DETAILED ACTION
This Office action responds to Applicant’s RCE amendments filed on 04/22/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 02/27/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/22/2026 has been entered.
Amendment Status
The amendment filed as an RCE submission on 04/22/2026, responding to the Office action mailed on 02/272026 has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-6, 8-11, and 14-16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi (US 2023/0162080) in view of Deen (US 2022/0037313) in view of Hidaka (US 2021/0167271).
Regarding claim 1, Kikuchi shows (see, e.g., Kikuchi: figs. 1A-1E) most aspects of the instant invention including a quantum computing (QC) chip module 1, comprising:
An interposer chip 30 (see, e.g., Kikuchi: par. [0066] and [0073]) having a footprint
A qubit chip bump 31 (see, e.g., Kikuchi: par. [0078]) bonded to the interposer chip 30 and arranged so that the qubit chip 10 extends beyond the footprint of the interposer chip 30 (see, e.g., Kikuchi: par. [0061]) and over a second interposer chip 20 that is distinct from the interposer chip 30
wherein:
The interposer chip 30 extends beyond an edge of the qubit chip 10
Kikuchi, however, fails (see, e.g., Kikuchi: figs. 1A-1E) to show a wiring harness connected to the interposer chip 30. Moreover, Kikuchi shows that lateral wiring used for connection of terminals between chips, must consider the energy loss due to an impedance mismatch with respect to a connection portion and superimposition of an unnecessary frequency component(s) (noise) on a signal easily occur. Thus, it is required to keep a distance between terminals to the minimum necessary (see, e.g., Kikuchi: par. [0016]).
Deen, in a similar device to Kikuchi, shows (see, e.g., Deen: fig. 4B and 5, and also par. [0041]) a wiring harness 419B/421B/525 connected to the interposer chip 415B/520. Deen also teaches (see, e.g., Deen: figs. 4B and 5, and also par. [0041]) that the ion trap chip 502/interposer component 520 is connected to the integrated switching apparatus 515 via an interconnect 525 (e.g., cable, wiring, and/or the like) in order to have signal communication direct between the integrated switching apparatus 515 and the ion trap chip 502/interposer component 520. Deen also shows that the ion trap chip 502 can be used as a quantum computing system that generates qubits (see, e.g., Deen: par. 0051]), and further shows that the integrated switching network/apparatus 515 comprises a plurality of monolithically-integrated controls and/or switches configured to condition a voltage signal applied to at least one of the plurality of electrodes (see, e.g., Deen: abstract)
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the wiring harness connected to the interposer chip of Deen in device of Kikuchi, to have signal communication direct between the qubit chip/interposer chip (the ion trap chip/interposer component) and the controller (the integrated switching apparatus), where the signal communication is configured to condition a voltage signal applied to at least one of the plurality of electrodes.
Kikuchi in view of Deen, however, fails (see, e.g., Kikuchi: figs. 1A-1E, and see, e.g., Deen: figs. 4B and 5) to show that the wiring harness is connected to the interposer chip 30 via solder bump bonds. Hidaka, in a similar device to Kikuchi in view of Deen, shows (see, e.g., Hidaka: fig. 2, and annotated figs. 2 and 12) that the wiring harness 13 is connected to the interposer chip via solder bump bonds 15 (see, e.g., Hidaka: par. [0040]). Hidaka also shows (see, e.g., Hidaka: fig. 2, and annotated figs. 2 and 12) that the superconductive solder bumps 15 are formed to join the wiring harness 13 with the quantum bit device through the interpose in order to transmit the superconductive magnetic flux quantum bits 14 on different coupled substrates.
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It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the solder bumps of Hidaka between the wiring harness and the interposer in the device of Kikuchi in view of Deen, to join the wiring harness with the quantum bit device through the interpose in order to transmit the superconductive magnetic flux quantum bits on different coupled substrates.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi in view of Deen in view of Hidaka in further view of Pourrahimi (US 6510604).
Regarding claim 2, Kikuchi in view of Deen in view of Hidaka shows (see, e.g., Kikuchi: figs. 1A-1E, and also see, e.g., Deen: fig. 4B and 5) most aspects of the instant invention including:
The wiring harness 419B/421B/525 (see, e.g., Deen: fig. 4B and 5)
The qubit chip 502 that is controlled and read by electrical signals (see, e.g., Deen: abstract) in the wiring harness 419B/421B/525 (see, e.g., Deen: fig. 4B and 5)
Kikuchi in view of Deen in view of Hidaka, however, fails (see, e.g., Kikuchi: figs. 1A-1E, and also see, e.g., Deen: fig. 4B and 5) to show that the wiring harness 419B/421B/525 comprises a superconducting flexible cable. Pourrahimi, in a similar device to Kikuchi in view of Deen in view of Hidaka, shows (see, e.g., Pourrahimi: fig.6, col.1/II22-32, and abstract) shows a wiring harness that comprises a superconducting flexible cable. Pourrahimi also shows that the cables can offer improved flexibility while maintaining a high current carrying capacity and, advantageously, the superconducting filaments of the cables can be formed from relatively brittle materials having comparatively high critical temperatures (see, e.g., Pourrahimi: abstract).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the superconductor flexible cable of Pourrahimi in the wiring harness of Kikuchi in view of Deen in view of Hidaka, to improve flexibility while maintaining a high current carrying capacity at high critical temperatures.
Regarding claim 3, Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows (see, e.g., Kikuchi: figs. 1A-1E) that a gap between the qubit chip 10 and the interposer chip 30 is defined by a final height of the bump bonds 31 that connect the qubit chip 10 to the interposer chip 30.
Regarding claim 4 Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows (see, e.g., Kikuchi: figs. 1A-1E) that:
The qubit chip 10 extends to horizontally beyond the interposer chip 30
The interposer chip 30 extends substantially vertically from the qubit chip 10
Claims 5, 8-10, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi (US 2023/0162080) in view of Deen (US 2022/0037313) in view of Hidaka (US 2021/0167271) in further view of Pourrahimi (US 6510604).
Regarding claim 5, Kikuchi shows (see, e.g., Kikuchi: figs. 1A-1E, and 3A-3C) most aspects of the instant invention including a quantum computing (QC) chip module 1, comprising:
A plurality of QC chip modules 10/20 connected in a row (see, e.g., Kikuchi: figs. 3A-3C)
Each QC chip module 10/20 (see, e.g., Kikuchi: figs. 3A-3C) comprising an interposer chip 30 having a footprint (see, e.g., Kikuchi: 3A-3C)
Each QC chip 10/20 comprising a qubit chip bump 31 bonded to the interposer 30 (see, e.g., Kikuchi: par. [0078])
Each interposer chip 30 extends beyond an edge of the qubit chip 10/20
Kikuchi, however, fails (see, e.g., Kikuchi: figs. 3A-3C) to show that the plurality of qubit chips 10/20 extend beyond the footprint of the interposer chips 30 and over a second interposer chip that is distinct from the interposer chip. Kikuchi, in a similar embodiment to Kikuchi, shows (see, e.g., Kikuchi: figs. 1A-1E) a qubit chip 10 that extends beyond the footprint of the interposer chips 30 and over a second interposer chip that is distinct from the interposer chip 20 (see, e.g., Kikuchi: par. [0061]). Kikuchi further shows that the qubit chip 10 that extends beyond the footprint of the interposer chips 30 is one of the arrangements that facilitates a chip configuration that is capacitively or inductively coupled (see, e.g., Kikuchi: par. [0065]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use the qubit chip (that extends beyond the footprint of the interposer chips) of Kikuchi (see, e.g., Kikuchi: figs. 1A-1E) in the plurality of qubit chips of Kikuchi (see, e.g., Kikuchi: figs. 3A-3C) to facilitate a chip configuration that is capacitively or inductively coupled.
Kikuchi, however, fails (see, e.g., Kikuchi: figs. 3A-3C) to show that the plurality of qubit chips 10/20 extend beyond the footprint of the interposer chips 30. Kikuchi, in a similar embodiment to Kikuchi, shows (see, e.g., Kikuchi: figs. 1A-1E) a qubit chip 10 that extends beyond the footprint of the interposer chips 30 (see, e.g., Kikuchi: par. [0061]). Kikuchi further shows that the qubit chip 10 that extends beyond the footprint of the interposer chips 30 is one of the arrangements that facilitates a chip configuration that is capacitively or inductively coupled (see, e.g., Kikuchi: par. [0065]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use in the plurality of qubit chips either the qubit chip (that extends beyond the footprint of the interposer chips and over a second interposer chip that is distinct from the interposer chip) of Kikuchi (see, e.g., Kikuchi: figs. 1A-1E) or the qubit chip (that do not extends beyond the footprint of the interposer chips) of Kikuchi (see, e.g., Kikuchi: figs. 3A-3C) because these were recognized in the semiconductor art for their use as qubit chips/interposers structures in the superconducting/semiconductor devices, as taught by Kikuchi and by Kikuchi, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Kikuchi, however, fails (see, e.g., Kikuchi: figs. 1A-1E) to show a wiring harness connected to the interposer chip 30. Moreover, Kikuchi shows that lateral wiring used for connection of terminals between chips, must consider the energy loss due to an impedance mismatch with respect to a connection portion and superimposition of an unnecessary frequency component(s) (noise) on a signal easily occur. Thus, it is required to keep a distance between terminals to the minimum necessary (see, e.g., Kikuchi: par. [0016]).
Deen, in a similar device to Kikuchi, shows (see, e.g., Deen: fig. 4B and 5, and also par. [0041]) a wiring harness 419B/421B/525 connected to the interposer chip 415B/520. Deen also teaches (see, e.g., Deen: figs. 4B and 5, and also par. [0041]) that the ion trap chip 502/interposer component 520 is connected to the integrated switching apparatus 515 via an interconnect 525 (e.g., cable, wiring, and/or the like) in order to have signal communication direct between the integrated switching apparatus 515 and the ion trap chip 502/interposer component 520. Deen also shows that the ion trap chip 502 can be used as a quantum computing system that generates qubits (see, e.g., Deen: par. 0051]), and further shows that the integrated switching network/apparatus 515 comprises a plurality of monolithically-integrated controls and/or switches configured to condition a voltage signal applied to at least one of the plurality of electrodes (see, e.g., Deen: abstract)
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the wiring harness connected to the interposer chip of Deen in device of Kikuchi, to have signal communication direct between the qubit chip/interposer chip (the ion trap chip/interposer component) and the controller (the integrated switching apparatus), where the signal communication is configured to condition a voltage signal applied to at least one of the plurality of electrodes.
Kikuchi in view of Deen further shows that the qubit chip 502 that is controlled and read by electrical signals (see, e.g., Deen: abstract) in the wiring harness 419B/421B/525 (see, e.g., Deen: fig. 4B and 5).
Kikuchi in view of Deen, however, fails (see, e.g., Kikuchi: figs. 1A-1E, and see, e.g., Deen: figs. 4B and 5) to show that the wiring harness is connected to the interposer chip 30 via solder bump bonds. Hidaka, in a similar device to Kikuchi in view of Deen, shows (see, e.g., Hidaka: fig. 2, and annotated figs. 2 and 12) that the wiring harness 13 is connected to the interposer chip via solder bump bonds 15 (see, e.g., Hidaka: par. [0040]). Hidaka also shows (see, e.g., Hidaka: fig. 2, and annotated figs. 2 and 12) that the superconductive solder bumps 15 are formed to join the wiring harness 13 with the quantum bit device through the interpose in order to transmit the superconductive magnetic flux quantum bits 14 on different coupled substrates.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the solder bumps of Hidaka between the wiring harness and the interposer in the device of Kikuchi in view of Deen, to join the wiring harness with the quantum bit device through the interpose in order to transmit the superconductive magnetic flux quantum bits on different coupled substrates.
Kikuchi in view of Deen in view of Hidaka, however, fails (see, e.g., Kikuchi: figs. 1A-1E, and also see, e.g., Deen: fig. 4B and 5) to show that the wiring harness 419B/421B/525 comprises a superconducting flexible cable. Pourrahimi, in a similar device to Kikuchi in view of Deen, shows (see, e.g., Pourrahimi: fig.6, col.1/II22-32, and abstract) shows a wiring harness that comprises a superconducting flexible cable. Pourrahimi also shows that the cables can offer improved flexibility while maintaining a high current carrying capacity and, advantageously, the superconducting filaments of the cables can be formed from relatively brittle materials having comparatively high critical temperatures (see, e.g., Pourrahimi: abstract).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the superconductor flexible cable of Pourrahimi in the wiring harness of Kikuchi in view of Deen in view of Hidaka, to improve flexibility while maintaining a high current carrying capacity at high critical temperatures.
Regarding claim 8 Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows (see, e.g., Kikuchi: figs. 1A-1E) that a gap between the qubit chip 10 and the interposer chip 30 is defined by a final height of the bump bonds 31 that connect the qubit chip 10 to the interposer chip 30.
Kikuchi in view of Deen in view of Hidaka of Pourrahimi shows (see, e.g., Kikuchi: figs. 1A-1E, and 3A-3C) shows a plurality of QC chip modules 10/20 (see, e.g., Kikuchi: figs. 3A-3C), where the gap between the qubit 10/20 and the interposer chip 30 is the same size as another gap between the qubit chip 10 and another interposer chip 20 within any of the module of the plurality of QC chip modules 10/20.
Regarding claim 9, Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows (see, e.g., Kikuchi: figs. 1A-1E, and 2A-2C) shows a plurality of QC chip modules (see, e.g., Kikuchi: figs. 2A-2C) arranged in a tiled formation to form an air-gapped connection between the qubit chip 101 of a first QC chip module 10 and the interposer chip 201 of a neighboring QC chip module 20.
Regarding claim 10, Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows (see, e.g., Kikuchi: figs. 1A-1E, and 2A-2C) shows the plurality of QC chip modules (see, e.g., Kikuchi: figs. 2A-2C) are arranged on a rigid backer 401.
Regarding claim 14, Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows (see, e.g., Kikuchi: figs. 1A-1E, and 2A-2C) that:
The rigid backer 401 holds all the plurality of QC modules 10/20
An inter-module gap between one qubit chip 10/20 and a neighboring interposer chip is the same as an intra-module bump gap (see, e.g., Kikuchi: figs. 1A-1E), wherein the neighboring chip is the second interposer chip 30
Regarding claim 15, Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows (see, e.g., Kikuchi: figs. 1E, and 3C) a coupling 11/12 or 15/25 between qubit chips 10/20 on neighboring QC modules comprises a capacitive coupling across an air gap between the neighboring QC modules (see, e.g., Kikuchi: par. [0065]).
Regarding claim 16, Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows (see, e.g., Kikuchi: figs. 1E, and 3C) a coupling 11/12 or 15/25 between qubit chips 10/20 on neighboring QC modules comprises a inductive coupling across an air gap between the neighboring QC modules (see, e.g., Kikuchi: par. [0065]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi in further view of Makino (US 2008/0054491).
Regarding claim 6, Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows a plurality of QC modules 10/20 (see, e.g., Kikuchi: figs. 3A-3C) that have the qubit chip 10/20 (see, e.g., Kikuchi: figs. 3A-3C), the interposer chip 30 (see, e.g., Kikuchi: figs. 3A-3C), and the wiring harness 419B/421B/525 (see, e.g., Deen: fig. 4B and 5, and also par. [0041]).
Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi, however, fails to show that the qubit chip 10/20 (see, e.g., Kikuchi: figs. 3A-3C), the interposer chip 30 (see, e.g., Kikuchi: figs. 3A-3C), and the wiring harness 419B/421B/525 (see, e.g., Deen: fig. 4B and 5, and also par. [0041]) are arranged in a L-shape geometry. However, it is noted that the specification fails to provide teachings about the criticality of having the qubit chip 10/20 (see, e.g., Kikuchi: figs. 3A-3C), the interposer chip 30 (see, e.g., Kikuchi: figs. 3A-3C), and the wiring harness 419B/421B/525 (see, e.g., Deen: fig. 4B and 5, and also par. [0041]) arranged in a L-shape geometry, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the shape of arrangement of the qubit chip 10/20 (see, e.g., Kikuchi: figs. 3A-3C), the interposer chip 30 (see, e.g., Kikuchi: figs. 3A-3C), and the wiring harness 419B/421B/525 (see, e.g., Deen: fig. 4B and 5, and also par. [0041]), disclosed by Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular L-shape claimed by applicant is nothing more than one of numerous contour shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Dailey, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed L-shape of a redistribution layer on the plane where the interconnection layer is located is known in the art: Makino, in the same field of endeavor, teaches (see, e.g., Makino: fig. 2) that the shape of arrangement of the chip 12ASIC, the interposer chip 13, and the wiring harness 16MCP pad has a L-shape (see, e.g., Makino: par. [0064]).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the L-shape of Makino, because the arrangement of the chip, the interposer chip, and the wiring harness is known in the semiconductor art to have a L-shape for its use as a chip/interposer/wiring similarly used for in instant invention of Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi, as suggested by Makino, and implementing a known structure shape for its conventional use/purpose would have been a common-sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi in further view of Barwicz (US 2018/0358778).
Regarding claim 11, Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi shows a plurality of QC modules 10/20 (see, e.g., Kikuchi: figs. 3A-3C) that have the qubit chip 10/20 (see, e.g., Kikuchi: figs. 3A-3C) and the plurality of QC chip modules (see, e.g., Kikuchi: figs. 2A-2C) are arranged on a rigid backer 401.
Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi, however, fails (see, e.g., Kikuchi: figs. 2A-2C) to show that the rigid backer 401 includes an alignment ridge to facilitate an in-plane alignment of the QC chip modules 10/20. Barwicz, in a similar semiconductor device to Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi, shows (see, e.g., Barwicz: figs. 1-2) that the rigid backer 120 includes an alignment ridge 50a to facilitate an in-plane alignment of the chips 100. Barwicz also shows that the self-alignment of the chips is provided by constraining the motions to lithographically defined mechanical stops that are aligned to ridge structures 50a (see, e.g., Barwicz: par. [0019]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the alignment ridge of Barwicz in the rigid backer of Kikuchi in view of Deen in view of Hidaka in view of Pourrahimi, to improve the self-alignment of the chips by constraining the motions to lithographically defined mechanical stops that are aligned to ridge structures.
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the new grounds of rejection. Examiner has read and considered Applicants’ arguments and finds them to be unpersuasive.
The applicants argue:
Kikuchi in view of Deen fails to anticipate or render obvious the amended limitation of "… a wiring harness connected to the interposer chip via solder bump bonds ", as recited in claims 1 and 5.
The examiner responds:
In view of the new grounds of rejection, Hidaka, in a similar device to Kikuchi in view of Deen, shows (see, e.g., Hidaka: fig. 2, and annotated figs. 2 and 12) that the wiring harness 13 is connected to the interposer chip via solder bump bonds 15 (see, e.g., Hidaka: par. [0040]). Hidaka also shows (see, e.g., Hidaka: fig. 2, and annotated figs. 2 and 12) that the superconductive solder bumps 15 are formed to join the wiring harness 13 with the quantum bit device through the interpose in order to transmit the superconductive magnetic flux quantum bits 14 on different coupled substrates.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the solder bumps of Hidaka between the wiring harness and the interposer in the device of Kikuchi in view of Deen, to join the wiring harness with the quantum bit device through the interpose in order to transmit the superconductive magnetic flux quantum bits on different coupled substrates.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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