DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to RCE filed on October 23, 2025.
Claim Objections
Claims 1 and 5 are objected to because of the following informalities: the last three lines of claims 1 and 5 should be amended, because it appears that Applicants claim that the semiconductor substrate can be a stacked semiconductor substrate such as a nitride semiconductor substrate bonded to a silicon substrate; also, “a gallium nitride substrate” appears to be “a nitride semiconductor substrate”; in addition, the phrases “at least one of” and “and/or” do not agree with each other grammatically. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5 and 8 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Shiigi et al. (US 2017/0111037, Foreign Priority: Oct. 19, 2015 (JP)), as evidenced by Roedle et al. (US 2010/0006860)
Regarding claim 1, Shiigi et al. disclose for a manufacturing method of a semiconductor device having a transistor portion (right-side portion having transistors, Fig. 13) and a diode portion (left-side portion having diode 80, Fig. 13) that
forming a drift region (n- drift region 2, Fig. 13) of a first conductivity type (n-type, Fig. 13) in a semiconductor substrate (composite substrate of the semiconductor base body 100 and oxide film 78, Fig. 13), because Applicants do not specifically claim whether it is a sole single, homogeneous substrate or multilayers including a semiconductor substrate such as semiconductor-on-insulator (SOI) wafer, and the Merriam-Webster dictionary defines a word “substratum” as “an underlying support or foundation”, therefore, a composite layer of the silicon carbide base body 100 ([0045]) and the oxide film 78 by Shiigi et al. is the underlying support of several components, therefore, a layer 100/78 can correspond to the semiconductor substrate in the claimed invention, and;
providing a first well region (p-type base region 71, Fig. 13) of a second conductivity type (p-type, Fig. 13) under an upper surface of the semiconductor substrate (upper surface of 100/78, Fig. 13) above the drift region (2, Fig. 1), because portions of the p-type base region 71 by Shiigi et al. in the center region of Fig. 13 are under an upper surface of the composite substrate of 100/78 (Fig. 13);
providing, in the diode portion (left-side portion having diode 80, Fig. 13), an anode region (p-type polysilicon layer 81, Fig. 13) of a second conductivity type (p-type polysilicon, Fig. 13, [0097]) under the upper surface of the semiconductor substrate (upper surface of 100/78, Fig. 13), because the p-type polysilicon layer 81 by Shiigi et al. is disposed under the upper surface of the composite substrate of 100/78 in the temperature sensing region 50 (Fig. 13); and
providing a first high concentration region (p+-type contact region 73, Fig. 13) of a second conductivity type (p+-type, Fig. 4) having a higher doping concentration (“p+”, Fig. 13) than the anode region (“p-type”, [0097]), because it is known in the art that “p+” typically denotes a concentration higher than “p”, under the upper surface of the semiconductor substrate (upper surface side of 100/78, Fig. 13),
wherein the first high concentration region (73, Fig. 13) being in direct contact with the first well region (71, Fig. 13),
wherein the first high concentration region (73, Fig. 13) is between the anode region (81, Fig. 13) and the first well region (71, Fig. 13),
wherein the first high concentration region (73, Fig. 13) fully separates the first well region (71, Fig. 13) and the anode region (81, Fig. 13), because both the P+-type contact region 73 and the oxide film 78 fully separate the p-type base region 71 and p-type polysilicon layer 81 (Fig. 13), and
wherein the semiconductor substrate is at least one of a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate, and/or a gallium nitride substrate, because Applicants do not specifically claim that the recited “a silicon carbide substrate” is limited to a single, homogeneous, single-crystalline substrate, i.e. Applicants do not claim that the semiconductor substrate (essentially) consists of a single material composition, and as evidenced by Roedle et al., a composite substrate structure of an oxide layer 14 disposed on a SiC substrate 12 shown in Fig. 1 of Roedle et al. is referred to as “an oxidized SiC substrate” (see Abstract, [0009], [0064]), which is a kind of a SiC substrate; therefore, the composite substrate of the semiconductor base body 100 and oxide film 78 disclosed by Shiigi et al. can be referred to as a silicon carbide substrate or “an oxidized silicon carbide substrate”; also, the Examiner notes that a silicon substrate covered with a native oxide film is referred to as a silicon substrate in semiconductor industry and research, which is a common nomenclature, rather than a non-silicon substrate.
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Regarding claim 4, Shiigi et al. further disclose for the manufacturing method according to claim 1 that providing the first high concentration region (p+-type contact region 73, Fig. 13) includes implanting a dopant into the semiconductor substrate while masking the region where the anode region is provided, because “the n+-type source region 5 , the p+-type contact region 6, and the n-type JFET region 7 are next formed by repeatedly executing the process including photolithography and ion implantation as a combination, under different ion implantation conditions” (emphasis added, [0076]), which corresponds to the process of “implanting a dopant into the semiconductor substrate while masking the region where the anode region is provided” in the claimed invention.
Regarding claim 5, Shiigi et al. further disclose for a manufacturing method of a semiconductor device having a transistor portion (left-side portion having transistor, Fig. 13) and a diode portion (left-side portion having diode, Fig. 13) that
providing a first well region (71, Fig. 13) of a second conductivity type (p-type, Fig. 13) that forms part of an upper surface of a semiconductor substrate under the upper surface of the semiconductor substrate (under an upper surface of a composite substrate of 100/78, Fig. 13);
providing, in the diode portion (left-side portion having diode, Fig. 13), an anode region (81, Fig. 13) of a second conductivity type (p-type polysilicon, [0097]) that forms part of the upper surface of the semiconductor substrate under the upper surface of the semiconductor substrate (upper surface of 100/78, Fig. 13); and
providing a first high concentration region (73, Fig. 13) of a second conductivity type (p+-type, Fig. 13) having a higher doping concentration (“p+”, Fig. 13) than the anode region (“p”, [0097]), because it is known in the art that “p+” typically denotes a concentration higher than “p”, that forms part of the upper surface of the semiconductor substrate under the upper surface of the semiconductor substrate (upper surface side of 100/78, Fig. 13),
wherein the first high concentration region (73, Fig. 13) being in direct contact with the first well region (71, Fig. 13),
wherein the first high concentration region (73, Fig. 13) is between the anode region (81, Fig. 13) and the first well region (71, Fig. 13),
wherein the first high concentration region (73, Fig. 13) fully separates the first well region (71, Fig. 13) and the anode region (81, Fig. 13), because both the P+-type contact region 73 and the oxide film 78 fully separate the p-type base region 71 and p-type polysilicon layer 81 (Fig. 13), and
wherein the semiconductor substrate is at least one of a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate, and/or a gallium nitride substrate, because Applicants do not specifically claim that the recited “a silicon carbide substrate” is limited to a single, homogeneous, single-crystalline substrate, as evidenced by Roedle et al., a composite structure of an oxide layer 14 formed on a SiC substrate 12 (Fig. 1) is described as “an oxidized SiC substrate” (see Abstract, [0009], [0064]), therefore, the composite substrate of the semiconductor base body 100 and oxide film 78 by Shiigi et al. can reasonably be referred to as “an oxidized silicon carbide substrate”, see additional explanations of the term “silicon carbide substrate” in the prior art rejection of claim 1 above.
Regarding claim 8, Shiigi et al. further disclose for the manufacturing method according to claim 5 that providing the first high concentration region (p+-type contact region 73, Fig. 13) includes implanting a dopant into the semiconductor substrate while masking the region where the anode region is provided, because “the n+-type source region 5 , the p+-type contact region 6, and the n-type JFET region 7 are next formed by repeatedly executing the process including photolithography and ion implantation as a combination, under different ion implantation conditions” (emphasis added, [0076]), which corresponds to the process of “implanting a dopant into the semiconductor substrate while masking the region where the anode region is provided” in the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over by Shiigi et al. (US 2017/0111037), as evidenced by Roedle et al. (US 2010/0006860), in view of Hirabayashi et al. (US 2017/0069625).
Regarding claim 2, Shiigi et al. further disclose for the manufacturing method according to claim 1 that the first high concentration region (73, Fig. 13) is provided in a mesa portion of the semiconductor substrate, because P+-type contact region 73 by Shiigi et al. is formed in the upper surface of the substrate 100, which corresponds to the mesa portion in the claimed invention.
Shiigi et al. differ from the claimed invention by not showing that the first high concentration region is sandwiched between trench portions in the providing the first high concentration region.
However, Hirabayashi et al. disclose for a semiconductor device having IGBT and diode regions that in the diode region 40 (Fig. 1), the anode contact region 42a has a high concentration (“p+”, Fig. 1), formed in a mesa portion of the substrate 12, and sandwiched between trench portions (52/54, Fig. 1).
Since both Shiigi et al. and Hirabayashi et al. teach a semiconductor device having IGBT and diode regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor device of Shiigi et al. can be modified in that the first high concentration region is formed in a mesa portion of the semiconductor substrate and sandwiched between trenches, as disclosed by Hirabayashi et al., in order to precisely control the flow of electrons within the diode.
Regarding claim 3, Shiigi et al. further disclose for the manufacturing method according to claim 1 that
providing an interlayer dielectric film (oxide film 78, Fig. 13) above the upper surface of the semiconductor substrate (100, Fig. 13); and
providing an emitter electrode (anode pad 54 or cathode pad 55, Fig. 13) above the interlayer dielectric film (78, Fig. 13), wherein the interlayer dielectric film (78, Fig. 13) is provided with one or more contact holes to electrically connect the emitter electrode (54 or 55, Fig. 13) and the semiconductor substrate (100, Fig. 13), because there are contact holes between portions of the oxide film 78 above trenches on the oxide film 78 that allow electrical connection between the anode pad 54 or cathode pad 55, and the semiconductor substrate 100 (Fig. 13), and
Shiigi et al. differ from the claimed invention by not showing that no contact hole is provided on the upper surface of the semiconductor substrate at the first high concentration region to electrically connect the emitter electrode (54 or 55, Fig. 13) and the semiconductor substrate (100, Fig. 13), because there is no contact hole provided on the p+-type contact region 73, which corresponds to the first high concentration region in the claimed invention (Fig. 13).
However, Hirabayashi et al. further disclose that an upper surface of the semiconductor substrate 12 at both the IGBT region 20 and the diode region 40 does not include any holes for electrical contacts, as shown in the attached Fig. 1 below, and one of ordinary skill in the art would acknowledge that IGBT device structure can be designed without contact holes on an upper surface of the semiconductor substrate, as disclosed by Hirabayashi et al.
Since both Shiigi et al. and Hirabayashi et al. teach a semiconductor device having IGBT and diode regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor device of Shiigi et al. can be modified in that the device does not include any holes for electrical contacts, as disclosed by Hirabayashi et al., as a matter of design choice to improve electrical contact characteristics of the conductive electrodes.
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Regarding claim 6, Shiigi et al. further disclose for the manufacturing method according to claim 5 that the first high concentration region (73, Fig. 13) is provided in a mesa portion of the semiconductor substrate, because P+-type contact region 73 by Shiigi et al. is formed in the upper surface of the substrate 100, which corresponds to the mesa portion in the claimed invention.
Shiigi et al. differ from the claimed invention by not showing that the first high concentration region is sandwiched between trench portions in the providing the first high concentration region.
However, Hirabayashi et al. disclose for a semiconductor device having IGBT and diode regions that in the diode region 40 (Fig. 1), the anode contact region 42a has a high concentration (“p+”, Fig. 1), formed in a mesa portion of the substrate 12, and sandwiched between trench portions (52/54, Fig. 1).
Since both Shiigi et al. and Hirabayashi et al. teach a semiconductor device having IGBT and diode regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor device of Shiigi et al. can be modified in that the first high concentration region is formed in a mesa portion of the semiconductor substrate and sandwiched between trenches, as disclosed by Hirabayashi et al., in order to precisely control the flow of electrons within the diode.
Regarding claim 7, Shiigi et al. further disclose for the manufacturing method according to claim 5 that
providing an interlayer dielectric film (oxide film 78, Fig. 13) above the upper surface of the semiconductor substrate (100, Fig. 13); and
providing an emitter electrode (anode pad 54 or cathode pad 55, Fig. 13) above the interlayer dielectric film (78, Fig. 13), wherein the interlayer dielectric film (78, Fig. 13) is provided with one or more contact holes to electrically connect the emitter electrode (54 or 55, Fig. 13) and the semiconductor substrate (100, Fig. 13), because there are contact holes between portions of the oxide film 78 above trenches on the oxide film 78 that allow electrical connection between the anode pad 54 or cathode pad 55, and the semiconductor substrate 100 (Fig. 13), and
Shiigi et al. differ from the claimed invention by not showing that no contact hole is provided on the upper surface of the semiconductor substrate at the first high concentration region to electrically connect the emitter electrode (54 or 55, Fig. 13) and the semiconductor substrate (100, Fig. 13), because there is no contact hole provided on the p+-type contact region 73, which corresponds to the first high concentration region in the claimed invention (Fig. 13).
However, Hirabayashi et al. further disclose that an upper surface of the semiconductor substrate 12 at both the IGBT region 20 and the diode region 40 does not include any holes for electrical contacts, as shown in the attached Fig. 1 above, and one of ordinary skill in the art would acknowledge that IGBT device structure can be designed without contact holes on an upper surface of the semiconductor substrate, as disclosed by Hirabayashi et al.
Since both Shiigi et al. and Hirabayashi et al. teach a semiconductor device having IGBT and diode regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor device of Shiigi et al. can be modified in that the device does not include any holes for electrical contacts, as disclosed by Hirabayashi et al., as a matter of design choice to improve electrical contact characteristics of the conductive electrodes.
Response to Arguments
Applicant's arguments filed in September 29, 2025 have been fully considered but they are not persuasive, for the reasons discussed above, an alternative interpretation of Shiigi et al. different from the previous Office Action, in connection with the rejections of claims 1 and 5 above.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815