DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 23 January 2026 has been entered. Applicant’s amendments to the Specification and Drawings have overcome the specification and drawings objections. Applicant’s amendments to the claims have overcome the 35 USC 112(a), (b), and (d) rejections due to the claims no longer being interpreted under 35 USC 112(f). Note, upon further reconsideration the method claims 16-20 are no longer interpreted under the 35 USC 112(f) interpretation. See MPEP 2181(I)(A) see Masco Corp. v. United States, 303 F.3d 1316, 1327, 64 USPQ2d 1182, 1189 (Fed. Cir. 2002) ("[W]here a method claim does not contain the term ‘step[s] for,’ a limitation of that claim cannot be construed as a step-plus-function limitation without a showing that the limitation contains no act.").
Claim Construction
Regarding claim 1, the preamble is given patentable weight. Claim 1 contains the limitation "the pieces of input neuron data" in the body, which is referring to the limitations as recited in the preamble. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of a floating-point computation apparatus for performing a multiply-and-accumulate operation on the pieces of input neuron data. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight.
Regarding claim 16, the preamble is given patentable weight. Claim 16 contains the limitation "the pieces of input neuron data", "the exponent processing unit", and "the mantissa processing unit" in the body, which is referring to the limitations as recited in the preamble. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of a floating-point computation apparatus for performing a multiply-and-accumulate operation on the pieces of input neuron data. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 16 should be afforded patentable weight.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the deep neural network training process" in pg. 11 ln. 2-3, 5-6. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over J. Lee et al., "An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory," 2021 IEEE Hot Chips 33 Symposium (HCS), Palo Alto, CA, USA, 2021, pp. 1-20, doi: 10.1109/HCS52781.2021.9566881. (hereinafter “Lee”, as cited on the 892 filed 10/28/2025) in view of US 20210064986 A1 Xi et al. (hereinafter “Xi”, as cited on the 892 filed 10/28/2025).
Regarding claim 1, Lee discloses: A floating-point computation apparatus (Pg. 10, FP CIM) for performing a Multiply-and-Accumulation (MAC) operation (Pg. 1; Pg. 11, ECIM Architecture; Pg. 16, Mantissa-Free-Exponent-Calculation) on a plurality of pieces of input neuron data represented in a floating-point format, the floating-point computation apparatus comprising:
a data preprocessing processor configured to separate and extract an exponent and a mantissa from each of the pieces of input neuron data;
an exponent processor (Pg. 8, <Prop. FP Computing Arch.> Exponent-CIM, Exp. Operand) connected to the data preprocessing processor for data transfer, the exponent processor being configured to perform Computing-in-Memory (CIM) (Pg. 11-12, ECIM Architecture) on input neuron exponents, which are exponents separated and extracted from the pieces of input neuron data; and
a mantissa processor (Pg. 8, <Prop. FP Computing Arch.> Mantissa memory and Digital Mantissa Processing Engine, Man. Operand) connected to the data preprocessing processor and the exponent processor (Pg. 8, Exponent-CIM connected to Digital Mantissa Processing Engine) for the data transfer, the mantissa processor being configured to perform a high-speed computation (Pg. 8, @T=0~1; Pg. 19, Heterogenous FP computing arch. -> MAC cycle) on input neuron mantissas, which are mantissas separated and extracted from the pieces of input neuron data,
wherein the exponent processor determines a mantissa shift size for a mantissa computation and transfers the mantissa shift size to the mantissa processor (Pg. 8, <Prop. FP Computing Arch.> Exponent-CIM, Mantissa Shift Amount; Pg. 11, Mantissa Shift Size; Pg. 12, Mantissa Shift; Pg. 16, output of Exponent Subtractor to Mantissa Shifter), and
wherein the mantissa processor normalizes a result of the mantissa computation (Pg. 10, Mantissa PE line; Pg. 16, Mantissa shifter and adder) and thereafter transfers a normalization value generated as a result of normalization to the exponent processor (Pg. 8, <Prop. FP Computing Arch.> Mantissa memory and Digital Mantissa Processing Engine, Norm. Result; Pg. 16, Output from Norm. & Round block).
Lee is silent with disclosing:
on a plurality of pieces of input neuron data represented in a floating-point format,
a data preprocessing processor configured to separate and extract an exponent and a mantissa from each of the pieces of input neuron data;
connected to the data preprocessing processor for data transfer, on input neuron exponents, which are exponents separated and extracted from the pieces of input neuron data;
connected to the data preprocessing processor for the data transfer, on input neuron mantissas, which are mantissas separated and extracted from the pieces of input neuron data.
Xi discloses:
on a plurality of pieces of input neuron data represented in a floating-point format ([0026], [0028], [0038]);
a data preprocessing processor (Fig. 3, 108, [0037]) configured to separate and extract (Fig. 2, 204, [0042]; Fig. 3, 302, [0038]) an exponent (Fig. 3, 314, [0046]) and a mantissa (Fig. 3, 304, [0043]) from each of the pieces of input neuron data ([abstract]);
connected to the data preprocessing processor for data transfer (Fig. 3 “312, 112” [0055]), on input neuron exponents, which are exponents separated and extracted (Fig. 3, 314, [0046]) from the pieces of input neuron data ([abstract]);
connected to the data preprocessing processor for data transfer (Fig. 3 “312, 112” [0055]), on input neuron mantissas, which are mantissas separated and extracted Fig. 3, 304, [0043]) from the pieces of input neuron data ([abstract]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lee’s floating-point computation apparatus with Xi’s neuron data and the data preprocessing processor feature because they are in the claimed invention’s same field of endeavor of floating-point computation architecture ([abstract]). Although Lee generally discloses mantissa and exponent values, they are silent with explicitly describing them as related to neuron data. It would have been obvious to one of ordinary skill in the art to implement them as part of neuron data format as they are a well-known technique for data representation for artificial intelligence applications ([0001]), and doing so would have yielded predictable results when implemented. Further, it would have been obvious to one of ordinary skill in the art to implement a data preprocessing processor to extract these particular data segments as doing so allows greater configurability for manipulation and calculation by processing certain portions of the segments, rather than the entirety of the value at once ([0037]). Using the known data representation to provide a predictable outcome in Lee would have been obvious to one of ordinary skill in the art before the effective filing date, since one of ordinary skill in the art would recognize the potential benefits associated with this modification, such as widening the use of the invention to applications in artificial intelligence for model training purposes ([0003]) and/or incorporating a preprocessing processor to extract and separate data segments for more efficient processing ([0031]).
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the data preprocessing processor (see claim 1 mapping) is configured to, as Lee discloses:
generate at least one input neuron data pair by pairing two or more pieces of input neuron data that are sequentially input for a Multiply-and-Accumulate (MAC) operation (Pg. 16, FP OP. Pipeline FP Multiplier and Accum.) depending on a sequence of the input neuron data,
separate and extract an exponent and a mantissa (Pg. 8, Exp. Operand and Man. Operand) from each of arbitrary first and second input neuron data forming the input neuron data pair in each preset operation cycle, and
transfer first and second input neuron exponents (Pg. 16, Exp. A and Exp. B), which are the separated and extracted exponents, to the exponent processor (Pg. 8, <Prop. FP Computing Arch.> Exponent-CIM; Pg. 10, 1. Exponent-Computing-in-Memory (ECIM) -> exponent, including IEMEM, Weight-ECIM SRAM ARRAY, Output-ECIM SRAM ARRAY), and transfer first and second input neuron mantissas (Pg. 16, Man. A and Man. B), which are the separated and extracted mantissas, to the mantissa processor (Pg. 8, <Prop. FP Computing Arch.> Mantissa memory and Digital Mantissa Processing Engine; Pg. 10, 2. Mantissa-Free-Exponent-Calculation (MFEC) -> mantissa, including IMMEM, WMMEM, Mantissa PE Line, OMMEM).
Lee is silent with disclosing:
generate at least one input neuron data pair by pairing two or more pieces of input neuron data depending on a sequence of the input neuron data,
separate and extract from each of arbitrary first and second input neuron data forming the input neuron data pair in each preset operation cycle,
transfer neuron exponents which are the separated and extracted exponents, and
transfer neuron mantissas which are the separated and extracted mantissas.
Xi discloses:
generate at least one input neuron data pair by pairing two or more pieces of input neuron data depending on a sequence of the input neuron data ([0038]),
separate and extract from each of arbitrary first and second input neuron data forming the input neuron data pair (exponent: Fig. 3, 314, [0046]; mantissa: Fig. 3, 304, [0043]) in each preset operation cycle ([0067]),
transfer neuron exponents ([0049]) which are the separated and extracted exponents (Fig. 3, output of 314, [0049]), and
transfer neuron mantissas ([0038], [0047]) which are the separated and extracted mantissas (Fig. 3, output of 304, [0047]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 3, in addition to the teachings addressed in the claim 2 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the exponent processor (see claim 1 mapping) comprises, as Lee discloses:
an input neuron exponent memory (Pg. 10 IEMEM) configured to sequentially store pairs of the first and second input neuron exponents (Pg. 16, Exp. A, Exp. B; Pg. 8, Exp. Operand) that are transferred in each operation cycle;
an exponent computation memory (Pg. 10 Weight-ECIM, Pg. 11 ECIM architecture) configured to sequentially perform computing-in-memory on the first and second input neuron exponent pairs (Pg. 12 F. Map’s Exponent) such that the computing-in-memory is performed in a bitwise manner (Pg. 12 bitcells, Pg. 14 Operational waveforms) and results of the computing-in-memory are output (Pg. 12 outputs to Adder/Comparator, BLB and BL); and
an exponent peripheral circuit (Pg. 12 Shared Exp. Peripheral) configured to sequentially calculate sums of the first and second input neuron exponent pairs from the results of the computing-in-memory transferred from the exponent computation memory (Pg. 12 Exp. Add), sequentially compare the sums of the first and second input neuron exponent pairs with each other (Pg. 12 Exp Compare), determine a difference between the sums to be the mantissa shift size (Pg. 12 mantissa shift; Pg. 16 Exponent Subtractor), and update and store a maximum exponent value (Pg. 12 Final Exp., Pg. 16 Exponent Updater).
Lee is silent with disclosing:
neuron exponent memory configured to sequentially store pairs of the first and second input neuron exponents that are transferred in each operation cycle,
neuron exponents, and
neuron mantissas.
Xi discloses:
neuron exponent memory configured to sequentially store pairs (Fig. 3 “102” [0026]) of the first and second input neuron exponents ([0038]) that are transferred in each operation cycle ([0067]),
neuron exponents ([0049]), and
neuron mantissas ([0038], [0047]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 4, in addition to the teachings addressed in the claim 3 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the exponent processor (see claim 1 mapping) further comprises, as Lee discloses:
one or more exponent computation memories (Pg. 10-11 Weight-ECIM SRAM Array and Output-ECIM SRAM), and
the exponent peripheral circuit is shared by the one or more exponent computation memories (Pg. 10-12 Shared Exponent Peripheral Circuit).
Regarding claim 5, in addition to the teachings addressed in the claim 3 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the exponent computation memory (see claim 4 mapping) comprises, as Lee discloses:
a plurality of computing-in-memory local arrays (Pg. 12 CIM Local Array (CLA)) disposed in an a x b arrangement (Pg. 11 512x128b, 128x128b) and configured to perform local computing-in-memory (Pg. 11 Weight ECIM – inference, back-propagation, Output ECIM – weight-gradient);
an input/output interface configured to provide an interface for reading and writing data (Pg. 11 Normal I/O Interface) from and to each of the plurality of computing-in-memory local arrays (Pg. 11 CIM Local Array);
a global bitline (Pg. 12 Global BL) and a global bitline bar (Pg. 12 Global BLB) configured to form a path through which results of local computing-in-memory for the plurality of computing-in-memory local arrays are moved to the exponent peripheral circuit (Pg. 12 Exp. Add with BLB and BL as inputs); and
a wordline driver (Pg. 11 WL Driver) configured to generate a wordline driving signal to be transferred (Pg. 11
W
L
0
~
W
L
31
and
W
L
736
~
W
L
767
) to the computing-in-memory local arrays (Pg. 11 CIM Local Array).
Although Lee discloses these sub-features with respect to the weight ECIM, they do not explicitly disclose the output ECIM as necessarily containing the same sub-features. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the output ECIM to contain the same sub-features as those described in the weight ECIM, and yield predictable results, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 6, in addition to the teachings addressed in the claim 5 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein each of the computing-in-memory local arrays (see claim 5 mapping) comprises, as Lee discloses:
a local bitline (Pg. 12 Local BL) and a local bitline bar (Pg. 12 Local BLB) in which the first input neuron exponent (Pg. 16, Exp. A; Pg. 8, Exp. Operand) is precharged (Pg. 12 precharged from the Pre-charger);
a precharger configured to precharge the local bitline and the local bitline bar based on a bit value of the first input neuron exponent (Pg. 12
V
D
D
Pre-charger with input to F. Map’s Exponent);
a plurality of memory cells (Pg. 12 32 6T Bitcells) configured to store the second input neuron exponent (Pg. 16, Exp. B; Pg. 8, Exp. Operand) in a bitwise manner (Pg. 13 <In-memory Op. Truth Table> stored bit), perform computing-in-memory on the second input neuron exponent and the first input neuron exponent precharged in the local bitline (Pg. 13 <In-memory Op. Truth Table> LBL, Pre-charge F. Map ‘A’) and the local bitline bar (Pg. 13 <In-memory Op. Truth Table> LBLB, Pre-charge F. Map ‘IA’), and then determine bit values of the local bitline and the local bitline bar (Pg. 13 read cell w/ Lower
V
W
L
);
a first driver configured to drive the bit value of the local bitline to the global bitline (Pg. 13 DR connected to LBL) in response to a global bitline enable signal that is input from an outside (Pg. 13 DR connected to LBL with GBL_EN); and
a second driver configured to drive the bit value of the local bitline bar to the global bitline bar (Pg. 13 DR connected to LBLB) in response to the global bitline enable signal (Pg. 13 DR connected to LBLB with GBL_EN).
Lee is silent with disclosing: neuron exponents.
Xi discloses: neuron exponents ([0049]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 7, in addition to the teachings addressed in the claim 6 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein each of the memory cells (see claim 6 mapping) is configured to, as Lee discloses:
operate in any one of a read mode and a write mode in response to the wordline driving signal (Pg. 13
V
W
L
reading when lower voltage, writing when higher voltage),
in the write mode, store the second input neuron exponent transferred through the input/output interface in a bitwise manner (Pg. 13 <In-memory Op. Truth Table> stored bit, higher
V
W
L
, Pg. 14 higher WL0 and WL1),
in the read mode, perform computing-in-memory on the precharged first input neuron exponent and the second input neuron exponent (Pg. 13 pre-charge F. Map ‘A’ and ‘IA’), stored in a bitwise manner (Pg. 13 <In-memory Op. Truth Table> stored bit), and then determine the bit values of the local bitline and the local bitline bar (Pg. 13 read cell w/ Lower
V
W
L
, Pg. 14 lower WL0 and WL1), and
determine the bit value of the local bitline by performing an AND operation on the first input neuron exponent and the second input neuron exponent in a bitwise manner (Pg. 12 in-memory AND op. @ CLA, Pg. 13-14) and determine the bit value of the local bitline bar by performing a NOR operation on the first input neuron exponent and the second input neuron exponent in a bitwise manner (Pg. 12 in-memory NOR op. @ CLA, Pg. 13-14).
Lee is silent with disclosing: neuron exponents.
Xi discloses: neuron exponents ([0049]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 10, in addition to the teachings addressed in the claim 5 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the exponent peripheral circuit (see claim 3 mapping) comprises, as Lee discloses:
a plurality of exponent computation units connected in parallel to each other (Pg. 12 Exp. Adder and Exp. Comp. pairs),
each of the exponent computation units comprises:
an exponent adder (Pg. 12 Exp. Adder) configured to receive, as inputs, the results of computing-in-memory transferred through the global bitline and the global bitline bar (Pg. 12 Exp. Adder BLB and BL) and calculate sums of the first and second input neuron exponent pairs (Pg. 12 Exp. Adder
S
o
u
t
,
C
o
u
t
); and
an exponent comparator (Pg. 12 Exp. Comp.) configured to sequentially compare the sums of the first and second input neuron exponent pairs (Pg. 12 Exp Compare), received from the exponent adder in each operation cycle, with each other, determine a difference between the sums to be the mantissa shift size (Pg. 12 mantissa shift; Pg. 16 Exponent Subtractor), and update and store a maximum exponent value (Pg. 12 Final Exp., Pg. 16 Exponent Updater).
Lee is silent with disclosing: each operation cycle; neuron exponents.
Xi discloses: each operation cycle ([0067]); neuron exponents ([0049]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 11, in addition to the teachings addressed in the claim 10 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the exponent comparator (see claim 10 mapping) comprises, as Lee discloses:
a floating-point exception handler (Pg. 12 Exception) configured to receive the sums of the first and second input neuron exponent pairs from the exponent adder (Pg. 12 Exception receives
S
o
u
t
) and perform exception handling in floating-point multiplication (Pg. 12 output from Exception);
a first register (Pg. 12 Reg.) configured to store a maximum exponent value (Pg. 12 input to Reg.), which is a maximum value, among the sums of the first and second input neuron exponent pairs calculated during a period ranging to a previous operation cycle (Pg. 16 FP Add. cycles);
a subtractor (Pg. 12 subtraction unit (-)) configured to obtain a difference between a sum of the first and second input neuron exponent pairs output from the floating-point exception handler (Pg. 12 output from Exception), and the maximum value stored in the first register (Pg. 12 output of reg feedback to subtraction unit); and
a comparator (Pg. 12 >?) configured to update the maximum exponent value stored in the first register based on a result of subtraction by the subtractor (Pg. 12 feedback loop from Reg. to subtractor), determine the mantissa shift size (Pg. 12 mantissa shift), and transfer the mantissa shift size to the mantissa processor (Pg. 8 mantissa shift amount; Pg. 11 Mantissa shift size),
wherein the first register is configured to determine a final exponent value (Pg. 12 output of Reg.) by updating the maximum exponent value based on the normalization value transferred from the mantissa processor (Pg. 16 Norm & Round output to Exponent Updater).
Lee is silent with disclosing: neuron exponents.
Xi discloses: neuron exponents ([0049]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 12, in addition to the teachings addressed in the claim 2 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the mantissa processor (see claim 1 mapping) further comprises, as Lee discloses:
an input neuron mantissa memory (Pg. 10 IMMEM) configured to sequentially store pairs of the first and second input neuron mantissas that are transferred (Pg. 10 inputted to Mantissa PE line) in each operation cycle; and
a plurality of mantissa computation units connected in parallel to each other (Pg. 10 x16 MPE) and configured to sequentially calculate the first and second input neuron mantissa pairs (Pg. 16 Mantissa multiplier, shifter, adder), normalize a final computation result (Pg. 16 Norm. & Round), and transfer a normalization value (Pg. 16 Norm & Round output to Exponent Updater), generated as a result of the normalization, to the exponent processor (Pg. 8 Norm. Result), thus allowing the exponent processor to determine a final exponent value (Pg. 16 Exponent Updater receives Norm. Result).
Lee is silent with disclosing: each operation cycle; neuron mantissas.
Xi discloses: each operation cycle ([0067]); neuron mantissas ([0038], [0047]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 13, in addition to the teachings addressed in the claim 12 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the mantissa processor (see claim 1 mapping) further comprises, as Lee discloses:
a weight mantissa memory (Pg. 10 WMMEM) configured to separate and separately store only a weight mantissa part, which is a mantissa part of the weight generated in the deep neural network training process; and
an output neuron mantissa memory (Pg. 10 OMMEM) configured to separate and separately store only an output neuron mantissa part, which is a mantissa part of output neuron data generated in the deep neural network training process,
wherein each of the mantissa computation units (Pg. 10 x16 MPE) is configured to perform a high-speed computation (Pg. 17 MFEC) on mantissas transferred from at least one of the input neuron mantissa memory, the weight mantissa memory, and the output neuron mantissa memory (Pg. 10 Mantissa PE Line connected to IMMEM, WMMEM, and OMMEM).
Lee is silent with disclosing to separate and separately store only a weight mantissa part, which is a mantissa part of the weight generated in the deep neural network training process; and to separate and separately store only an output neuron mantissa part, which is a mantissa part of output neuron data generated in the deep neural network training process.
Xi discloses to separate and separately store only a weight mantissa part ([0039] mw, [0040-0041]), which is a mantissa part of the weight generated in the deep neural network training process ([abstract], [0037-0038]); and to separate and separately store only an output neuron mantissa part ([0039] w, [0040-0041]), which is a mantissa part of output neuron data generated in the deep neural network training process ([abstract], [0037-0038]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 14, in addition to the teachings addressed in the claim 12 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein the mantissa computation units (see claim 12 mapping) further comprises, as Lee discloses:
a multiplier configured to perform multiplication on the first and second input neuron mantissa pairs and store a result of the multiplication (Pg. 16, Mantissa Multiplier);
a shifter configured to perform shifting on the result of the multiplication based on the mantissa shift size (Pg. 16, Mantissa Shifter using Exponent Subtractor output as mantissa shift size);
a mantissa adder configured to perform addition on one or more shifted multiplication results (Pg. 16, Mantissa Adder);
a counter configured to count a mantissa overflow generated as a result of the addition (Pg. 16, Overflow “Ovf” Counter);
a second register configured to accumulate and store the result of the addition (Pg. 16, Accum Reg.); and
a normalization processor configured to normalize the result of the mantissa computation (Pg. 16, Norm. & Round).
Lee is silent with disclosing: neuron mantissas.
Xi discloses: neuron mantissas ([0038], [0047]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 15, in addition to the teachings addressed in the claim 14 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein, as Lee discloses:
the mantissa computation unit is configured to sequentially perform the mantissa computation on all of the first and second input neuron mantissa pairs stored in the input neuron mantissa memory (see claims 13-14 mapping),
the counter (Pg. 16, Overflow “Ovf” Counter) and the second register (Pg. 16, Accum Reg.) are configured to transfer a mantissa overflow and an accumulated and stored value of the addition result that are generated in an intermediate operation stage to the shifter so as to perform an operation in a subsequent stage (Pg. 16, Accum Reg. feedback to Mantissa Shifter), and to transfer the mantissa overflow and the addition result that are generated during a mantissa computation in a final stage to the normalization processor (Pg. 16 outputs from Ovf Counter and Accum Reg. are input to Norm. & Round), and
the normalization processor is configured to perform normalization only on the mantissa overflow and the addition result that are generated during the mantissa computation in the final stage (Pg. 16, Normalize once after accum. Finished, FP Norm.).
Lee is silent with disclosing: neuron mantissas.
Xi discloses: neuron mantissas ([0038], [0047]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 16, Lee discloses:
A floating-point computation method for performing a multiply-and- accumulation operation (Pg. 1; Pg. 11, ECIM Architecture; Pg. 16, Mantissa-Free-Exponent-Calculation) on a plurality of pieces of input neuron data represented in a floating-point format using a floating-point computation apparatus (Pg. 10, FP CIM) that includes an exponent processing unit for an exponent computation in the floating-point format (Pg. 8, <Prop. FP Computing Arch.> Exponent-CIM; Pg. 10, 1. Exponent-Computing-in-Memory (ECIM) -> exponent, including IEMEM, Weight-ECIM SRAM ARRAY, Output-ECIM SRAM ARRAY) and a mantissa processing unit for a mantissa computation in the floating point format (Pg. 8, <Prop. FP Computing Arch.> Mantissa memory and Digital Mantissa Processing Engine; Pg. 10, 2. Mantissa-Free-Exponent-Calculation (MFEC) -> mantissa, including IMMEM, WMMEM, Mantissa PE Line, OMMEM), the floating-point computation method comprising:
a data preprocessing operation of separating and extracting an exponent and a mantissa from each of the pieces of input neuron data;
an exponent computation operation of performing, by the exponent processing unit, computing-in-memory (CIM) (Pg. 8, <Prop. FP Computing Arch.> Exponent-CIM, Exp. Operand) on input neuron exponents, which are exponents separated and extracted in the data preprocessing operation; and
a mantissa computation operation of performing, by the mantissa processing unit (Pg. 8, <Prop. FP Computing Arch.> Mantissa memory and Digital Mantissa Processing Engine, Man. Operand), a high-speed computation (Pg. 8, @T=0~1; Pg. 19, Heterogenous FP computing arch. -> MAC cycle) on input neuron mantissas, which are mantissas separated and extracted in the data preprocessing operation,
wherein the exponent computation operation comprises determining a mantissa shift size for the mantissa computation and transferring the mantissa shift size to the mantissa processing unit (Pg. 8, <Prop. FP Computing Arch.> Exponent-CIM, Mantissa Shift Amount; Pg. 11, Mantissa Shift Size; Pg. 12, Mantissa Shift; Pg. 16, output of Exponent Subtractor to Mantissa Shifter), and
wherein the mantissa computation operation comprises normalizing a result of the mantissa computation (Pg. 10, Mantissa PE line; Pg. 16, Mantissa shifter and adder) and thereafter transferring a normalization value generated as a result of normalization to the exponent processing unit (Pg. 8, <Prop. FP Computing Arch.> Mantissa memory and Digital Mantissa Processing Engine, Norm. Result; Pg. 16, Output from Norm. & Round block).
Lee is silent with disclosing:
on a plurality of pieces of input neuron data represented in a floating-point format,
a data preprocessing operation of separating and extracting an exponent and a mantissa from each of the pieces of input neuron data;
on input neuron exponents, which are exponents separated and extracted in the data preprocessing operation;
on input neuron mantissas, which are mantissas separated and extracted in the data preprocessing operation.
Xi discloses:
on a plurality of pieces of input neuron data represented in a floating-point format ([0026], [0028], [0038]);
a data preprocessing operation (Fig. 3, 108, [0037]) of separating and extracting (Fig. 2, 204, [0042]; Fig. 3, 302, [0038]) an exponent (Fig. 3, 314, [0046]) and a mantissa (Fig. 3, 304, [0043]) from each of the pieces of input neuron data ([abstract]);
on input neuron exponents, which are exponents separated and extracted in the data preprocessing operation (Fig. 3, 314, [0046]);
on input neuron mantissas, which are mantissas separated and extracted in the data preprocessing operation (Fig. 3, 304, [0043]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 17, in addition to the teachings addressed in the claim 16 analysis of which the rejection is incorporated, Lee in view of Xi discloses the method, wherein the data preprocessing operation (see claim 16 mapping) comprises, as Lee discloses:
a data pair generation operation of generating at least one input neuron data pair by pairing two or more pieces of input neuron data that are sequentially received for a Multiply-and-Accumulate (MAC) operation (Pg. 16, FP OP. Pipeline FP Multiplier and Accum.);
an exponent/mantissa separation extraction operation of separating and extracting an exponent and a mantissa (Pg. 8, Exp. Operand and Man. Operand) from each of arbitrary first and second input neuron data forming the input neuron data pair in each preset operation cycle; and
a data transfer operation of transferring first and second input neuron exponents (Pg. 16, Exp. A and Exp. B), which are the separated and extracted exponents to the exponent processing unit (Pg. 8, <Prop. FP Computing Arch.> Exponent-CIM; Pg. 10, 1. Exponent-Computing-in-Memory (ECIM) -> exponent, including IEMEM, Weight-ECIM SRAM ARRAY, Output-ECIM SRAM ARRAY), and transferring first and second input neuron mantissas (Pg. 16, Man. A and Man. B), which are the separated and extracted mantissas, to the mantissa processing unit (Pg. 8, <Prop. FP Computing Arch.> Mantissa memory and Digital Mantissa Processing Engine; Pg. 10, 2. Mantissa-Free-Exponent-Calculation (MFEC) -> mantissa, including IMMEM, WMMEM, Mantissa PE Line, OMMEM).
Lee is silent with disclosing:
a data pair generation operation of generating at least one input neuron data pair by pairing two or more pieces of input neuron data;
an exponent/mantissa separation extraction operation of separating and extracting from each of arbitrary first and second input neuron data forming the input neuron data pair in each preset operation cycle; and
a data transfer operation of transferring first and second input neuron exponents which are the separated and extracted exponents, and
transferring first and second input neuron mantissas which are separated and extracted mantissa.
Xi discloses:
a data pair generation operation of generating at least one input neuron data pair by pairing two or more pieces of input neuron data ([0038]);
an exponent/mantissa separation extraction operation of separating and extracting from each of arbitrary first and second input neuron data forming the input neuron data pair (exponent: Fig. 3, 314, [0046]; mantissa: Fig. 3, 304, [0043]) in each preset operation cycle ([0067]); and
a data transfer operation of transferring ([0049]) first and second input neuron ([0038]) exponents which are the separated and extracted exponents (Fig. 3, output of 314, [0049]), and
transferring ([0047]) first and second input neuron ([0038]) mantissas which are separated and extracted mantissa (Fig. 3, output of 304, [0047]).
The motivation to combine provided with respect to claim 16 equally applies.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Xi as applied to claim 1 above, and further in view of US 20220101914 A1 Dreesen et al. (hereinafter “Dreesen”).
Regarding claim 8, in addition to the teachings addressed in the claim 7 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein, as Lee discloses:
the exponent computation memory further comprises a decoder (Pg. 11 CLA Decoder) configured to analyze the first and second input neuron exponents that are targets of computing-in-memory (Pg. 10 Decoder receives inputs from IEMEM) and to control an operation to be performed by selecting a bitline in which the first input neuron exponent is to be charged and a memory cell (Pg. 12 Bitcell 31) in which the second input neuron exponent is to be stored (Pg. 11 selecting bitlines via the WL signals, Pg. 13 WL intersection with LBLB and LBL ), and
the decoder generates the global bitline enable signal (Pg. 13 DR connected to LBLB with GBL_EN).
Although Lee discloses these sub-features with respect to the weight ECIM, they do not explicitly disclose the output ECIM as necessarily containing the same sub-features. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the output ECIM to contain the same sub-features as those described in the weight ECIM, and yield predictable results, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Lee appears to be silent with disclosing neuron exponents and the decoder generating the enable signal.
Xi discloses:
neuron exponents ([0049]).
The motivation to combine provided with respect to claim 1 similarly applies.
Lee in view of Xi are silent with disclosing the decoder generating the enable signal.
Dreesen discloses the decoder generating ([0033], [0062]) the enable signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lee in view of Xi’s modified floating-point computation apparatus with Dreesen’s decoder generating enable signals feature because they are in the claimed invention’s same field of endeavor of computing-in-memory architecture ([abstract]). Although Lee generally discloses the enable signal, they are silent with explicitly describing them as being generated from the decoder. It would have been obvious to one of ordinary skill in the art to configure Lee’s decoder, as decoders generating useable signals are a well-known technique ([0033]), and doing so would have yielded predictable results when implemented. Further, it would have been obvious to one of ordinary skill in the art to implement decoders as generating enable signals as doing so allows greater data selection for manipulation, processing, and calculation ([0062]). Using the known concept of decoders generating useable signals to provide a predictable outcome in Lee in view of Xi would have been obvious to one of ordinary skill in the art before the effective filing date, since one of ordinary skill in the art would recognize the potential benefits associated with this modification, such as configuring Lee’s decoder to generate a selection signal based on its operands to better select operands for manipulation, processing, and calculation ([0062]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Xi as applied to claim 1 above, and further in view of J. Lee et al., "A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory," 2021 Symposium on VLSI Circuits, Kyoto, Japan, 2021, pp. 1-2, doi: 10.23919/ VLSICircuits52068.2021.9492476. (hereinafter “Lee’13.7”, as cited on the 892 filed 10/28/2025).
Regarding claim 9, in addition to the teachings addressed in the claim 6 analysis of which the rejection is incorporated, Lee in view of Xi discloses the floating-point computation apparatus, wherein each of the plurality of computing-in-memory local arrays is configured to sequentially perform (see claim 5 mapping), as Lee discloses:
a precharge process using the precharger (Pg. 14 LBL/LBLB of CLA0 and LBL/LBLB of CLA1),
a computing-in-memory process on each of the plurality of memory cells (Pg. 14 WL0 and WL1), and
a driving process using each of the first and second drivers (Pg. 14 GLB EN0 and GBL EN1),
wherein the processes are pipelined to overlap each other between adjacent computing-in-memory local arrays (Pg. 14 example of CLA0 and CLA1) in such a way that a precharge process using an arbitrary n-th computing-in-memory local array (Pg. 14 CLA0), a computing-in-memory process using an (n+ 1)-th computing-in-memory local array (Pg. 14 CLA1), and a driving process using an (n+2)-th computing-in-memory local array (Pg. 15 CLA2) are pipelined to overlap each other.
Although Lee generally discloses the precharge, computing-in-memory, and driving process and generally pipelining the processes to overlap each other, they appear to be silent to disclosing the operational waveforms for CLA2 for the entirety of the pipelined overlapping.
Lee and Lee in view of Xi are silent with disclosing the operational waveforms for CLA2 for the entirety of the pipelined overlapping.
However, Lee’13.7 discloses the processes pipelined to overlap each other using three instances of the computing-in-memory local arrays (Fig. 4(c), Pg. 1 Co. 2 ⁋ 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lee in view of Xi’s modified floating-point computation apparatus with Lee’13.7’s third local array operational waveforms feature because they are in the claimed invention’s same field of endeavor of computing-in-memory architecture ([abstract]). Although Lee generally discloses the operational waveforms for two computing-in-memory local arrays, they are silent with explicitly describing the operational waveforms for the third computing-in-memory local array, or the (n+2)-th. It would have been obvious to one of ordinary skill in the art to receive the operational waveforms of the third computing-in-memory local array as doing so would have yielded predictable results when implemented given that the operational waveforms of the first two arrays are described in Lee (Lee, Pg. 14 example of CLA0 and CLA1). Further, it would have been obvious to one of ordinary skill in the art to receive the operational waveforms corresponding to the third computing-in-local array as doing so provides greater visualization of the operation of more arrays in the invention, thus providing more information on how the invention is operating and where the voltage is flowing, which can provide greater insights into performance metrics (Lee’13.7, Fig. 4(c) and 4(d)). Using the known concept of analyzing operational waveforms to provide a predictable outcome in Lee in view of Xi would have been obvious to one of ordinary skill in the art before the effective filing date, since one of ordinary skill in the art would recognize the potential benefits associated with this modification, such as assessing the performance of Lee’s computing-in-memory local arrays and provide greater insights for designers (Lee’13.7, Pg. 1 Co. 2 ⁋ 4 ).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Xi as applied to claim 16 above, and further in view of Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2013. (hereinafter “Patterson”).
Regarding claim 18, in addition to the teachings addressed in the claim 17 analysis of which the rejection is incorporated, and Lee discloses the method, wherein the exponent computation operation (see claim 16 mapping) comprises:
a computing-in-memory operation (Pg. 11, 512x128 Weight ECIM; Pg. 12, CIM Local Array) of sequentially calculating pairs of the first and second input neuron exponents (Pg. 16, Exp. A, Exp. B; Pg. 8, Exp. Operand) transferred in each operation cycle (Pg. 14, Operational Waveforms, LBL/LBLB found in row “CLA0” and LBL/LBLB found in row “CLA1”) such that computing-in-memory is performed in a bitwise manner (Pg. 13, <In-Memory op. Truth Table>; Pg. 14, ECIM Status) and sums of the first and second input neuron exponent pairs are calculated (Pg. 12, Exp. Adder output; Pg. 16, Exponent Adder output);
a mantissa shift size determination operation of sequentially comparing the sums of the first and second input neuron exponent pairs that are sequentially calculated in the computing-in-memory operation with each other (Pg. 12,
S
o
u
t
inputted in to Exception unit that is included in the Exp Compare), determining a difference between the sums (Pg. 12, two inputs into “
-
“ unit) to be the mantissa shift size (Pg. 12, mantissa shift output from “
-
“ unit; Pg. 16, Exponent Subtractor output), and transferring the mantissa shift size to the mantissa processing unit (Pg. 16, Exponent Subtractor output to Mantissa Shifter; Pg. 8, Mantissa Shift Amount to Digital Mantissa Processing Engine);
a maximum exponent value determination operation of determining a larger one of the sums of the first and second input neuron exponent pairs generated as a result of the sequential comparison to be a maximum exponent value (Pg. 12, output of “>?” unit included in the Exp Compare);
a repetition operation of repeatedly performing the operation of performing the computing-in-memory operation, the mantissa shift size determination operation, and the maximum exponent value determination operation (see claim 18 mapping above) until a normalization value is transferred from the mantissa processing unit (Pg. 16, Accum. Reg. Feedback loop to reperform Mantissa Shifting and Adding); and
a final exponent determination operation of, when the normalization value is transferred from the mantissa processing unit (Pg. 16, output of Norm. & Round sent to Exponent Updater), determining a final exponent value by updating the maximum exponent value based on the normalization value (Pg. 16, Exponent Updater).
Lee is silent with disclosing:
first and second input neuron exponents;
a repetition operation of repeatedly performing.
Xi discloses: first and second input neuron ([0038]) exponents.
The motivation to combine provided with respect to claim 16 equally applies.
Xi and the combination of Lee in view of Xi are silent with disclosing a repetition operation of repeatedly performing.
Patterson discloses a repetition operation of repeatedly performing (Pg. 92, while loop; Pg. 93, Para. 1, for loop).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lee in view of Xi’s modified floating-point computation apparatus with Patterson’s repetition feature because they are in the claimed invention’s same field of endeavor of computer-based calculations (Pg. 92, Loops). Although Lee generally discloses performing computing-in-memory operations, they are silent with explicitly describing them as being repeatedly performed. It would have been obvious to one of ordinary skill in the art to configure Lee’s operations to repeat as repeatedly performing operations are a well-known technique (Pg. 92-93), and doing so would have yielded predictable results when implemented. Further, it would have been obvious to one of ordinary skill in the art to implement repeatedly performing operations as doing so assists designers with configuring the memory systems to better fit the invention (Pg. 375 ⁋ 1). Using the known concept of repeated operations to provide a predictable outcome in Lee in view of Xi would have been obvious to one of ordinary skill in the art before the effective filing date, since one of ordinary skill in the art would recognize the potential benefits associated with this modification, such as configuring Lee in view of Xi’s with better suited memory based on what blocks of operations would be repeated and which would not be (Pg. 375 ⁋ 2-3).
Regarding claim 19, in addition to the teachings addressed in the claim 18 analysis of which the rejection is incorporated, and Lee in view of Xi discloses the method, wherein the mantissa computation operation (see claim 16 mapping) comprises, as Lee discloses:
a multiplication operation of sequentially calculating pairs of the first and second input neuron mantissas generated in each operation cycle such that multiplication on the first and second input neuron mantissa pairs is calculated (Pg. 16, Mantissa Multiplier);
a shift operation of performing shifting on a result of the multiplication based on the mantissa shift size (Pg. 16, Mantissa Shifter using Exponent Subtractor output as mantissa shift size);
an addition operation of performing addition on one or more shifted multiplication results (Pg. 16, Mantissa Adder);
a count operation of counting a mantissa overflow generated as a result of the addition (Pg. 16, Overflow “Ovf” Counter);
an accumulation operation of accumulating and storing the result of the addition (Pg. 16, Accum Reg.); and
a normalization operation of normalizing a result of the mantissa computation (Pg. 16, Norm. & Round), and
wherein the mantissa computation is sequentially performed on all of the first and second input neuron mantissa pairs (Pg. 16, Man. A and Man. B) that are transferred in the data transfer operation.
Lee is silent with disclosing: first and second input neuron mantissas that are transferred in the data transfer operation.
Xi discloses: first and second input neuron ([0038]) mantissas that are transferred in the data transfer operation ([0047]).
The motivation to combine provided with respect to claim 16 equally applies.
Regarding claim 20, in addition to the teachings addressed in the claim 19 analysis of which the rejection is incorporated, and Lee in view of Xi discloses the method, wherein, Lee discloses:
each of the multiplication operation, the shift operation, the addition operation, the count operation, and the accumulation operation is repeated until the mantissa computation is sequentially performed on all of the first and second input neuron mantissa pairs (see claim 19 mapping) that are transferred in the data transfer operation,
the shift operation comprises performing preliminary normalization (Pg. 16, Normalize every MAC -> overflow counter + accumulation register) on the result of the multiplication (Pg. 16, Mantissa Multiplier output) based on a mantissa overflow (Pg. 16, Reg. output) and an accumulated and stored value for the result of the addition that are generated in an intermediate operation stage (Pg. 16, Accum Reg. feedback to Mantissa Shifter), and
the normalization operation is performed during a mantissa computation in a final stage, among mantissa computations on all of the first and second input neuron mantissa pairs that are transferred in the data transfer operation, and is performed to transfer a normalization value generated as a result of the normalization, to the exponent processing unit (Pg. 16, Norm. & Round output sent to Exponent Updater in Exponent side).
Lee is silent with disclosing: is repeated; all of the first and second input neuron mantissa pairs that are transferred in the data transfer operation.
Xi discloses: all of the first and second input neuron ([0038]) mantissa pairs that are transferred in the data transfer operation ([0047]).
The motivation to combine provided with respect to claim 16 equally applies.
Xi and the combination of Lee in view of Xi are silent with disclosing a repetition operation of repeatedly performing.
Patterson discloses repeatedly performing (Pg. 92, while loop; Pg. 93, Para. 1, for loop).
The motivation to combine provided with respect to claim 18 equally applies.
Response to Arguments
Specification. The specification objections have been withdrawn based upon the amendment to the specification.
Drawings. The drawings objections have been withdrawn based upon the amendment to the drawings.
35 USC 112(f). The claims are no longer interpreted under the previous 35 USC 112(f) invocation and are instead interpreted under the BRI of the plain meaning. Note, upon further reconsideration the method claims 16-20 are no longer interpreted under the 35 USC 112(f) interpretation. See MPEP 2181(I)(A) see Masco Corp. v. United States, 303 F.3d 1316, 1327, 64 USPQ2d 1182, 1189 (Fed. Cir. 2002) ("[W]here a method claim does not contain the term ‘step[s] for,’ a limitation of that claim cannot be construed as a step-plus-function limitation without a showing that the limitation contains no act.").
35 USC 112(a). The 112(a) rejections are withdrawn based upon the amendment to the claims.
35 USC 112(b). The 112(b) rejections are withdrawn based upon the amendment to the claims.
35 USC 112(d). The 112(d) rejections are withdrawn based upon the amendment to the claims.
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151