DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/03/2026 has been entered.
Response to Arguments
Applicant's arguments filed 06/03/2026 have been fully considered but they are not persuasive. Regarding Claims 1 and 11, Applicant argues that prior art of record Aleksov et al. (US 2022/0093517 A1) and Brun et al. (US 2023/0197664 A1) “lack the claimed integrated architecture where specific structures (a thermally conductive coating/film or metal vapor chamber) act as the heat spreader plane directly with the buffer die”. Examiner respectfully disagrees. As shown in the 35 USC § 103 rejections below, Aleksov et al. (US 2022/0093517 A1) and Brun et al. (US 2023/0197664 A1) do meet all recited limitations of the claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 1 and 11, it is unclear how to interpret the recited limitation “a heat spreader plane deposited on ..”. The term “deposited on” implies a process step and it is unclear why the Examiner should be concerned with how the heat spreader plane is formed as that does not appear to impact any structure characteristics in the claim. For purposes of examination, Examiner interprets the limitation “deposited on” as “on” and that a plurality of elements could then be between the heat spreader plane and the silicon buffer die.
Regarding Claims 1 and 11 it is unclear who to interpret “a heat spreader plane deposited on…” along with “the heat spreader plane being…a metal vapor chamber”. It is unclear how a metal vapor chamber can be deposited. For purposes of examination, Examiner interprets the limitation “a heat spreader plane deposited on…” along with “the heat spreader plane being…a metal vapor chamber” as “a heat spreader plane on…” and “the heat spreader plane being…a metal vapor chamber”.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov et al. (US 2022/0093517 A1, hereinafter Aleksov ‘517) in view of Brun et al. (US 2023/0197664 A1, hereinafter Brun ‘664), in view of the following arguments.
With respect to Claim 1 Aleksov ‘517 discloses an apparatus (100, Figs 1 and 37-44) comprising:
an interposer (150, Fig 37, Para [0077]) comprising one or more area array interconnections (connections for 102-1, connections for 102-2 and connections for 102-3 as shown in Fig 37), the one or more area array interconnections (connections for 102-1, connections for 102-2 and connections for 102-3 as shown in Fig 37) including a first type of area array interconnection (130, connections for 102-1 (DB contacts 110) shown in Fig 37 are disclosed as direct bond, Para [0078]) and a second type of area array interconnection (120, connections for 102-2 (solder contacts 140 and solder 120) shown in Fig 37 are disclosed as solder bond in Para [0078]);
a first die (102-1, Fig 37, Para [0078]) coupled to the interposer (150) via the first type of area array interconnection (130); and
a second die (102-2, Fig 37, Para 0078]) coupled to the interposer (150) via the second type of area array interconnection (120),
a heat spreader plane (152, Fig 1, Para [0024]), wherein the heat spreader plane (152) is configured to distribute heat within the heat spreader plane (Para [0040] disclose heat spreader plane dissipates heat from die)
wherein the first type of area array interconnection (130) is different from the second type of area array interconnection (120)(130 is direct bond and 120 is solder bond as disclosed in Para [0078]);
wherein the interposer (150) comprises the first type of area array interconnection (direct bonding 130, Fig 37, Para [0078]) comprising direct copper-to-copper bonding (the connections for 102-1 in area array 130 are direct bond contacts 110 as shown in Fig 37 and are disclosed as direct bond in Para [0078]) and the second type of area array interconnection (solder bonding 120/140, Fig 37, Para [0078]) comprising a plurality of solder bumps (120, connections for 102-2 are solder contacts 140 and solder 120 as shown in Fig 37 and are disclosed as a plurality of solder bonds in Para [0078]).
But Aleksov ‘517 fails to explicitly disclose a silicon buffer die coupled to a first surface of a first top side of the first die and a first surface of a second side of the second die, the silicon buffer die being positioned above the first die and the second die, wherein the silicon buffer die comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate, a heat spreader plane deposited on the silicon buffer die, the silicon buffer die being positioned between the heat spread plane and the first die, the heat spreader plane being a thermally conductive coating/film or a metal vapor chamber, the silicon buffer die acting as a transition layer to thermally couple the first die and the second die to the heat spreader plane.
Nevertheless, in a related endeavor (Fig 3A-3B of Brun ‘664), Brun ‘664 teaches a silicon buffer die (345a/345b, Fig 3B of Brun ‘664, Para [0064] discloses 345a/345b as passive heat spreader interposer of silicon) coupled to a first surface (top of 310a as shown in Fig 3B of Brun ‘664) of a first top side (topside of leftmost 310a as shown in Fig 3B of Brun ‘664) of the first die (310a, Fig 3B of Brun ‘664, Para [0053]) and a first surface (top of 310b as shown in Fig 3B of Brun ‘664) of a second side (topside of leftmost 310b as shown in Fig 3B of Brun ‘664) of the second die (310b, Fig 3B of Brun ‘664, Para [0053]), the silicon buffer die (345a/345b) being positioned above (disclosed in Fig 3B of Brun ‘664) the first die (310a) and the second die (310b)(Fig 3B of Brun ‘664 discloses 345a/345b above 310a and 310b), wherein the silicon buffer die (345a/345b) comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate (Para [0064] of Brun ‘664 discloses 345a/345b comprises silicon), a heat spreader plane (340, Fig 3B of Brun ‘664, Para [0053]) deposited on (Note examiner’s above interpretation of “deposited on” as “on”)(340 on 345a/345b disclosed in Fig 3B and Para [0053] of Brun ‘664) the silicon buffer die (345a/345b), the silicon buffer die (345a/345b) being positioned between the heat spread plane (340) and the first die (310a)(Fig 3B of Brun ‘664 discloses 345a/345b between heat spreader 320 and first die 310a), the heat spreader plane (340) being a thermally conductive coating/film (340, Fig 3B, Para [0053]) or a metal vapor chamber, the silicon buffer die (345a/345b) acting as a transition layer to thermally couple the first die (310a) and the second die (310b) to the heat spreader plane (340)(Examiner Note: “acting as a transition layer to thermally couple” is a functional property of the silicon buffer die. That being said, Para [0053] of Brun ‘664 discloses 345a/345b as a heat spreader between die and layer 340).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Brun ‘664’s teaching of a silicon buffer die coupled to a first surface of a first top side of the first die and a first surface of a second side of the second die, the silicon buffer die being positioned above the first die and the second die, wherein the silicon buffer die comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate, a heat spreader plane deposited on the silicon buffer die, the silicon buffer die being positioned between the heat spread plane and the first die, the heat spreader plane being a thermally conductive coating/film or a metal vapor chamber, the silicon buffer die acting as a transition layer to thermally couple the first die and the second die to the heat spreader plane into Aleksov ‘517’s device. Aleksov ‘517 discloses a package on package structure and Aleksov ‘517 discloses the use of a thermal interface material (TIM) to remove heat from the structure and discloses that the TIM can be many different materials. Brun ‘664 also teaches a package on package structure and teaches means to remove heat from the device through the use of a silicon interposer between the die and the heat spreader plane. The ordinary artisan would then have a reasonable expectation of success in substituting the heat spreader design of Brun ‘664 for the TIM structure of Aleksov ‘517. Further, the ordinary artisan would have been motivated to modify Aleksov ‘517 in the manner set forth above, at least, because, as Brun ‘664 teaches in Para [0026] the use of the buffer die (silicon interposer 345a/345b of Brun ‘664) can compensate for thickness mismatch between the die to the heat spreader and helps to conduct heat from the die to the heat spreader.
As incorporated, the silicon buffer die (345a/345b) and the heat spreader plane (340) of Brun ‘664 would be used between the first (102-1) and second (102-2) dies and heat spreader plane (340) would be incorporated as the heat plane of Aleksov ‘517 so that 345a/345b is between the first and second die and the heat plane.
With respect to Claim 2 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the apparatus of claim 1, and Aleksov ‘517 further discloses wherein the interposer (150) comprises an organic interposer (Para [0077] discloses 150 as an organic interposer).
With respect to Claim 3 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the apparatus of claim 1, and Aleksov ‘517 further discloses wherein the first type of area array interconnection (130) is one of:
a solder bonded interconnection; or
a copper bonded interconnection (Para [0026] discloses direct bonding region 130 having copper bonded interconnections).
With respect to Claim 5 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the apparatus of claim 3, and Aleksov ‘517 further discloses wherein the copper bonded interconnection (130) includes one of direct copper bonding or hybrid copper bonding (Para [0026] discloses direct bonding region 130 as direct copper bonding between connections 110 and 108) of the first die (102-1) to the interposer (150).
With respect to Claim 6 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the apparatus of claim 3, and Aleksov ‘517 further discloses wherein the second type of area array interconnection (120) is one of solder bonded (120 is solder bond as disclosed in Para [0078]) or copper bonded, and different from the first type of area array (130) (130 is direct bond and 120 is solder bond as disclosed in Para [0078]).
With respect to Claim 11 Aleksov ‘517 discloses a semiconductor device (100, Figs 1 and 37-44 and 49) comprising:
a circuit board (182, Fig 41, Para [0037]) comprising one or more internal layers (Para [0037] discloses 182 includes conductive pathways);
a first semiconductor package (100, Fig 41, Para [0083]) coupled to the circuit board (182), the first semiconductor package (100) including:
substrate (Para [0037 discloses additional components, “the support component 182 may include another IC package, an interposer, or any other suitable component” coupled to 182) coupled to the circuit board (182)
an interposer (150, Fig 49, Para [0077]) coupled to the circuit board (182), the interposer (150) comprising one or more area array interconnections (connections for 102-1, connections for 102-2 and connections for 102-3 as shown in Fig 49, Para [0083]), the one or more area array interconnections (connections for 102-1, connections for 102-2 and connections for 102-3) including a first type of area array interconnection (130, connections for 102-1 (DB contacts 110) shown in Fig 37 are disclosed as direct bond, Para [0078]), and a second type of area array interconnection (120, connections for 102-2 (solder contacts 140 and solder 120) shown in Fig 37 are disclosed as solder bond in Para [0078]);
a first die (102-1, Fig 37, Para [0078]) coupled to the interposer (150) via the first type of area array interconnection (130 disclosed in Para [0078] as direct bonded); and
a second die (102-2, Fig 37, Para 0078]) coupled to the interposer (150) via the second type of area array interconnection (120, connections for 102-2 (solder contacts 140 and solder 120) shown in Fig 37 are disclosed as solder bond in Para [0078]),
a heat spreader plane (152, Fig 1, Para [0024]), wherein the heat spreader plane (152) is configured to distribute heat within the heat spreader plane (Para [0040] disclose heat spreader plane dissipates heat from die)
wherein the first type of area array interconnection (130) is different from the second type of area array interconnection (120)(direct bonding, 130, is different than solder bond 120);
wherein the interposer (150) comprises the first type of area array interconnection (direct bonding 130, Fig 37, Para [0078]) comprising direct copper-to-copper bonding (the connections for 102-1 in area array 130 are direct bond contacts 110 as shown in Fig 37 and are disclosed as direct bond in Para [0078]) and the second type of area array (120) interconnection (solder bonding 120/140, Fig 37, Para [0078]) comprising a plurality of solder bumps (120, connections for 102-2 are solder contacts 140 and solder 120 as shown in Fig 37 and are disclosed as a plurality of solder bonds in Para [0078]).
But Aleksov ‘517 fails to explicitly disclose a silicon buffer die coupled to a first surface of a first top side of the first die and a first surface of a second side of the second die, the silicon buffer die being positioned above the first die and the second die, wherein the silicon buffer die comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate, a heat spreader plane deposited on the silicon buffer die, the silicon buffer die being positioned between the heat spread plane and the first die, the heat spreader plane being a thermally conductive coating/film or a metal vapor chamber, the silicon buffer die acting as a transition layer to thermally couple the first die and the second die to the heat spreader plane
Nevertheless, in a related endeavor (Fig 3A-3B of Brun ‘664), Brun ‘664 teaches a silicon buffer die (345a/345b, Fig 3B of Brun ‘664, Para [0064] discloses 345a/345b as passive heat spreader interposer of silicon) coupled to a first surface (top of 310a as shown in Fig 3B of Brun ‘664) of a first top side (topside of leftmost 310a as shown in Fig 3B of Brun ‘664) of the first die (310a, Fig 3B of Brun ‘664, Para [0053]) and a first surface (top of 310b as shown in Fig 3B of Brun ‘664) of a second side (topside of leftmost 310b as shown in Fig 3B of Brun ‘664) of the second die (310b, Fig 3B of Brun ‘664, Para [0053]), the silicon buffer die (345a/345b) being positioned above (disclosed in Fig 3B of Brun ‘664) the first die (310a) and the second die (310b)(Fig 3B of Brun ‘664 discloses 345a/345b above 310a and 310b), wherein the silicon buffer die (345a/345b) comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate (Para [0064] of Brun ‘664 discloses 345a/345b comprises silicon), a heat spreader plane (340, Fig 3B of Brun ‘664, Para [0053]) deposited on (Note examiner’s above interpretation of “deposited on” as “on”)(340 on 345a/345b disclosed in Fig 3B and Para [0053] of Brun ‘664) the silicon buffer die (345a/345b), the silicon buffer die (345a/345b) being positioned between the heat spread plane (340) and the first die (310a)(Fig 3B of Brun ‘664 discloses 345a/345b between heat spreader 320 and first die 310a), the heat spreader plane (340) being a thermally conductive coating/film (340, Fig 3B, Para [0053]) or a metal vapor chamber, the silicon buffer die (345a/345b) acting as a transition layer to thermally couple the first die (310a) and the second die (310b) to the heat spreader plane (340)(Examiner Note: “acting as a transition layer to thermally couple” is a functional property of the silicon buffer die. That being said, Para [0053] of Brun ‘664 discloses 345a/345b as a heat spreader between die and layer 340).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Brun ‘664’s teaching of a silicon buffer die coupled to a first surface of a first top side of the first die and a first surface of a second side of the second die, the silicon buffer die being positioned above the first die and the second die, wherein the silicon buffer die comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate, a heat spreader plane deposited on the silicon buffer die, the silicon buffer die being positioned between the heat spread plane and the first die, the heat spreader plane being a thermally conductive coating/film or a metal vapor chamber, the silicon buffer die acting as a transition layer to thermally couple the first die and the second die to the heat spreader plane into Aleksov ‘517’s device. Aleksov ‘517 discloses a package on package structure and Aleksov ‘517 discloses the use of a thermal interface material (TIM) to remove heat from the structure and discloses that the TIM can be many different materials. Brun ‘664 also teaches a package on package structure and teaches means to remove heat from the device through the use of a silicon interposer between the die and the heat spreader plane. The ordinary artisan would then have a reasonable expectation of success in substituting the heat spreader design of Brun ‘664 for the TIM structure of Aleksov ‘517. Further, the ordinary artisan would have been motivated to modify Aleksov ‘517 in the manner set forth above, at least, because, as Brun ‘664 teaches in Para [0026] the use of the buffer die (silicon interposer 345a/345b of Brun ‘664) can compensate for thickness mismatch between the die to the heat spreader and helps to conduct heat from the die to the heat spreader.
As incorporated, the silicon buffer die (345a/345b) and the heat spreader plane (340) of Brun ‘664 would be used between the first (102-1) and second (102-2) dies and heat spreader plane (340) would be incorporated as the heat plane of Aleksov ‘517 so that 345a/345b is between the first and second die and the heat plane.
With respect to Claim 12 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the semiconductor device of claim 11, and Aleksov ‘517 further discloses wherein the interposer (150) comprises an organic interposer (Para [0030] discloses 150 as formed from an organic material).
With respect to Claim 13 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the semiconductor device of claim 11, and Aleksov ‘517 further discloses wherein the first type of area array interconnection (130) is one of:
a solder bonded interconnection; or
a copper bonded interconnection (Para [0026] discloses 130 as direct bonding having copper bonded interconnections).
With respect to Claim 14 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the semiconductor device of claim 13, and Aleksov ‘517 further discloses wherein the second type of area array interconnection (120) is one of solder bonded (120 is solder bond as disclosed in Para [0078]) or copper bonded, and different from the first type of area array (solder bond 120 is different than direct copper bond 130).
With respect to Claim 15 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the semiconductor device of claim 13, and Aleksov ‘517 further discloses wherein the copper bonded interconnection (130) includes one of direct copper bonding or hybrid copper bonding of the first die to the interposer (Para [0026] discloses direct bonding having copper bonded interconnections).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov ‘517 in view of Brun ‘664 in further view of Lin et al. (US 2013/0062761 A1, hereinafter Lin ‘761) in view of the following arguments.
With respect to Claim 4 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the apparatus of claim 3, and but Aleksov ‘517 as modified by Brun ‘664 fails to disclose wherein the solder bonded interconnection includes one of a copper pillar with solder tip or solder micro bump interconnection.
Nevertheless, in a related endeavor (Fig 2 of Lin ‘761), Lin ‘761 teaches wherein the solder bonded interconnection (connections of 116 to 112, Fig 2 of Lin ‘761, Para 0035]) includes one of a copper pillar (118, Fig 2 of Lin ‘761, Para [0035]) with solder tip (120, Fig 2 of Lin ‘761, Para [0035]) or solder micro bump interconnection.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to incorporate Lin ‘761’s teaching of the solder bonded interconnection includes one of a copper pillar with solder tip or solder micro bump interconnection into the apparatus of Aleksov ‘517 as modified by Brun ‘664. Aleksov ‘517 discloses a package on package structure and discloses various interconnections within the package and Para [0023] discloses that it is open to additional contact interconnections. Lin ‘761 also teaches a package and package structure with interconnections between package elements. The ordinary artisan would have been motivated to modify Aleksov ‘517 as modified by Brun ‘664 in the manner set forth above, at least, because using a copper pillar with solder tip to attach the dies allows the device to have a finer connection pitch than a standard solder connection.
As incorporated, the copper pillar (118) with solder tip (120) taught by Lin ‘761 would be used in the array (130) of Aleksov ‘517 as modified by Brun ‘664.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov ‘517 in view of Brun ‘664 in view of Park et al. (US 2018/0096913 A1, hereinafter Park ‘913) in view of the following arguments.
With respect to Claim 10 Aleksov ‘517 as modified by Brun ‘664 discloses all limitations of the apparatus of claim 1, and Aleksov ‘517 as modified by Brun ‘664 further discloses the heat spreader plane (152 of Aleksov ‘517) deposited (as modified, described above, the heat spreader plane 152 of Aleksov ‘517 would be on the silicon buffer die of Brun ‘664) on the silicon buffer die (345a/345b of Brun ‘664).
But Aleksov ‘517 as modified by Brun ‘664 fails to explicitly disclose wherein the heat spreader plane is a multilayer graphene plane.
Nevertheless, in a related endeavor (Fig 10 of Park ‘913), Park ‘913 teaches wherein the heat spreader plane (GL, Fig 10 of Park ‘913, Para [0050]) is a multilayer graphene plane (Para [0050] discloses GL as graphene).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to incorporate Park ‘913’s teaching of a graphene heat spreader plane teaching into the apparatus of Aleksov ‘517 as modified by Brun ‘664. Aleksov ‘517 discloses a package on package structure and Aleksov ‘517 discloses the use of a thermal interface material (TIM) to remove heat from the structure and discloses that the TIM can be many different materials. Park ‘913 teaches a semiconductor package structure and teaches a graphene TIM can be used the remove heat from the device. The ordinary artisan would have a reasonable expectation of success in using the well-known thermal interface material of graphene in place of the well-known TIM of Aleksov ‘517 to achieve the well-known advantage of removing heat from the semiconductor package. Further, the ordinary artisan would have been motivated to modify Aleksov ‘517 as modified by Brun ‘664 in the manner set forth above, at least, because, as Park ‘913 teaches in Para [0050], materials such as graphene and graphite have relatively superior thermal conductivity which would provide a more efficient heat transfer improving the operation of the device.
As incorporated, the teaching of Park ‘913 of using a multilayer graphene plane (GL) as a heat spreader plane would be used as the heat spreader plan (152) of Aleksov ‘517 as modified by Brun ‘664.
Claims 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov et al. (US 2022/0093517 A1, hereinafter Aleksov ‘517) in view of Brun et al. (US 2023/0197664 A1, hereinafter Brun ‘664), in further view of Ku et al. (US 2019/0385929 A1, hereinafter Ku ‘929) in view of the following arguments.
With respect to Claim 1 Aleksov ‘517 discloses an apparatus (100, Figs 1 and 37-44) comprising:
an interposer (150, Fig 37, Para [0077]) comprising one or more area array interconnections (connections for 102-1, connections for 102-2 and connections for 102-3 as shown in Fig 37), the one or more area array interconnections (connections for 102-1, connections for 102-2 and connections for 102-3 as shown in Fig 37) including a first type of area array interconnection (130, connections for 102-1 (DB contacts 110) shown in Fig 37 are disclosed as direct bond, Para [0078]) and a second type of area array interconnection (120, connections for 102-2 (solder contacts 140 and solder 120) shown in Fig 37 are disclosed as solder bond in Para [0078]);
a first die (102-1, Fig 37, Para [0078]) coupled to the interposer (150) via the first type of area array interconnection (130); and
a second die (102-2, Fig 37, Para 0078]) coupled to the interposer (150) via the second type of area array interconnection (120),
a heat spreader plane (152, Fig 1, Para [0024]), wherein the heat spreader plane (152) is configured to distribute heat within the heat spreader plane (Para [0040] disclose heat spreader plane dissipates heat from die)
wherein the first type of area array interconnection (130) is different from the second type of area array interconnection (120)(130 is direct bond and 120 is solder bond as disclosed in Para [0078]);
wherein the interposer (150) comprises the first type of area array interconnection (direct bonding 130, Fig 37, Para [0078]) comprising direct copper-to-copper bonding (the connections for 102-1 in area array 130 are direct bond contacts 110 as shown in Fig 37 and are disclosed as direct bond in Para [0078]) and the second type of area array interconnection (solder bonding 120/140, Fig 37, Para [0078]) comprising a plurality of solder bumps (120, connections for 102-2 are solder contacts 140 and solder 120 as shown in Fig 37 and are disclosed as a plurality of solder bonds in Para [0078]).
But Aleksov ‘517 fails to explicitly disclose a silicon buffer die coupled to a first surface of a first top side of the first die and a first surface of a second side of the second die, the silicon buffer die being positioned above the first die and the second die, wherein the silicon buffer die comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate, a heat spreader plane deposited on the silicon buffer die, the silicon buffer die being positioned between the heat spread plane and the first die, the silicon buffer die acting as a transition layer to thermally couple the first die and the second die to the heat spreader plane.
Nevertheless, in a related endeavor (Fig 3A-3B of Brun ‘664), Brun ‘664 teaches a silicon buffer die (345a/345b, Fig 3B of Brun ‘664, Para [0064] discloses 345a/345b as passive heat spreader interposer of silicon) coupled to a first surface (top of 310a as shown in Fig 3B of Brun ‘664) of a first top side (topside of leftmost 310a as shown in Fig 3B of Brun ‘664) of the first die (310a, Fig 3B of Brun ‘664, Para [0053]) and a first surface (top of 310b as shown in Fig 3B of Brun ‘664) of a second side (topside of leftmost 310b as shown in Fig 3B of Brun ‘664) of the second die (310b, Fig 3B of Brun ‘664, Para [0053]), the silicon buffer die (345a/345b) being positioned above (disclosed in Fig 3B of Brun ‘664) the first die (310a) and the second die (310b)(Fig 3B of Brun ‘664 discloses 345a/345b above 310a and 310b), wherein the silicon buffer die (345a/345b) comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate (Para [0064] of Brun ‘664 discloses 345a/345b comprises silicon), a heat spreader plane (320, Fig 3B of Brun ‘664, Para [0053]) deposited on (Note examiner’s above interpretation of “deposited on” as “on”)(320 on 345a/345b disclosed in Fig 3B and Para [0053] of Brun ‘664) the silicon buffer die (345a/345b), the silicon buffer die (345a/345b) being positioned between the heat spread plane (320) and the first die (310a)(Fig 3B of Brun ‘664 discloses 345a/345b between heat spreader 320 and first die 310a) the silicon buffer die (345a/345b) acting as a transition layer to thermally couple the first die (310a) and the second die (310b) to the heat spreader plane (320)( Examiner Note: “acting as a transition layer to thermally couple” is a functional property of the silicon buffer die. That being said, Para [0053] of Brun ‘664 discloses 345a/345b as a heat spreader between die and layer 340).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Brun ‘664’s teaching of a silicon buffer die coupled to a first surface of a first top side of the first die and a first surface of a second side of the second die, the silicon buffer die being positioned above the first die and the second die, wherein the silicon buffer die comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate, a heat spreader plane deposited on the silicon buffer die, the silicon buffer die being positioned between the heat spread plane and the first die, the silicon buffer die acting as a transition layer to thermally couple the first die and the second die to the heat spreader plane into Aleksov ‘517’s device. Aleksov ‘517 discloses a package on package structure and Aleksov ‘517 discloses the use of a thermal interface material (TIM) to remove heat from the structure and discloses that the TIM can be many different materials. Brun ‘664 also teaches a package on package structure and teaches means to remove heat from the device through the use of a silicon interposer between the die and the heat spreader plane. The ordinary artisan would then have a reasonable expectation of success in substituting the heat spreader design of Brun ‘664 for the TIM structure of Aleksov ‘517. Further, the ordinary artisan would have been motivated to modify Aleksov ‘517 in the manner set forth above, at least, because, as Brun ‘664 teaches in Para [0026] the use of the buffer die (silicon interposer 345a/345b of Brun ‘664) can compensate for thickness mismatch between the die to the heat spreader and helps to conduct heat from the die to the heat spreader.
As incorporated, the silicon buffer die (345a/345b) and of Brun ‘664 would be used between the first (102-1) and second (102-2) dies and the heat plane (152) of Aleksov ‘517 so that 345a/345b is between the first and second die and the heat plane.
Aleksov ‘517 as modified by Brun ‘664 fails to explicitly disclose the heat spreader plane being a metal vapor chamber.
Nevertheless, in a related endeavor (Fig 1A of Ku ‘929), Ku ‘929 teaches the heat spreader plane (131, Fig 1A of Ku ‘929, Para [0030]) being a metal vapor chamber (Para [0030] of Ku ‘929 discloses 131 as a vapor chamber lid).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ku ‘929’s teaching of the heat spreader plane being a metal vapor chamber into Aleksov ‘517 as modified by Brun ‘664’s device. Aleksov ‘517 as modified by Brun ‘664 discloses a package on package structure and Aleksov ‘517 discloses the use of a thermal interface material (TIM) to remove heat from the structure and discloses that the TIM can be many different materials. Brun ‘664 teaches a package on package structure and teaches means to remove heat from the device through the use of a silicon interposer between the die and the heat spreader plane. Aleksov ‘517 as modified by Brun ‘664 is open to the heat spreader plane having other configurations as Aleksov ‘517 discloses in Para [0041] “The heat transfer structure 152 may include any suitable thermally conductive material (e.g., metal, appropriate ceramics, etc.), and may include any suitable features (e.g., a heat spreader, a heat sink including fins, a cold plate, etc.)”. The ordinary artisan would then have a reasonable expectation of success in substituting the heat spreader design of Ku ‘929 for the heat spreader structure of Aleksov ‘517 as modified by Brun ‘664. Further, the ordinary artisan would have been motivated to modify Aleksov ‘517 as modified by Brun ‘664 in the manner set forth above, at least, because, as Ku ‘929 teaches in Para [0020] the use of the vapor chamber lid enables an increase thermal spreading effects and a reduction of package thermal resistance.
As incorporated, the heat spreader plane being a metal vapor chamber (131) of Ku ‘929 would be used as the heat spreader plane in the apparatus of Aleksov ‘517 as modified by Brun ‘664.
With respect to Claim 11 Aleksov ‘517 discloses a semiconductor device (100, Figs 1 and 37-44 and 49) comprising:
a circuit board (182, Fig 41, Para [0037]) comprising one or more internal layers (Para [0037] discloses 182 includes conductive pathways);
a first semiconductor package (100, Fig 41, Para [0083]) coupled to the circuit board (182), the first semiconductor package (100) including:
substrate (Para [0037 discloses additional components, “the support component 182 may include another IC package, an interposer, or any other suitable component” coupled to 182) coupled to the circuit board (182)
an interposer (150, Fig 49, Para [0077]) coupled to the circuit board (182), the interposer (150) comprising one or more area array interconnections (connections for 102-1, connections for 102-2 and connections for 102-3 as shown in Fig 49, Para [0083]), the one or more area array interconnections (connections for 102-1, connections for 102-2 and connections for 102-3) including a first type of area array interconnection (130, connections for 102-1 (DB contacts 110) shown in Fig 37 are disclosed as direct bond, Para [0078]), and a second type of area array interconnection (120, connections for 102-2 (solder contacts 140 and solder 120) shown in Fig 37 are disclosed as solder bond in Para [0078]);
a first die (102-1, Fig 37, Para [0078]) coupled to the interposer (150) via the first type of area array interconnection (130 disclosed in Para [0078] as direct bonded); and
a second die (102-2, Fig 37, Para 0078]) coupled to the interposer (150) via the second type of area array interconnection (120, connections for 102-2 (solder contacts 140 and solder 120) shown in Fig 37 are disclosed as solder bond in Para [0078]),
a heat spreader plane (152, Fig 1, Para [0024]), wherein the heat spreader plane (152) is configured to distribute heat within the heat spreader plane (Para [0040] disclose heat spreader plane dissipates heat from die)
wherein the first type of area array interconnection (130) is different from the second type of area array interconnection (120)(direct bonding, 130, is different than solder bond 120);
wherein the interposer (150) comprises the first type of area array interconnection (direct bonding 130, Fig 37, Para [0078]) comprising direct copper-to-copper bonding (the connections for 102-1 in area array 130 are direct bond contacts 110 as shown in Fig 37 and are disclosed as direct bond in Para [0078]) and the second type of area array (120) interconnection (solder bonding 120/140, Fig 37, Para [0078]) comprising a plurality of solder bumps (120, connections for 102-2 are solder contacts 140 and solder 120 as shown in Fig 37 and are disclosed as a plurality of solder bonds in Para [0078]).
But Aleksov ‘517 fails to explicitly disclose a silicon buffer die coupled to a first surface of a first top side of the first die and a first surface of a second side of the second die, the silicon buffer die being positioned above the first die and the second die, wherein the silicon buffer die comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate, a heat spreader plane deposited on the silicon buffer die, the silicon buffer die being positioned between the heat spread plane and the first die the silicon buffer die acting as a transition layer to thermally couple the first die and the second die to the heat spreader plane.
Nevertheless, in a related endeavor (Fig 3A-3B of Brun ‘664), Brun ‘664 teaches a silicon buffer die (345a/345b, Fig 3B of Brun ‘664, Para [0064] discloses 345a/345b as passive heat spreader interposer of silicon) coupled to a first surface (top of 310a as shown in Fig 3B of Brun ‘664) of a first top side (topside of leftmost 310a as shown in Fig 3B of Brun ‘664) of the first die (310a, Fig 3B of Brun ‘664, Para [0053]) and a first surface (top of 310b as shown in Fig 3B of Brun ‘664) of a second side (topside of leftmost 310b as shown in Fig 3B of Brun ‘664) of the second die (310b, Fig 3B of Brun ‘664, Para [0053]), the silicon buffer die (345a/345b) being positioned above (disclosed in Fig 3B of Brun ‘664) the first die (310a) and the second die (310b)(Fig 3B of Brun ‘664 discloses 345a/345b above 310a and 310b), wherein the silicon buffer die (345a/345b) comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate (Para [0064] of Brun ‘664 discloses 345a/345b comprises silicon), a heat spreader plane (320, Fig 3B of Brun ‘664, Para [0053]) deposited on (Note examiner’s above interpretation of “deposited on” as “on”)(320 on 345a/345b disclosed in Fig 3B and Para [0053] of Brun ‘664) the silicon buffer die (345a/345b), the silicon buffer die (345a/345b) being positioned between the heat spread plane (320) and the first die (310a)(Fig 3B of Brun ‘664 discloses 345a/345b between heat spreader 320 and first die 310a) the silicon buffer die (345a/345b) acting as a transition layer to thermally couple the first die (310a) and the second die (310b) to the heat spreader plane (320)( Examiner Note: “acting as a transition layer to thermally couple” is a functional property of the silicon buffer die. That being said, Para [0053] of Brun ‘664 discloses 345a/345b as a heat spreader between die and layer 340).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Brun ‘664’s teaching of a silicon buffer die coupled to a first surface of a first top side of the first die and a first surface of a second side of the second die, the silicon buffer die being positioned above the first die and the second die, wherein the silicon buffer die comprises at least one of a silicon carrier die, a buffer die, or a silicon wafer substrate, a heat spreader plane deposited on the silicon buffer die, the silicon buffer die being positioned between the heat spread plane and the first die, the silicon buffer die acting as a transition layer to thermally couple the first die and the second die to the heat spreader plane into Aleksov ‘517’s device. Aleksov ‘517 discloses a package on package structure and Aleksov ‘517 discloses the use of a thermal interface material (TIM) to remove heat from the structure and discloses that the TIM can be many different materials. Brun ‘664 also teaches a package on package structure and teaches means to remove heat from the device through the use of a silicon interposer between the die and the heat spreader plane. The ordinary artisan would then have a reasonable expectation of success in substituting the heat spreader design of Brun ‘664 for the TIM structure of Aleksov ‘517. Further, the ordinary artisan would have been motivated to modify Aleksov ‘517 in the manner set forth above, at least, because, as Brun ‘664 teaches in Para [0026] the use of the buffer die (silicon interposer 345a/345b of Brun ‘664) can compensate for thickness mismatch between the die to the heat spreader and helps to conduct heat from the die to the heat spreader.
As incorporated, the silicon buffer die (345a/345b) and of Brun ‘664 would be used between the first (102-1) and second (102-2) dies and the heat plane (152) of Aleksov ‘517 so that 345a/345b is between the first and second die and the heat plane.
Aleksov ‘517 as modified by Brun ‘664 fails to explicitly disclose the heat spreader plane being a metal vapor chamber.
Nevertheless, in a related endeavor (Fig 1A of Ku ‘929), Ku ‘929 teaches the heat spreader plane (131, Fig 1A of Ku ‘929, Para [0030]) being a metal vapor chamber (Para [0030] of Ku ‘929 discloses 131 as a vapor chamber lid).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ku ‘929’s teaching of the heat spreader plane being a metal vapor chamber into Aleksov ‘517 as modified by Brun ‘664’s device. Aleksov ‘517 as modified by Brun ‘664 discloses a package on package structure and Aleksov ‘517 discloses the use of a thermal interface material (TIM) to remove heat from the structure and discloses that the TIM can be many different materials. Brun ‘664 teaches a package on package structure and teaches means to remove heat from the device through the use of a silicon interposer between the die and the heat spreader plane. Aleksov ‘517 as modified by Brun ‘664 is open to the heat spreader plane having other configurations as Aleksov ‘517 discloses in Para [0041] “The heat transfer structure 152 may include any suitable thermally conductive material (e.g., metal, appropriate ceramics, etc.), and may include any suitable features (e.g., a heat spreader, a heat sink including fins, a cold plate, etc.)”. The ordinary artisan would then have a reasonable expectation of success in substituting the heat spreader design of Ku ‘929 for the heat spreader structure of Aleksov ‘517 as modified by Brun ‘664. Further, the ordinary artisan would have been motivated to modify Aleksov ‘517 as modified by Brun ‘664 in the manner set forth above, at least, because, as Ku ‘929 teaches in Para [0020] the use of the vapor chamber lid enables an increase thermal spreading effects and a reduction of package thermal resistance.
As incorporated, the heat spreader plane being a metal vapor chamber (131) of Ku ‘929 would be used as the heat spreader plane in the apparatus of Aleksov ‘517 as modified by Brun ‘664.
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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