DETAILED ACTION
Response to Arguments
Applicant's arguments filed 03/04/2025 have been fully considered but they are not persuasive.
Applicant argues 20200075490 A1 Sung hereafter “Sung” and Sung in view of US 20160315072 A1 Keser et al hereafter “Keser” do not teach all of the claimed features.
Applicant Emphasis the limitations “a first integrated device coupled to the first metallization portion through a first plurality of solder interconnects, wherein the first plurality of solder interconnects directly touch some metallization interconnects from the first plurality of metallization interconnects; an interconnection die coupled to the first metallization portion through a second plurality of solder interconnects, wherein the second plurality of solder interconnects directly touch some other metallization interconnects from the first plurality of metallization interconnects;” and “wherein the second metallization portion is coupled to and directly touches the interconnection die”. After additional consideration of the claim limitations and the amended features and/or scope the examiner respectfully disagrees as shown in the rejections below.
The applicant impart argues the prior art of record does not teach the limitation of;
the direct touch between the first plurality of solder interconnects and some metallization interconnects from first plurality of metallization interconnects.
the direct touch between the second plurality of solder interconnects and some other metallization interconnects from the first plurality of metallization interconnects.
The direct touch between the second metallization portion and the interconnection die.
In view of the modification that the interconnects of Sung comprise a solder as shown in below and in prior non-final office action filed 12/04/2025 these features are sufficiently illustrated fig. 1 and fig. 3 the argument of the applicant appears to match the features and/or interpret the prior art in a different manner than as matched an/or the specific interpretation applied by the examiner [See annotation below]. under broadest reasonable interpretation [See MPEP 2111] the examiner must use the broadest reasonable interpretation consistent with the specification without importing limitations from the specification. The examiner notes that structural differences between the current prior art of record and instant applicant can be seen within the drawings and specification however these differences are not currently claimed as written. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant also in part that Sung does not teach “a first integrated device coupled to the first metallization portion through a first plurality of solder interconnects”. The examiner as shown prior office action filed agrees that Sung does not explicitly teach the first plurality of interconnects comprising solder. However, the examiner does not purely rely on the device explicitly disclosed by Sung but a Modified Sung in view of what Sung teaches. As shown in prior non-final office action filed 02/07/2025 and below Sung teaches “a first integrated device coupled to the first metallization portion through a first plurality interconnects” and separately “Solder” as a material for interconnects to reduce the overall thickness of the device and/or the selection of a known material (solder) based on its suitability for its intended use (an interconnect) is prima facie type obviousness [see MPEP 2144.07]. Note that under broadest reasonable interpretation “Solder” includes but is not limited to the meaning “A metal alloy with a melting temperature that is below 427 ºC [800 ºF]” [IPC-T-50M], “interconnection” includes but is not limited to the meaning “the joining of electrical devices to complete a circuit” [IPC-T-50M] and “Solder Connection” includes but is not limited to the meaning “A metallurgical connection serving electrical/mechanical/thermal functions that employs solder for the joining of two or more metal surfaces” [IPC-T-50M].
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
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Annotated fig. 1: highlighting the limitations as match by the examiner
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 11 and dependent claims recites the limitation “means for die interconnection” in “means for die interconnection coupled to the first metallization portion through a first plurality of solder interconnects” [Claim 11], “the means for die interconnection are located between the first metallization portion and the second metallization portion” [Claim 11], “wherein the second metallization portion is coupled to and directly touches the means for die interconnection” [Claim 11], “wherein the means for die interconnection comprises” [Claim 12], “wherein the means for die interconnection comprises” [claim 19].
The corresponding structure described in the applicant’s specification that performs this function is interconnection die 101. Note; interpretation under 112(f) was acknowledged by applicant in arguments filed 05/05/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-12, and 15-20 are rejected under 35 U.S.C. 103 as being obvious over US 20200075490 A1 Sung hereafter “Sung”.
Regarding claim 1 Sung teaches a package comprising:
a first metallization portion (150 fig. 1) comprising:
at least one first dielectric layer (152, and/or 154 and/or 156 fig. 3, illustrated but not labeled in fig. 1); and
a first plurality of metallization interconnects (151, and/or 153, and/or 155 fig. 3 illustrated but not fully labeled in fig. 1);
a first integrated device coupled (110 fig. 1) to the first metallization portion through a first plurality of interconnects (111 fig. 3, illustrated but not labeled fig. 1, “contact pads” qualify as a type of interconnect under broadest reasonable interpretation, the general meaning of “pad” includes but is not limited by “land”, “a portion of a conductive pattern usually used for connection and/or attachment of components” [ICP-T-50M 2015], [see MPEP 2111] and/or is material the same as an interconnect [see MPEP 2112]), wherein the first plurality of interconnects directly touch some metallization interconnects (151, fig. 1 and 3) from the first plurality of metallization interconnects [illustrated fig. 1 and fig. 3];
an interconnection die (120L and 125L fig. 1 and/or 120R and 125R fig. 1) coupled to the first metallization portion through a second plurality of interconnects (121L fig. 3, 121L and 121R illustrated but not labeled fig. 1, “via pads” qualify as a type of interconnect under broadest reasonable interpretation, the general meaning of “pad” includes but is not limited by “land”, “a portion of a conductive pattern usually used for connection and/or attachment of components” [ICP-T-50M 2015], [see MPEP 2111] and/or is material the same as an interconnect [see MPEP 2112]), wherein the second plurality of interconnects directly touch some other metallization interconnects (153 fig. 1 and fig. 3) from the first plurality of metallization interconnects [illustrated fig. 1 and fig. 3];
a second metallization portion (250 fig. 1) coupled to the first metallization portion through (i) the interconnection die and (ii) the second plurality of interconnects, such that the first integrated device and the interconnection die are located between the first metallization portion and the second metallization portion,
wherein the second metallization portion is coupled to and directly touches the interconnection die [sufficiently illustrated fig. 1, limitation is met as second metallization portion 250 includes element 510 which directly touches element 125R and/or 125L of the interconnection die], and
wherein the second metallization portion comprises:
at least one second dielectric layer (252 and/or 254 fig. 4, illustrated but not labeled fig. 1); and
a second plurality of metallization interconnects (251 fig. 4 illustrated in fig. 1 but not labeled); and
an encapsulation layer (160 and 610 fig. 1) coupled to the first metallization portion and the second metallization portion, wherein (at least a portion of) the encapsulation layer is located between the first metallization portion and the second metallization portion.
A plurality of solder interconnects (510 fig. 1 and 590 fig. 1, sufficiently disclosed “The inner connectors 510 may be realized using solder balls” Paragraph 0030 and “The outer connectors 590 may be realized using solder balls” Paragraph 0031) and sufficiently discloses the use of solder interconnects “may lead to reduction of a thickness of the stack package” [Paragraph 0031]
Sung does not teach the first plurality of interconnects being a first plurality of solder interconnects nor the second plurality of interconnects being a second plurality of solder interconnects.
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute the first plurality of interconnects and the second plurality of interconnects with solder interconnects such that the first plurality of interconnects and the second plurality of interconnects are “a first plurality of solder interconnects” and “a second plurality of solder interconnects” to reduce the overall thickness of the device and/or the selection of a known material (solder) based on its suitability for its intended use (an interconnect) is prima facie type obviousness [see MPEP 2144.07].
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Annotated fig. 1: highlighting the limitations as match by the examiner
Regarding claim 2 Modified Sung teaches as shown above the package of claim 1, wherein the interconnection die comprises:
a die substrate (129 illustrated as 129L in fig. 3, illustrated but not labeled fig. 1); and
a plurality of die interconnects (comprising 121, 123, and 125; illustrated as 121L, 123L, 125L in fig. 3, illustrated in fig. 1 but not fully labeled) wherein some of the die interconnects [125R and/or 125L fig. 1 and fig. 3] from the plurality of die interconnects touch some metallization interconnects [510 fig. 1 and fig. 3, sufficiently disclosed paragraph 0030 “Inner connectors” comprising “solder” which is metal ] from the second plurality of metallization interconnects [sufficiently illustrated fig. 1, limitation is met as second metallization portion 250 includes element 510 which touches element 125R and/or 125L of the interconnection die].
Regarding claim 5 modified Sung teaches as shown above the package of claim 2, wherein the plurality of die interconnects includes a via die interconnect (123; illustrated as 123L fig. 3, illustrated but not fully labeled fig. 1) and a pad die interconnect (121L-R and 125R; illustrated as 121L and 125L fig. 3; illustrated in fig. 1 but not labeled, met under MPEP 2111 and/or MPEP 2112.01, the general meaning of “pad” includes but is not limited by “land”, “a portion of a conductive pattern usually used for connection and/or attachment of components” [ICP-T-50M 2015] and this is sufficiently illustrated fig. 1 and 3, 121 and 125 are portions of a conductive pattern and connect adjacent electrical components), wherein the pad die interconnect touches a metallization interconnects [510 fig. 1 and fig. 3 disclosed as “inter connection” and “Solder” which is a metal, sufficiently disclosed paragraph 0030] from the second plurality of metallization interconnects [sufficiently illustrated fig. 1 and fig. 3 at least pad die interconnect element 125R and/or 125 L touch element 510 of the metallization interconnects].
Regarding claim 6 Modified Sung teaches as shown above the package of claim 2, wherein the die substrate includes glass and/or silicon. [sufficiently discloses and embodiment of silicon in paragraph 0039 “Since the first left body 129L of the first left bridge die 120L is comprised of a semiconductor material, the first left through vias 123L may be formed using a semiconductor process, for example, a silicon process. Thus, the first left through vias 123L may be formed to have a through silicon via (TSV) structure with a fine diameter D1”]
Regarding claim 7 Modified Sung teaches as shown above the package of claim 1, further comprising a second integrated device (210 fig. 1) coupled to the second metallization portion, wherein the first integrated device is a first chiplet and the second integrated device is a second chiplet [sufficiently illustrated fig. 1], and wherein a front side of the first integrated device [the bottom side as illustrated fig. 1 constitutes a front side under broadest reasonable interpretation of “front side” and/or MPEP 2112.01, wherein the bottom-side has all the structure disclosed necessary to be considered the front side] faces in a direction [down fig. 1] towards the first metallization portion [illustrated fig. 1].
Regarding claim 8 Modified Sung teaches as shown above the package of claim 1
wherein the first metallization portion includes a first redistribution portion (151 fig. 3, illustrated in fig. 1),
wherein the first plurality of metallization interconnects includes a first plurality of redistribution interconnects [illustrated in fig. 1],
wherein the second metallization portion includes a second redistribution portion (155 fig. 3 illustrated in fig. 3), and
wherein the second plurality of metallization interconnects includes a second plurality of redistribution interconnects [illustrated in fig. 1].
Regarding claim 9 Modified Sung teaches as shown above the package of claim 8
wherein a first portion of a first redistribution interconnect from the first plurality of redistribution interconnects, includes a side profile that has a U-shape or a V shape [fig. 1 and 3 illustrates a side profile with a U-shape tip, see annotation below], and
wherein a second portion of a second redistribution interconnect from the second plurality of redistribution interconnects, includes a side profile that has a U-shape or a V shape [fig. 1 and 3 illustrates a side profile that has a U-shape tip, see annotation below].
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Annotated fig. 3; highlighting the U-shaped profiles in a side view
Regarding claim 10 Modified Sung teaches as shown above the package of claim 1, wherein the interconnection die is free of transistors. [this limitation is met as no transistors illustrated as part of the interconnect die]
Regarding claim 11 Sung teaches a device comprising:
a first package (100 and 200 fig. 1) comprising:
a first metallization portion (150 fig. 1) comprising:
at least one first dielectric layer (152, 154, 156 fig. 3; not fully labeled in fig. 1 but illustrated); and a first plurality of metallization interconnects (151, 153, 155 fig. 1 and fig. 3);
a first integrated device (110 fig. 1) coupled to the first metallization portion through a first plurality of interconnects(111 fig. 3, illustrated but not labeled fig. 1, “contact pads” qualify as a type of interconnect under broadest reasonable interpretation [see MPEP 2111] and/or is material the same as an interconnect [see MPEP 2112]), wherein the first plurality of interconnects directly touch some metallization interconnects (151, fig. 1 and 3) from the first plurality of metallization interconnects [illustrated fig. 1 and fig. 3];
means for die interconnection (120L-R and 125L-R fig. 1 and 3) coupled to the first metallization portion through a second plurality of interconnects (121L fig. 3, 121L and 121R illustrated but not labeled fig. 1, “via pads” qualify as a type of interconnect under broadest reasonable interpretation [see MPEP 2111] and/or is material the same as an interconnect [see MPEP 2112]), wherein the second plurality of interconnects directly touch some other metallization interconnects (153 fig. 1 and fig. 3) from the first plurality of metallization interconnects [illustrated fig. 1 and fig. 3];
a second metallization portion (250 fig. 1) coupled to the first metallization portion through (i) the means for die interconnection and (ii) the second plurality of interconnects,
such that the first integrated device and the means for die interconnection are located between the first metallization portion and the second metallization portion [illustrated in fig. 1 the structures are physically and/or electrically coupled through the die interconnection],
wherein the second metallization portion is coupled to and directly touches the means for die interconnection [sufficiently illustrated fig. 1, limitation is met as second metallization portion 250 includes element 510 which directly touches element 125R and/or 125L of the interconnection die], and
wherein the second metallization portion comprises:
at least one second dielectric layer (252, 254 fig. 4 illustrated in fig. 1 not fully labeled); and a second plurality of metallization interconnects (251 fig. 4; illustrated in fig. 1 not fully labeled); and an encapsulation layer (comprising 160 and 610 fig. 1) coupled to the first metallization portion and the second metallization portion [illustrated in fig. 1], wherein (at least a portion of) the encapsulation layer is located between the first metallization portion and the second metallization portion [illustrated in fig. 1].
A plurality of solder interconnects (510 fig. 1 and 590 fig. 1, sufficiently disclosed “The inner connectors 510 may be realized using solder balls” Paragraph 0030 and “The outer connectors 590 may be realized using solder balls” Paragraph 0031) and sufficiently discloses the use of solder interconnects “may lead to reduction of a thickness of the stack package” [Paragraph 0031]
Sung does not teach the first plurality of interconnects being a first plurality of solder interconnects nor the second plurality of interconnects being a second plurality of solder interconnects.
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute the first plurality of interconnects and the second plurality of interconnects with solder interconnects such that the first plurality of interconnects and the second plurality of interconnects are “a first plurality of solder interconnects” and “a second plurality of solder interconnects” to reduce the overall thickness of the device and/or the selection of a known material (solder) based on its suitability for its intended use (an interconnect) is prima facie type obviousness [see MPEP 2144.07].
Regarding claim 12 Modified Sung teaches as shown above the device of claim 11, wherein the means for die interconnection comprises:
a die substrate (129R and 129 L fig. 1); and
a plurality of die interconnects (120L-R and 125L-R fig. 1), wherein some of the die interconnects [125R and/or 125L fig. 1 and fig. 3] from the plurality of die interconnects touch some metallization interconnects [510 fig. 1 and fig. 3, sufficiently disclosed paragraph 0030 “Inner connectors” comprising “solder” which is metal ] from the second plurality of metallization interconnects [sufficiently illustrated fig. 1, limitation is met as second metallization portion 250 includes element 510 which touches element 125R and/or 125L of the interconnection die].
Regarding claim 15 Modified Sung teaches as shown above the device of claim 12, wherein the plurality of die interconnects includes a via die interconnect (123L-R; illustrated in fig. 3 as 123L; illustrated in fig. 1 not fully labeled) and a pad die interconnect (121L-R and 125R; illustrated as 121L and 125L fig. 3; illustrated in fig. 1 but not labeled, met under MPEP 2111 and/or MPEP 2112.01, the general meaning of “pad” includes but is not limited by “land”, “a portion of a conductive pattern usually used for connection and/or attachment of components” [ICP-T-50M 2015] and this is sufficiently illustrated fig. 1 and 3, 121 and 125 are portions of a conductive pattern and connect adjacent electrical components), wherein the pad die interconnect touches a metallization interconnects [510 fig. 1 and fig. 3 disclosed as “inter connection” and “Solder” which is a metal, sufficiently disclosed paragraph 0030] from the second plurality of metallization interconnects [sufficiently illustrated fig. 1 and fig. 3 at least pad die interconnect element 125R and/or 125 L touch element 510 of the metallization interconnects].
Regarding claim 16 Modified Sung teaches as shown above the device of claim 12, wherein the die substrate includes glass and/or silicon. [sufficiently discloses and embodiment of silicon in paragraph 0039 “Since the first left body 129L of the first left bridge die 120L is comprised of a semiconductor material, the first left through vias 123L may be formed using a semiconductor process, for example, a silicon process. Thus, the first left through vias 123L may be formed to have a through silicon via (TSV) structure with a fine diameter D1”]
Regarding claim 17 Modified Sung teaches as shown above the device of claim 11
wherein the first metallization portion includes a first redistribution portion (151 fig. 1 and fig. 3),
wherein the first plurality of metallization interconnects includes a first plurality of redistribution interconnects,
wherein the second metallization portion includes a second redistribution portion, and
wherein the second plurality of metallization interconnects includes a second plurality of redistribution interconnects.
Regarding claim 18 Modified Sung teaches as shown above the device of claim 11, further comprising a second package (300 and 400 fig. 1) coupled to the first package through a third plurality of solder interconnects (510 fig. 1, “solder balls” Paragraph 0031), wherein the second package comprises:
a substrate (350 fig 1);
a second integrated device (310 fig. 1) coupled to the substrate; and
a second encapsulation layer (300 fig. 1 is illustrated as being the same as 200 fig. 1 which comprises encapsulation layer and/or molding layer 260 fig. 1) coupled to the substrate and the second integrated device [illustrated in fig. 1].
Regarding claim 19 Modified Sung teaches as shown above the device of claim 11, wherein the means for die interconnection is free of transistors [means for die interconnection element is interpreted under 35 U.S.C. 112(f) as the interconnection die from 101 fig. 1 comprising interconnects 112 and substrate 110 of the instant application, Sung illustrates in fig. 1 and fig. 3 as die interconnection 120L-R and 125L-R is physically and/or electrically coupled to the first metallization portion, no transistor is illustrated in fig. 1 and/or 3 as part of the die interconnection].
Regarding claim 20 Modified Sung teaches as shown above the device of claim 11, wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle. [As to claim 20 Sung sufficiently discloses embodiments of “a personal digital assistant”, “a personal computer”, and “a mobile phone” [Paragraph 130]. Additionally per MPEP 2112.01, the device is structurally and compositionally the same as disclosed and/or claimed thus meets this functional limitation and/or intended use limitation].
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sung as applied above, and further in view of US 20160315072 A1 Keser et al hereafter “Keser”.
Regarding claim 3 Modified Sung teaches as shown above the package of claim 2,
Sung does not teach two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of 150-270 micrometers.
Keser teaches two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of 150-270 micrometers. [Sufficently discloses an embodiment of 200 μm, Paragraph 0051 the pitch of the two adjacent vias in the package interconnect 210 may be about 200 microns (μm) or less]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the shape and/or size of the die interconnects as Sung teaches such that they have a pitch of 200 μm as Keser teaches such that “two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of 150-270 micrometers” as changes in shape and/or size is prima facie type obviousness [see MPEP 2144.04] and/or optimize the parasitic capacitance between adjacent conductor elements.
Regarding claim 13 Modified Sung teaches as shown above the package of claim 12,
Sung does not teach two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of 150-270 micrometers.
Keser teaches two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of 150-270 micrometers. [Sufficiently discloses an embodiment of 200 μm, Paragraph 0051 the pitch of the two adjacent vias in the package interconnect 210 may be about 200 microns (μm) or less]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the shape and/or size of the die interconnects as Sung teaches such that they have a pitch of 200 μm as Keser teaches such that “two neighboring die interconnects from the plurality of die interconnects have a pitch in a range of 150-270 micrometers” as changes in shape and/or size is prima facie type obviousness [see MPEP 2144.04] and/or optimize the parasitic capacitance between adjacent conductor elements.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sung as applied above, and further in view of US 20200006293 A1 Sankman et al hereafter “Sankman” .
Regarding claim 4 Modified Sung teaches as shown above the package of claim 2,
Sung does not teach the plurality of die interconnects have an aspect ratio in a range of 20:1 to 10:1.
Sankman teaches the plurality of die interconnects have an aspect ratio in a range of 20:1 to 10:1 [Paragraph 0055, “the height:width aspect ratio of the conductive pillars [712] may be… 10:1 or greater”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the relative proportions of the die interconnects as Sung teaches such that they have an aspect ratio greater than 10:1 as Sankman teaches such that “the plurality of die interconnects have an aspect ratio in a range of 20:1 to 10:1” as changes in relative proportions are prima facie type obviousness [see MPEP 2144.04], to enable a suitable height for forming electronics packages in a face-to-face configuration [Sankman Paragraph 0055], and/or reduce the shear forces at the interconnects ends and reduce the chances of fatigue and failure [evidenced by US 5474458 A Vafi Column 8 line 67 through Column 9 line 17 ]
Regarding claim 14 Modified Sung teaches as shown above the package of claim 12,
Sung does not teach the plurality of die interconnects have an aspect ratio in a range of 20:1 to 10:1.
Sankman teaches the plurality of die interconnects have an aspect ratio in a range of 20:1 to 10:1 [Paragraph 0055, “the height:width aspect ratio of the conductive pillars [712] may be… 10:1 or greater”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the relative proportions of the die interconnects as Sung teaches such that they have an aspect ratio greater than 10:1 as Sankman teaches such that “the plurality of die interconnects have an aspect ratio in a range of 20:1 to 10:1” as changes in relative proportions are prima facie type obviousness [see MPEP 2144.04], to enable a suitable height for forming electronics packages in a face-to-face configuration [Sankman Paragraph 0055], and/or reduce the shear forces at the interconnects ends and reduce the chances of fatigue and failure [evidenced by US 5474458 A Vafi Column 8 line 67 through Column 9 line 17 ]
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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