DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OHGURO (US 20150249156).
Regarding claim 1, OHGURO discloses an integrated circuit, comprising:
a gate electrode (gate electrode 10, see fig 1, para 25);
a gate dielectric on the gate electrode (gate dielectric 210, see fig 1, para 26);
a semiconductor region (fig 1, 220, para 26) on the gate dielectric;
one or more dielectric layers over the semiconductor region (fig 1, 230, para 27); and
a conductive contact (conductive contact comprising 30 and 222, see fig 1, para 28) that extends through the one or more dielectric layers and contacts a portion of the semiconductor region (30 and 222 extend through 230 to contact 220, see fig 1) the conductive contact having a width extending from a sidewall of the one or more dielectric layers to an opposite sidewall of the one or more dielectric layers (the contacts comprising 30 and 222 are located between two sidewalls of 230, see fig 1);
wherein the conductive contact comprises a contact semiconductor region (fig 1, 222s, para 28) and a metal fill (12 and 13 can be metal, see fig 1 and 8, para 31, 53 and 55), the contact semiconductor region having a metal oxide semiconductor material (fig 1, 222s, para 28) and at least one dopant element (fig 1, 11, para 34),
wherein the contact semiconductor region is between the metal fill and the portion of the semiconductor region (222s is between 30 and 220, see fig 1) and extends to the sides of the metal fill to be between the metal fill and the sidewall of the one or more dielectric layers and between the metal fill and the opposite sidewall of the one or more dielectric layers (222s is between 30 and the sidewalls of 230, see fig 1), and wherein the contact semiconductor region does not extend beyond the width of the conductive contact (30 and 222 do not extend horizontally beyond the sidewalls of 230, see fig 1).
Regarding claim 3, OHGURO discloses the integrated circuit of claim 1, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc (222 can be IGZO, see para 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over OHGURO (US 20150249156) in view of ISHIZU (US 20150091629).
Regarding claim 2, OHGURO discloses the integrated circuit of claim 1.
OHGURO fails to explicitly disclose a device, wherein the conductive contact is coupled to a metal- insulator-metal (MIM) capacitor.
ISHIZU teaches a device, wherein the conductive contact is coupled to a metal- insulator-metal (MIM) capacitor (s/d electrode 701 can be coupled to MIM capacitor C101, see fig 14A, para 58).
OHGURO and ISHIZU are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the capacitor of ISHIZU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the capacitor of ISHIZU in order to improve processing speed (see ISHIZU para 13).
Claim(s) 4-8, and 10-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over OHGURO (US 20150249156) in view of YAMAZAKI (US 20160284823).
Regarding claim 4, OHGURO discloses the integrated circuit of claim 3.
OHGURO fails to explicitly disclose a device, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one dopant element comprises nitrogen.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements (the semiconductor can be IN:M:Zn in a ratio of 2:1:1.5 meaning that the In concentration is the highest, see para 138), and the at least one dopant element comprises nitrogen (107a can contain nitrogen, see fig 2, para 166).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 5, OHGURO discloses the integrated circuit of claim 3.
OHGURO fails to explicitly disclose a device, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one dopant element comprises oxygen.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements (107a includes 106c which can be In:M:Zn and M can be Ga, so In:Ga:Zn in a ratio of 1:3:2, meaning more Ga than other elements, see fig 2, para 137 and 133), and the at least one dopant element comprises oxygen (the impurities of the semiconductor can be oxygen, see para 96 and the layer can contain oxygen, see para 135).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 6, OHGURO discloses the integrated circuit of claim 1.
OHGURO fails to explicitly disclose a device, wherein the contact semiconductor region comprises a plurality of contact semiconductor layers, each layer of the plurality of contact semiconductor layers having a different material composition.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a plurality of contact semiconductor layers (doped regions 136b and 107a of 106b, see fig 2 and 4, para 271 and 108), each layer of the plurality of contact semiconductor layers having a different material composition (the portion of 106b in 107a comprises an additional dopant, see para 165).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 7, OHGURO discloses the integrated circuit of claim 6.
OHGURO fails to explicitly disclose a device, wherein each layer of the plurality of contact semiconductor layers includes a different dopant profile.
YAMAZAKI teaches a device, wherein each layer of the plurality of contact semiconductor layers includes a different dopant profile (the portion of 106b in 107a comprises an additional dopant, see para 165).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 8, OHGURO discloses the integrated circuit of claim 1.
OHGURO fails to explicitly disclose a device, wherein the conductive contact extends into one or more layers of the semiconductor region.
YAMAZAKI teaches a device, wherein the conductive contact extends into one or more layers of the semiconductor region (107a extends into 106b, see fig 2A).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the contact geometry of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the contact geometry of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 10, OHGURO discloses the integrated circuit of claim 1.
OHGURO fails to explicitly disclose a device a printed circuit board comprising the integrated circuit of claim 1.
YAMAZAKI teaches a printed circuit board comprising the integrated circuit of claim 1 (the device can include a printed wiring board, see para 698).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the printed circuit board of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the printed circuit board of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 11, OHGURO discloses the TFT structure comprising
a gate electrode (gate electrode 10, see fig 1, para 25);
a gate dielectric on the gate electrode (gate dielectric 210, see fig 1, para 26);
a semiconductor region (fig 1, 220, para 26) on the gate dielectric;
one or more dielectric layers over the semiconductor region (fig 1, 230, para 27); and
a conductive contact (conductive contact comprising 30 and 222, see fig 1, para 28) that extends through the one or more dielectric layers and contacts a portion of the semiconductor region (30 and 222 extend through 230 to contact 220, see fig 1) the conductive contact having a width extending from a sidewall of the one or more dielectric layers to an opposite sidewall of the one or more dielectric layers (the contacts comprising 30 and 222 are located between two sidewalls of 230, see fig 1);
wherein the conductive contact comprises a contact semiconductor region (fig 1, 222s, para 28) and a metal fill (12 and 13 can be metal, see fig 1 and 8, para 31, 53 and 55), the contact semiconductor region having a metal oxide semiconductor material (fig 1, 222s, para 28) and at least one dopant element (fig 1, 11, para 34),
wherein the contact semiconductor region is between the metal fill and the portion of the semiconductor region (222s is between 30 and 220, see fig 1) and extends to the sides of the metal fill to be between the metal fill and the sidewall of the one or more dielectric layers and between the metal fill and the opposite sidewall of the one or more dielectric layers (222s is between 30 and the sidewalls of 230, see fig 1), and wherein the contact semiconductor region does not extend beyond the width of the conductive contact (30 and 222 do not extend horizontally beyond the sidewalls of 230, see fig 1).
OHGURO fails to explicitly disclose an integrated circuit, comprising:
a plurality of semiconductor devices;
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; and
a thin film transistor (TFT) structure within one or more interconnect layers of the plurality of stacked interconnect layers.
YAMAZAKI teaches a device an integrated circuit, comprising:
a plurality of semiconductor devices (the transistors 2200 in substrate 450, see fig 27, para 530);
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers (the region of the device above 450 including the insulating layers 464, 466, 489, 493 and 494 and all the elements embedded in those layers which can include as the transistor 2100 the transistor described in embodiment 1, in fig 1-2 , see fig 27, para 538); and
a thin film transistor (TFT) structure (the TFT 2100 which can be the transistor of embodiment 1 as shown in fig 1-2, see fig 27, para 529 and 107) within an interconnect layer of the plurality of stacked interconnect layers (2100 is within 489 and 493, see fig 27).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the TFT inside a plurality of stacked layers of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the TFT inside a plurality of stacked layers of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 12, OHGURO and YAMAZAKI disclose the integrated circuit of claim 11.
OHGURO further discloses a device, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc (222 can be IGZO, see para 30).
Regarding claim 13, OHGURO and YAMAZAKI disclose the integrated circuit of claim 12.
OHGURO fails to explicitly disclose a device, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one dopant element comprises nitrogen.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements (the semiconductor can be IN:M:Zn in a ratio of 2:1:1.5 meaning that the In concentration is the highest, see para 138), and the at least one dopant element comprises nitrogen (the impurities of the semiconductor can be oxygen, see para 96 and the layer can contain oxygen, see para 135).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 14, OHGURO and YAMAZAKI disclose the integrated circuit of claim 12.
OHGURO fails to explicitly disclose a device, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one dopant element comprises oxygen.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements (the semiconductor can be In:M:Zn and M can be Ga, so In:Ga:Zn in a ratio of 1:3:2, meaning more Ga than other elements, see fig 2, para 137 and 133), and the at least one dopant element comprises oxygen (the impurities of the semiconductor can be oxygen, see para 96 and the layer can contain oxygen, see para 135).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 15, OHGURO and YAMAZAKI disclose the integrated circuit of claim 11.
OHGURO fails to explicitly disclose a device, wherein the TFT structure is a first TFT structure of an array of TFT structures within the one or more interconnect layers.
A second embodiment of YAMAZAKI teaches a device, wherein the TFT structure is a first TFT structure of an array of TFT structures within the one or more interconnect layers (the device can have a plurality of transistors 4200 and 4300 within the interconnect layers, see fig 41, para 596).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 16, OHGURO discloses the TFT structure comprising
a gate electrode (gate electrode 10, see fig 1, para 25);
a gate dielectric on the gate electrode (gate dielectric 210, see fig 1, para 26);
a semiconductor region (fig 1, 220, para 26) on the gate dielectric;
one or more dielectric layers over the semiconductor region (fig 1, 230, para 27); and
a conductive contact (conductive contact comprising 30 and 222, see fig 1, para 28) that extends through the one or more dielectric layers and contacts a portion of the semiconductor region (30 and 222 extend through 230 to contact 220, see fig 1) the conductive contact having a width extending from a sidewall of the one or more dielectric layers to an opposite sidewall of the one or more dielectric layers (the contacts comprising 30 and 222 are located between two sidewalls of 230, see fig 1);
wherein the conductive contact comprises a contact semiconductor region (fig 1, 222s, para 28) and a metal fill (12 and 13 can be metal, see fig 1 and 8, para 31, 53 and 55),
wherein the contact semiconductor region is between the metal fill and the portion of the semiconductor region (222s is between 30 and 220, see fig 1) and extends to the sides of the metal fill to be between the metal fill and the sidewall of the one or more dielectric layers and between the metal fill and the opposite sidewall of the one or more dielectric layers (222s is between 30 and the sidewalls of 230, see fig 1), and wherein the contact semiconductor region does not extend beyond the width of the conductive contact (30 and 222 do not extend horizontally beyond the sidewalls of 230, see fig 1).
OHGURO fails to explicitly disclose An integrated circuit, comprising:
a plurality of semiconductor devices;
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; and
a thin film transistor (TFT) structure within an interconnect layer of the plurality of stacked interconnect layers,
the contact semiconductor region having a first dopant profile of at least one first dopant element, and wherein the portion of the semiconductor region beneath the conductive contact has a second dopant profile of at least one second dopant element.
YAMAZAKI teaches An integrated circuit, comprising:
a plurality of semiconductor devices (the transistors 2200 in substrate 450, see fig 27, para 530);
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers (the region of the device above 450 including the insulating layers 464, 466, 489, 493 and 494 and all the elements embedded in those layers which can include as the transistor 2100 the transistor described in embodiment 1, in fig 1-2 , see fig 27, para 538); and
a thin film transistor (TFT) structure (the TFT 2100 which can be the transistor of embodiment 1 as shown in fig 1-2, see fig 27, para 529 and 107) within an interconnect layer of the plurality of stacked interconnect layers (2100 is within 489 and 493, see fig 27),
wherein the conductive contact comprises a contact semiconductor region (107a comprises a portion of semiconductor 106b which is doped with an additional material such as silicon, see fig 2A, para 165) and a metal fill (108a can be Al, see fig 2A, para 213), the contact semiconductor region having a first dopant profile of at least one first dopant element (107a has a doping of a material such as tungsten in addition to the Si doping of 106b, see fig 2A, para 165),
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 17, OHGURO and YAMAZAKI disclose the integrated circuit of claim 16.
OHGURO further discloses, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc (222 can be IGZO, see para 30).
Regarding claim 18, OHGURO and YAMAZAKI disclose the integrated circuit of claim 16.
OHGURO fails to explicitly disclose a device, wherein the first dopant element is the same as the second dopant element.
YAMAZAKI teaches a device, wherein the first dopant element is the same as the second dopant element (both 106b and the portion of 107a which starts as 106b can be doped with Si, see para 150).
OHGURO and YAMAZAKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over OHGURO (US 20150249156) in view of YAMAZAKI (US 20160284823) and further in view of TANAKA (US 20140225105).
Regarding claim 9, OHGURO and YAMAZAKI disclose the integrated circuit of claim 8.
OHGURO and YAMAZAKI fail to explicitly disclose a device, wherein the semiconductor region includes a plurality of compositionally distinct layers, and the conductive contact extends through an uppermost layer of the semiconductor region and lands on or within another layer of the semiconductor region.
TANAKA teaches a device, wherein the semiconductor region includes a plurality of compositionally distinct layers (layers 436a, 436b and 436c, see fig 27A, para 475), and the conductive contact extends through an uppermost layer of the semiconductor region and lands on or within another layer of the semiconductor region (conductive contact 416 extends through 436c to reach 436b, see fig 27d, para 481).
OHGURO, YAMAZAKI and TANAKA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO and YAMAZAKI with the semiconductor layers of TANAKA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO and YAMAZAKI with the semiconductor layers of TANAKA in order to increase the reliability of the transistor (see TANAKA para 411).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over OHGURO (US 20150249156) in view of YAMAZAKI (US 20160284823) and further in view of LUO (US 20200411567).
Regarding claim 19, OHGURO and YAMAZAKI disclose the integrated circuit of claim 16.
OHGURO and YAMAZAKI fail to explicitly disclose a device, wherein the first dopant profile comprises a dopant gradient of the first dopant element across any number of contact semiconductor layers in the contact semiconductor region.
LUO teaches a device, wherein the first dopant profile comprises a dopant gradient of the first dopant element across any number of contact semiconductor layers (semiconductor layers402 and 404 can have a doping gradient across them, see fig 4, para 75) in the contact semiconductor region.
OHGURO, YAMAZAKI and LUO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO and YAMAZAKI with the dopant gradient of LUO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO and YAMAZAKI with the dopant gradient of LUO in order to increase the on-state current (see LUO para 76).
Regarding claim 20, OHGURO and YAMAZAKI disclose the integrated circuit of claim 16.
OHGURO and YAMAZAKI fail to explicitly disclose a device, wherein the second dopant profile comprises a dopant gradient of the second dopant element across any number of semiconductor layers in the semiconductor region.
LUO teaches a device, wherein the second dopant profile comprises a dopant gradient of the second dopant element across any number of semiconductor layers (semiconductor layers 401 and 402 can have a doping gradient across them, see fig 4, para 75) in the semiconductor region.
OHGURO, YAMAZAKI and LUO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OHGURO and YAMAZAKI with the dopant gradient of LUO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OHGURO and YAMAZAKI with the dopant gradient of LUO in order to increase the on-state current (see LUO para 76).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 16 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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