DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ISHII (US 20060042447).
Regarding claim 1, ISHII discloses an integrated circuit, comprising:
a gate electrode (fig 1, 6, para 60);
a gate dielectric (fig 1, 7, para 60) on the gate electrode;
a semiconductor region (fig 1, 8, para 60) on the gate dielectric;
one or more dielectric layers (fig 1, 12, para 62) over the semiconductor region; and
a conductive contact (the contact structure comprising 13 and 15, see fig 1, para 64) that extends through the one or more dielectric layers (13 and 15 extend through 12, see fig 1B, para 64) and contacts a portion of the semiconductor region (13 contacts a part of 8, see fig 1B);
wherein the conductive contact comprises a contact semiconductor region (doped ZnO layer 13, para 63) and a metal fill (metal layer 15, see fig 1, para 64), the contact semiconductor region having a metal oxide semiconductor material and at least one dopant element different from the metal oxide semiconductor material (13 can be n-doped ZnO, see para 63),
wherein the contact semiconductor region is between the metal fill and the portion of the semiconductor region (13 is between 15 and 8, see fig 1B) and extends to the sides of the metal fill to be between the metal fill and the one or more dielectric layers (13 is on the sides of 15 to be between 15 and 12, see fig 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over ISHII (US 20060042447) in view of ISHIZU (US 20150091629).
Regarding claim 2, ISHII discloses the integrated circuit of claim 1.
ISHII fails to explicitly disclose a device, wherein the conductive contact is coupled to a metal- insulator-metal (MIM) capacitor.
ISHIZU teaches a device, wherein the conductive contact is coupled to a metal- insulator-metal (MIM) capacitor (s/d electrode 701 can be coupled to MIM capacitor C101, see fig 14A, para 58).
ISHII and ISHIZU are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the MIM capacitor of ISHIZU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the MIM capacitor of ISHIZU in order to improve processing speed (see ISHIZU para 13).
Claim(s) 3-8 and 10-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over ISHII (US 20060042447) in view of YAMAZAKI (US 20160284823).
Regarding claim 3, ISHII discloses the integrated circuit of claim 1.
ISHII fails to explicitly disclose a device, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc (the semiconductor 106b and 107a contains a region of can be an indium oxide that contains both gallium and zinc, see para 133).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 4, ISHII discloses the integrated circuit of claim 3.
ISHII fails to explicitly disclose a device, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one dopant element comprises nitrogen.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements (the semiconductor can be IN:M:Zn in a ratio of 2:1:1.5 meaning that the In concentration is the highest, see para 138), and the at least one dopant element comprises nitrogen (107a can contain nitrogen, see fig 2, para 166).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 5, ISHII discloses the integrated circuit of claim 3.
ISHII fails to explicitly disclose a device, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one dopant element comprises oxygen.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements (107a includes 106c which can be In:M:Zn and M can be Ga, so In:Ga:Zn in a ratio of 1:3:2, meaning more Ga than other elements, see fig 2, para 137 and 133), and the at least one dopant element comprises oxygen (the impurities of the semiconductor can be oxygen, see para 96 and the layer can contain oxygen, see para 135).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 6, ISHII discloses the integrated circuit of claim 1.
ISHII fails to explicitly disclose a device, wherein the contact semiconductor region comprises a plurality of contact semiconductor layers, each layer of the plurality of contact semiconductor layers having a different material composition.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a plurality of contact semiconductor layers (doped regions 136b and 107a of 106b, see fig 2 and 4, para 271 and 108), each layer of the plurality of contact semiconductor layers having a different material composition (the portion of 106b in 107a comprises an additional dopant, see para 165).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 7, ISHII discloses the integrated circuit of claim 6.
ISHII fails to explicitly disclose a device, wherein each layer of the plurality of contact semiconductor layers includes a different dopant profile.
YAMAZAKI teaches a device, wherein each layer of the plurality of contact semiconductor layers includes a different dopant profile (the portion of 106b in 107a comprises an additional dopant, see para 165).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 8, ISHII discloses the integrated circuit of claim 1.
ISHII fails to explicitly disclose a device, wherein the conductive contact extends into one or more layers of the semiconductor region.
YAMAZAKI teaches a device, wherein the conductive contact extends into one or more layers of the semiconductor region (107a extends into 106b, see fig 2A).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 10, ISHII discloses the integrated circuit of claim 1.
ISHII fails to explicitly disclose a printed circuit board comprising the integrated circuit.
YAMAZAKI teaches a printed circuit board comprising the integrated circuit of claim 1 (the device can include a printed wiring board, see para 698).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the circuit board of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the circuit board of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 11, ISHII discloses a thin film transistor (TFT) structure (the TFT comprising at least 6, 7, 8, 13 and 15, see fig 1, para 60-65) within one or more interconnect layers of the plurality of stacked interconnect layers (the TFT is within 7, 12 and 17, see fig 1B), the TFT structure comprising
a gate electrode (fig 1, 6, para 60);
a gate dielectric (fig 1, 7, para 60) on the gate electrode;
a semiconductor region (fig 1, 8, para 60) on the gate dielectric;
one or more dielectric layers (fig 1, 12, para 62) over the semiconductor region; and
a conductive contact (the contact structure comprising 13 and 15, see fig 1, para 64) that extends through the one or more dielectric layers (13 and 15 extend through 12, see fig 1B, para 64) and contacts a portion of the semiconductor region (13 contacts a part of 8, see fig 1B);
wherein the conductive contact comprises a contact semiconductor region (doped ZnO layer 13, para 63) and a metal fill (metal layer 15, see fig 1, para 64), the contact semiconductor region having a metal oxide semiconductor material and at least one dopant element different from the metal oxide semiconductor material (13 can be n-doped ZnO, see para 63),
wherein the contact semiconductor region is between the metal fill and the portion of the semiconductor region (13 is between 15 and 8, see fig 1B) and extends to the sides of the metal fill to be between the metal fill and the one or more dielectric layers (13 is on the sides of 15 to be between 15 and 12, see fig 1B).
ISHII fails to explicitly disclose an integrated circuit, comprising:
a plurality of semiconductor devices;
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers.
YAMAZAKI teaches an integrated circuit, comprising:
a plurality of semiconductor devices (the transistors 2200 in substrate 450, see fig 27, para 530);
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers (the region of the device above 450 including the insulating layers 464, 466, 489, 493 and 494 and all the elements embedded in those layers which can include as the transistor 2100 the transistor described in embodiment 1, in fig 1-2 , see fig 27, para 538).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the array of TFTs in an interconnect region over a substrate with semiconductor devices of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the array of TFTs in an interconnect region over a substrate with semiconductor devices of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 12, ISHII discloses the integrated circuit of claim 11.
ISHII fails to explicitly disclose a device, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc (the semiconductor 106b and 107a contains a region of can be an indium oxide that contains both gallium and zinc, see para 133).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 13, ISHII discloses the integrated circuit of claim 12.
ISHII fails to explicitly disclose a device, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one dopant element comprises nitrogen.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements (the semiconductor can be IN:M:Zn in a ratio of 2:1:1.5 meaning that the In concentration is the highest, see para 138), and the at least one dopant element comprises nitrogen (the impurities of the semiconductor can be oxygen, see para 96 and the layer can contain oxygen, see para 135).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 14, ISHII discloses the integrated circuit of claim 12.
ISHII fails to explicitly disclose a device, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one dopant element comprises oxygen.
YAMAZAKI teaches a device, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements (the semiconductor can be In:M:Zn and M can be Ga, so In:Ga:Zn in a ratio of 1:3:2, meaning more Ga than other elements, see fig 2, para 137 and 133), and the at least one dopant element comprises oxygen (the impurities of the semiconductor can be oxygen, see para 96 and the layer can contain oxygen, see para 135).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 15, ISHII and YAMAZAKI disclose the integrated circuit of claim 11.
ISHII further discloses a device, wherein the TFT structure is a first TFT structure of an array of TFT structures within the one or more interconnect layers (there is a matrix array of TFT devices 3, see fig 1, para 59).
Regarding claim 16, ISHII discloses a thin film transistor (TFT) structure (the TFT comprising at least 6, 7, 8, 13 and 15, see fig 1, para 60-65) within one or more interconnect layers of the plurality of stacked interconnect layers (the TFT is within 7, 12 and 17, see fig 1B), the TFT structure comprising
a gate electrode (fig 1, 6, para 60);
a gate dielectric (fig 1, 7, para 60) on the gate electrode;
a semiconductor region (fig 1, 8, para 60) on the gate dielectric;
one or more dielectric layers (fig 1, 12, para 62) over the semiconductor region; and
a conductive contact (the contact structure comprising 13 and 15, see fig 1, para 64) that extends through the one or more dielectric layers (13 and 15 extend through 12, see fig 1B, para 64) and contacts a portion of the semiconductor region (13 contacts a part of 8, see fig 1B);
wherein the conductive contact comprises a contact semiconductor region (doped ZnO layer 13, para 63) and a metal fill (metal layer 15, see fig 1, para 64),
wherein the contact semiconductor region is between the metal fill and the portion of the semiconductor region (13 is between 15 and 8, see fig 1B) and extends to the sides of the metal fill to be between the metal fill and the one or more dielectric layers (13 is on the sides of 15 to be between 15 and 12, see fig 1B).
ISHII fails to explicitly disclose an integrated circuit, comprising:
a plurality of semiconductor devices;
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; and
the contact semiconductor region having a first dopant profile of at least one first dopant element, and wherein the portion of the semiconductor region beneath the conductive contact has a second dopant profile of at least one second dopant element.
YAMAZAKI teaches an integrated circuit, comprising:
a plurality of semiconductor devices (the transistors 2200 in substrate 450, see fig 27, para 530);
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers (the region of the device above 450 including the insulating layers 464, 466, 489, 493 and 494 and all the elements embedded in those layers which can include as the transistor 2100 the transistor described in embodiment 1, in fig 1-2 , see fig 27, para 538); and
wherein the conductive contact comprises a contact semiconductor region (107a comprises a portion of semiconductor 106b which is doped with an additional material such as silicon, see fig 2A, para 165) and a metal fill (108a can be Al, see fig 2A, para 213), the contact semiconductor region having a first dopant profile of at least one first dopant element (107a has a doping of a material such as tungsten in addition to the Si doping of 106b, see fig 2A, para 165).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the array of TFTs in an interconnect region over a substrate with semiconductor devices of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the array of TFTs in an interconnect region over a substrate with semiconductor devices of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 17, ISHII discloses the integrated circuit of claim 16.
ISHII fails to explicitly disclose a device, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc.
YAMAZAKI teaches a device wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc (the semiconductor 106b and 107a contains a region of can be an indium oxide that contains both gallium and zinc, see para 133).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Regarding claim 18, ISHII discloses the integrated circuit of claim 16.
ISHII fails to explicitly disclose a device, wherein the first dopant element is the same as the second dopant element.
YAMAZAKI teaches a device, wherein the first dopant element is the same as the second dopant element (both 106b and the portion of 107a which starts as 106b can be doped with Si, see para 150).
ISHII and YAMAZAKI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the semiconductor material of YAMAZAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the semiconductor material of YAMAZAKI in order to increase the on-state current (see YAMAZAKI para 145).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over ISHII (US 20060042447) in view of TANAKA (US 20140225105).
Regarding claim 9, ISHII discloses the integrated circuit of claim 8.
ISHII fails to explicitly disclose a device, wherein the semiconductor region includes a plurality of compositionally distinct layers, and the conductive contact extends through an uppermost layer of the semiconductor region and lands on or within another layer of the semiconductor region.
TANAKA teaches a device, wherein the semiconductor region includes a plurality of compositionally distinct layers (layers 436a, 436b and 436c, see fig 27A, para 475), and the conductive contact extends through an uppermost layer of the semiconductor region and lands on or within another layer of the semiconductor region (conductive contact 416 extends through 436c to reach 436b, see fig 27d, para 481).
ISHII and TANAKA are analogous art because they both are directed towards TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the layers of TANAKA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the layers of TANAKA in order to increase the reliability of the transistor (see TANAKA para 411).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ISHII (US 20060042447) in view of LUO (US 20200411567).
Regarding claim 19, ISHII and YAMAZAKI discloses the integrated circuit of claim 16.
ISHII fails to explicitly disclose a device, wherein the first dopant profile comprises a dopant gradient of the first dopant element across any number of contact semiconductor layers in the contact semiconductor region.
LUO teaches a device, wherein the first dopant profile comprises a dopant gradient of the first dopant element across any number of contact semiconductor layers (semiconductor layers402 and 404 can have a doping gradient across them, see fig 4, para 75) in the contact semiconductor region.
ISHII And LUO are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the gradient doping of LUO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the gradient doping of LUO in order to increase the on-state current (see LUO para 76).
Regarding claim 20, ISHII and YAMAZAKI discloses the integrated circuit of claim 16.
ISHII fails to explicitly disclose a device, wherein the second dopant profile comprises a dopant gradient of the second dopant element across any number of semiconductor layers in the semiconductor region.
LUO teaches a device, wherein the second dopant profile comprises a dopant gradient of the second dopant element across any number of semiconductor layers (semiconductor layers 401 and 402 can have a doping gradient across them, see fig 4, para 75) in the semiconductor region.
ISHII And LUO are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of ISHII with the gradient doping of LUO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of ISHII with the gradient doping of LUO in order to increase the on-state current (see LUO para 76).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811