DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed May 5, 2025 have been fully considered but they are not persuasive.
While, “surface mount device" and “surface mount technology” are known terms in the art that has specific elements, the "surface mount package" is not as well defined and the examiner’s interpretation is reasonable for a surface mount package. Tang in Fig 4B teaches “a second layer may not include a dielectric substrate, and may include surface-mount components rather than embedded components." Reference Fig 1B shows a structure with a device 140 which is mounted and embedded in a dielectric 128 and bonded to carrier 102 which is equivalent to applicant’s "surface mount package 114 comprises a package body 116 with one or more semiconductor dies 115 embedded within the package body 116." Ultimately, there is no structural difference between the Applicant's surface mount packages and Tate's embedded components.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Tang et al. (US 2022/0037280).
Regarding claim 1, Tang teaches a semiconductor assembly, comprising:
a carrier (102, base layer) comprising a dielectric substrate (118) and a plurality of contact pads (120) disposed on an upper surface of the carrier (see Figs. 1B and 4B);
first and second surface mount packages (104, 106) mounted on the carrier (102);
first and second discrete inductors (170) respectively mounted over the first and second surface mount packages (see Fig. 1A),
wherein the first and second surface mount packages each comprise lower surface terminals (142, 143) that face and electrically connect with the contact pads from the carrier,
wherein the first and second surface mount packages each comprise an upper side that faces away from the carrier (Fig. 1A-1B), and
wherein the first and second discrete inductors are respectively thermally coupled to the upper sides of the first and second surface mount packages ([0019]-[0020]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. as applied to claim 1 above, further in view of Herbsommer et al. (US 2014/0245598).
Regarding claim 2, Tang discloses the semiconductor assembly of claim 1 as described above, further including first and second leads (174)
However, Tang does not explicitly teach wherein the first and second discrete inductors each comprise an outer body of electrically insulating material, a metal element arranged within the outer body, and that the first and second leads are exposed from the outer body, wherein the outer body of each of the first and second discrete inductors comprises a lower side that faces the carrier and an upper side that faces away from the carrier, and wherein the metal element of each of the first and second discrete inductors comprises a heat radiating block that is exposed at the upper side of the outer body of the respective first and second discrete inductors.
Herbsommer teaches, in Fig 2, an outer body (111, [0024]) of electrically insulating material, a metal element (113 and the not shown metal coil, [0023]) arranged within the outer body, and that first and second leads (112a and 112b, [0023]) are exposed from the outer body, wherein the outer body comprises a lower side (not numbered but clearly shown in Figure) that faces the carrier (120, [0023]) and an upper side (not numbered but clearly shown in Figure) that faces away from the carrier, and wherein the metal element comprises a heat radiating block (113, [0033]) that is exposed at the upper side of the outer body to have the inductor “double as an effective heat sink” ([0010]) to “enhance the converter efficiency” ([0011]).
It would have been obvious to the ordinary artisan at the time of filing to combine the metal element, leads, heat radiating block, and their respective arrangements of Herbsommer to each of the first and second discrete inductors of Tang, because the result would be to have them double as effective heat sinks to enhance the converter efficiency.
Regarding claim 3, Tang in view of Herbsommer teaches claim 2 as described above and further teaches in Fig 1B of Tang, wherein the upper sides of the first and second surface mount packages each comprise one or more exposed metal pads (162, 122, and 152, [0019, 0032, 0035]), and herein the one or more exposed metal pads of the first and second surface mount packages are respectively thermally coupled to the metal element of the first and second discrete inductors.
Regarding claim 4, Tang in view Herbsommer teaches claim 3 as described above and in Tang Fig 1B teaches wherein the one or more exposed metal pads of the first and second surface mount packages comprise a respective first output pad of each of the first and second surface mount packages (162, [0018-0019]), and wherein the first leads of the first and second discrete inductors are respectively electrically connected to the respective first output pads of the first and second surface mount packages.
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Regarding to claim 5, Tang in view Herbsommer teaches claim 4 as described above and in Tang’s Fig 1B (annotated and reproduced here), wherein the second leads (2nd lead, see annotated Figure 1B above) of the first and second discrete inductors are respectively electrically connected (electrically connected by 152 and 122) to one of the contact pads (one of the contact pads, see annotated Figure 1B above) disposed on the upper surface of the carrier.
Regarding claim 6, Tang in view Herbsommer teaches claim 4 as described above, and in Tang, Fig 1B (annotated and reproduced here), wherein the one or more exposed metal pads of the first and second surface mount packages comprise a dummy pad (152 with 160), wherein the first leads (1st lead, see annotated Figure 1B above) of the first and second discrete inductors are respectively soldered to the respective first output pads ([0019]) of the first and second surface mount packages, and wherein the second leads of the first and second discrete inductors are respectively soldered to the dummy pads ([0019]) of the first and second surface mount packages.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. in view of Herbsommer et al. (US 2014/0245598) as applied to claim 2 above, and in further view of Cho et al. (US 9640474 B1, hereafter Cho I).
Regarding claim 9, Tang and Herbsommer teach most of the limitations of this claim, as set forth above with regard to claim 2.
However, Tang and Herbsommer do not explicitly teach wherein the first and second discrete inductors are respectively thermally coupled to the upper sides of the first and second surface mount packages by an electrically isolating material arranged between the upper sides of the first and second surface mount packages and exposed parts of the metal element that respectively connect with the first and second leads of the first and second discrete inductors.
Cho I teaches, in Fig 2j, wherein a discrete inductor (258, col. 8 lines 17-43) is respectively thermally coupled to the upper side (213 and 215, col. 8 lines 20-35) of a surface mount package (202, col. 8 lines 10-25) by an electrically isolating material (218 and 230, col. 7 lines 9-34, col. 8 lines 30-43) arranged between the upper side of the surface mount package and exposed parts of the metal element (the metal element,113 and the not shown metal coil, of Herbsommer akin to the body 258 of Cho I) that respectively connect with the first and second leads (226a/b of Cho I; akin to 112a/b of Herbsommer) of the surface mount package to “electrically insulate” (col. 7 lines 9-34) the surface mount package from surrounding conductive elements “enabling wide connection interfaces and easy connectivity to electrical connectors or routing structures” (col. 8 lines 30-67 and col. 9 lines 1-9).
It would have been obvious to the ordinary artisan at the time of filing to combine the upper side coupling of Cho I with the structure of Tang in view of Herbsommer, because the result would electrically insulate elements while enabling easy and reliable electrical connectivity.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. as applied claim 1 above, and in further view of Cho et al. (US 2018/0054119, hereafter Cho II).
Regarding claim 10, Tang teaches most of the limitations of this claim, as set forth above with regard to claim 1.
However, Tang does not explicitly teach wherein the first and second surface mount packages each comprise a power semiconductor die embedded within a laminate package body.
Cho II teaches, in Fig 3, a power semiconductor die (46A, [0040]) embedded within a laminate package body ([0040]) to construct “a device with a substantially co-planar surface” ([0057]) “to easily mount to a PCB” ([0061]).
It would have been obvious to the ordinary artisan at the time of filing to combine the power semiconductor embedded within a laminate package body of Cho II to each of the first and second mount packages of Tang to construct a device with substantially coplanar surfaces which result in easier mounting to a PCB which is advantageous and within the purview of one having ordinary skill in the art.
Regarding claim 11, Tang teaches most of the limitations of this claim, as set forth above with regard to claim 1.
However, Tang does not explicitly teach wherein the first and second surface mount packages each comprise a power semiconductor die embedded within an electrically insulating mold compound.
Cho II teaches, in Fig 2, a power semiconductor die (26A, [0030]) embedded within an
electrically insulating mold compound ([0027] of Tang) to construct “a device with a substantially
co-planar surface” ([0057]) “to easily mount to a PCB” ([0061]).
It would have been obvious to the ordinary artisan at the time of filing to combine the power semiconductor of Cho II and embedded it within the electrically insulating mold compound of the first and second surface mount packages of Tang to construct a device with substantially co-planar surfaces which result in easier mounting to a PCB which is advantageous and within the purview of one having ordinary skill in the art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630.
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/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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