DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/02/2026 have been fully considered but they are not persuasive. Regarding Claims 33 and 36, Applicant argues that the office action relies Chen et al. (US 2020/0006266 A1, hereinafter Chen ‘266) for features of device 100 to bond it to device 200 which is a die, not a redistribution substrate as cited in the claims. Examiner’s respectfully disagrees. As presented below the rejection of Claims 33 and 36 do not use the devices of Chen ‘266, rather the rejection uses the teaching of Chen ‘266 of pad spacing to facilitate direct bonding of bond pads. Applicant further argues that Chen ‘266 does not teach pad intervals that are less than their widths. Examiner again respectfully disagrees. As presented in the rejections of the claims below the Examiner is not relying on Chen ‘266 for the pad and pad spacing dimensions. The rejection relies on the teachings of Chen et al. (2020/0395339 !a, hereinafter Chen ‘339) for dimensions of pads for bonding and on Chen ‘266 for interval spacing between bond pads. Combining these teachings to have pad spacings less than pad widths would be obvious to a person of ordinary skill in the art as described below. Thirdly Applicant argues that the Office action does not support a motivation to combine the prior art references of claims 33 and 36. Examiner again respectfully disagrees. As described in the rejection below, the ordinary artisan would have been motivated to modify, therefore, Wu ‘474 as modified by Chen ‘339 in the manner set forth above, at least, because as taught in by Chen ‘266 (Para [0072]) using the taught constant pitch between bond pads provides an increased bonding are that can reduce device contact resistance due to misalignment or warping that may occur during bonding.
Applicant’s arguments with respect to claims 26-45 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Regarding Claim 26, Applicants Arguments of 01/02/2026 have shown support for the limitation “fourth maximum width” of upper coupling pads (233). Examiner withdraws 35 USC 112(a) rejection of Claim 26 of Non Final Office Action mailed on 10/02/2025.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding Claim 26, Applicants Arguments of 01/02/2026 have clarified support for the limitation “fourth maximum width” of upper coupling pads (233). Examiner withdraws 35 USC 112(b) rejection of Claim 26 of Non Final Office Action mailed on 10/02/2025.
Claim 41 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 41 recites the broad recitation “wherein the first pad part in each of the plurality of upper coupling pads provides” , and the claim also recites “first pad parts of the plurality of upper coupling pads” which is the narrower statement of the range/limitation. Further claim 41 the broad recitation “wherein the second pad part in each of the plurality of redistribution chip pads provides second pad parts of the plurality of redistribution chip pads provides” , and the claim also recites “second pad parts of the plurality of redistribution chip pads” which is the narrower statement of the range/limitation. The claim is considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 26-32 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2018/0342474 A1, hereinafter Wu ‘474) in view of Chen et al. (US 2020/0395339 A1, hereinafter Chen ‘339), in view of the following arguments.
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With respect to Claim 26 Wu ‘474 discloses a semiconductor package (Fig 1-15), comprising:
a lower redistribution substrate (28, Fig 2, Para [0019]) including a first base dielectric layer (38, Fig 2 and 3, Para [0019]) and a plurality of (disclosed in Fig 2) first upper coupling pads (pads 36, Fig 3, Para [0019]) in the first base dielectric layer (38);
a first semiconductor chip (42, Fig 5, Para [0029]) on the lower redistribution substrate (28), the first semiconductor chip (42) including a first semiconductor substrate (43, Fig 5, Para [0029]), first chip pads (first chip pads of 42 disclosed in Para [0030] but are not shown in Figures, hereinafter FCP), a first protection layer (dielectric layer of 44 in contact with 48, Figs 5 and 7, Para [0029]), a first redistribution dielectric layer (48, Fig 5, Para [0031]), and a plurality of (disclosed in Figs 5 and 7) first redistribution chip pads (pads 46, Fig 5, Para [0031]);
an upper redistribution substrate (60, Fig 9, Para [0037]) including a second base dielectric layer (upper dielectric layer 62, Fig 9, Para [0037]) and a plurality of (disclosed in Fig 9) second upper coupling pads (pads 64, Fig 9, Para [0037]) in the second base dielectric layer (upper dielectric layer 62)(64 in upper dielectric layer 62 is shown in Fig 9);
a molding layer (58, Fig 9, Para [0035]) between (disclosed in Fig 9) the lower redistribution substrate (28) and the upper redistribution substrate (60), the molding layer (58) covering (disclosed in Fig 9 and Para [0035]) the first semiconductor chip (42);
metal pillars (40, Fig 9, Para [0027]) disposed around the first semiconductor chip (42), the metal pillars (40) connecting (disclosed in Fig 9) the lower redistribution substrate (28) to the upper redistribution substrate (60); and
a second semiconductor chip (74, Fig 10, Para [0044]) on the upper redistribution substrate (60); and a plurality of connection terminals (78, Fig 10, Para [0047]) connected between the second semiconductor chip (74) and top surfaces (tops of 64 as shown in Fig 10) of the plurality of second upper coupling pads (64)(Fig 10 and Para [0052] discloses top of 64 connected to terminals 78),
wherein a top surface (top of 38) of the first base dielectric layer (38) is in direct contact (Fig 5 and Para [0034] disclose top of 38 in direct contact with top of 48) with a top surface (top of 48) of the first redistribution dielectric layer (48),
top surfaces (tops of 46) of the plurality of first redistribution chip pads (46) are in direct contact (Fig 5 and Para [0034] disclose top of 46 in direct contact with top of 36) with top surfaces (tops of 36) of the plurality of first upper coupling pads (36),
each of the top surfaces (tops of 46) of the plurality of first redistribution chip pads (46) has a first width (first width of 46 shown in annotated Fig 7 of Wu ‘474, hereinafter FMW),
each of the top surfaces (tops of 36) of the plurality of first upper coupling pads (36) has a second width (second width of 36 shown in annotated Fig 7 of Wu ‘474, hereinafter SMW), and
each of the top surfaces (tops of 64) of the plurality of second upper coupling pads (64) has a fourth width (fourth width of 64 shown in annotated Fig 9 of Wu ‘474, hereinafter 4MW)
the molding layer (58) covers a top surface (top of 42) of the first semiconductor chip (42)(Fig 9 and Para [0035] disclose 58 higher than top of 42), and
the molding layer (58) extends between the first semiconductor chip (42) and the upper redistribution substrate (60)(Fig 9 and Para [0037] disclose 58 extends between 42 and 60).
But Wu ‘474 fails to explicitly disclose a first redistribution chip pads has a first maximum width, upper coupling pads has a second maximum width second and second upper coupling pads has a fourth maximum width fourth width.
Nevertheless, in a related endeavor (Fig 3 of Chen ‘339), Chen ‘339 teaches a pad has a maximum width (Para [0026] of Chen ‘339 teaches a maximum top width of bond via 120 as 10µm).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chen ‘339’s maximum pad width into Wu ‘474’s device. Wu ‘474 teaches a semiconductor package comprising a die that is directly bonded to a substrate but Wu ‘474 teaches the direct bond process but is Wu ‘474 does not provide details with regards to the dimensions of the pads to be bonded. Chen ‘339 teaches a direct bond process for a die to a substrate (Para 0029 of Chen ‘339 teaches that 101 may be a wafer) and provides details on pad widths and spacing; Chen ‘339 presents (Para [0026]) a width range for the direct bond connections. Therefore, the ordinary artisan would have been motivated to modify Wu ‘474 in the manner set forth above, at least, because the widths of the direct bond connections as taught by Chen ‘339 in Para [0051] these pad dimensions can support a process which simplify the bonding process and therefore lead to reduced costs.
As incorporated, the maximum pad widths of redistribution chip pads taught by Chen ‘339 would be used as the maximum pad width of first redistribution pads (46) of Wu ‘474 and the maximum pad widths of upper coupling pads as taught by Chen ‘339 would be used as the maximum width of upper coupling pads (36 and 64) of Wu’474.
With respect to Claim 27 Wu ‘474 as modified by Chen ‘339 discloses all limitation of the semiconductor package of claim 26, and Wu ‘474 further discloses wherein the molding layer (58) has a bottom surface (bottom of 58 as shown in Fig 7) in contact with the top surface (top of 38 as shown in Fig 7) of the first base dielectric layer (38, Note that Fig 7 does not number what appears to be the top layer of the redistribution substrate but Fig 3 and Para [0025] disclose 38 as top layer of lower redistribution substrate) of the lower redistribution substrate (28).
With respect to Claim 28 Wu ‘474 as modified by Chen ‘339 discloses all limitation of the semiconductor package of claim 26, and Wu ‘474 discloses further wherein the metal pillars (40) contacts first ones (rightmost pad 36 as shown in Fig 4, Para [0027] discloses 40 contacts 36) of the plurality of first upper coupling pads (pads 36) of the lower redistribution substrate (28).
With respect to Claim 29 Wu ‘474 as modified by Chen ‘339 discloses all limitation of the semiconductor package of claim 26, and Wu ‘474 discloses further wherein a sidewall (right sidewall of 58 as shown in Fig 6) of the molding layer (58) is vertically aligned (disclosed in Fig 6) with sidewalls (right sidewall of 28 and right sidewall of 60 as shown in Fig 10) of the lower redistribution substrate (28) and the upper redistribution substrate (60).
With respect to Claim 30 Wu ‘474 as modified by Chen ‘339 discloses all limitation of the semiconductor package of claim 26, and Wu ‘474 further discloses wherein the first base dielectric layer (38) includes a first photosensitive polymer layer (Para [0021] discloses 38 as a photosensitive polymer layer, hereinafter 1PPL),
the first redistribution dielectric layer (48) includes a second photosensitive polymer layer (Para [0031] discloses 48 as a photosensitive polymer layer, hereinafter 2PPL), and
a top surface (top of 1PPL) of the first photosensitive polymer layer (1PPL) is in direct contact (Para [0034] discloses 38 in direct contact with 48) with a top surface (top of 2PPL) of the second photosensitive polymer layer (2PPL).
With respect to Claim 31 Wu ‘474 as modified by Chen ‘339 discloses all limitation of the semiconductor package of claim 26, and Wu ‘474 further discloses wherein the first redistribution dielectric layer (48) and the first base dielectric layer (upper dielectric layer 62) include a same dielectric material (Para [0031] discloses 48 as BCB and Para [0037] discloses 62 as BCB), and the plurality of first redistribution chip pads (pads 46) and the plurality of first upper coupling pads (pads 36) include a same metallic material (Para [0024] discloses 36 as copper and Para [0030] disclose 46 as copper).
With respect to Claim 32 Wu ‘474 as modified by Chen ‘339 discloses all limitation of the semiconductor package of claim 26, and Wu ‘474 further discloses wherein the molding layer (58) covers the first semiconductor chip (42), and a sidewall (right sidewall of 58 as shown in Fig 6) of the molding layer (58) is aligned with sidewalls (right sidewall of 28 and right sidewall of 60 as shown in Fig 10) of the lower redistribution substrate (28) and the upper redistribution substrate (60).
Claims 33, 36 and 39 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Wu ‘474 in view of Chen ‘339 and in further view of Chen et al. (US 2020/0006266 A1, hereinafter Chen ‘266), in view of the following arguments.
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With respect to Claim 33 Wu ‘474 as modified by Chen ‘339 discloses all limitations of the semiconductor package of claim 26, but Wu ‘474 as modified by Chen ‘339 fails to explicitly disclose wherein an interval between adjacent ones of the plurality of first upper coupling pads is less than the first maximum width, and an interval between adjacent ones of the plurality of first redistribution chip pads is less than the first maximum width.
Nevertheless, in a related endeavor, (Fig 1A of Chen ‘266), Chen ‘266 teaches wherein an interval between adjacent ones of the plurality of first redistribution chip pads (Fig 1A and Para [0015] of Chen ‘266 teaches a pad pitch of 5µm).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use wherein an interval between adjacent ones of the plurality of first redistribution chip pads as taught by Chen ‘266 in the semiconductor package of Wu ‘474 as modified by Chen ‘339. Wu ‘474 as modified by Chen ‘339 discloses a semiconductor device comprising a die that is direct bonded to a substrate and further teaches pad widths and Wu ‘474 as modified by Chen ‘339 is open to the interval spacing between those pads. Chen ‘266 also teaches a direct bond process and provides details on interval spacing between bond pads. The ordinary artisan would have been motivated to modify, therefore, Wu ‘474 as modified by Chen ‘339 in the manner set forth above, at least, because as taught in by Chen ‘266 (Para [0072]) using the taught constant pitch between bond pads provides an increased bonding are that can reduce device contact resistance due to misalignment or warping that may occur during bonding.
As incorporated the pad spacing of Chen ‘266 would be used as the interval spacing of first upper coupling pads (36) and the first redistribution chip pads (pads 46) of Wu ‘474 as modified by Chen ‘339.
Therefore, the combination of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 further discloses wherein an interval (5µm as taught by Chen ‘266) between adjacent ones of the plurality of first redistribution chip pads (pads 46 of Wu ‘474) is less than the first maximum width (10 µm of Chen ‘339).
With respect to Claim 36 Wu ‘474 discloses a semiconductor package (Fig 1-15), comprising:
a redistribution substrate (28, Fig 2, Para [0019]) including a base dielectric layer (38, Fig 2 and 3, Para [0019]) and a plurality (disclosed in Fig 2) of upper coupling pads (pads 36, Fig 3, Para [0019]) in the base dielectric layer (38);
a semiconductor chip (42, Fig 5, Para [0029]) on the redistribution substrate (28), the semiconductor chip (42) including a semiconductor substrate (43, Fig 5, Para [0029]), a plurality of chip pads (chip pads of 42 disclosed in Para [0030] but are not shown in Figures), a protection layer (dielectric layer of 44 in contact with 48, Fig 5, Para [0029]) covering the plurality of chip pads (chip pads disclosed in Para [0030] but are not shown in Figures)(Fig 7 discloses dielectrics of 44 cover bottom of die 42), a redistribution dielectric layer (48, Fig 5, Para [0031]) on the protection layer (dielectric layer of 44 in contact with 48), and a plurality (disclosed in Figs 5 and 7) of redistribution chip pads (pads 46, Fig 5, Para [0031]) that penetrate the redistribution dielectric layer (48)(46 penetrating 48 disclosed in Fig 7 and Para [0031]) and the protection layer (dielectric layer of 44 in contact with 48) and are connected to the plurality of chip pads (chip pads of 42 disclosed in Para [0030] but are not shown in Figures) (Para [0030] discloses that 46 are die pillars are mechanically and electrically connected to 42 chip pads and the protection layer is on layer 48 as described above, therefore 46 penetrates the protection layer (dielectric layer of 44) and are connected to chip pads of 42); and
a molding layer (58, Fig 9, Para [0035]) covering a top surface (top of 42) of the semiconductor chip (42)(Fig 9 and Para [0035] disclose 58 higher than top of 42); and
wherein a top surface (top of 38) of the base dielectric layer (38) is in direct contact (Fig 5 and Para [0034] disclose top of 38 in direct contact with top of 48) with a top surface (top of 48) of the redistribution dielectric layer (48),
top surfaces (tops of 46) of the plurality of redistribution chip pads (pads 46) are in direct contact (Fig 5 and Para [0034] disclose top of 46 in direct contact with top of 36) with top surfaces (tops of 36) of the plurality of upper coupling pads (pads 36), respectively,
each of the top surfaces (tops of 46) of the plurality of redistribution chip pads (pads 46) has a first width (first width of 46 shown in annotated Fig 7),
each of the top surfaces (tops of 36) of the plurality of upper coupling pads (pads 36) has a second width (second width of 36 shown in annotated Fig 7),
the base dielectric layer (38) and the redistribution dielectric layer (48) comprise a same photosensitive polymer (Para [0021] discloses 38 as BCB and Para [0031] discloses 48 as BCB),
But Wu ‘474 fails to explicitly disclose each of the top surfaces (top of pads 46 of Wu ‘474) of the plurality of redistribution chip pads (pads 46 of Wu ‘474) has a first maximum width, each of the top surfaces (top of pads 36) of the plurality of upper coupling pads (pads 36) has a second maximum width.
Nevertheless, in a related endeavor (Fig 3 of Chen ‘339), Chen ‘339 teaches a pad has a maximum width (Para [0026] of Chen ‘339 teaches a maximum top width of bond via 120 as 10µm).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chen ‘339’s maximum pad width into Wu ‘474’s device. Wu ‘474 teaches a semiconductor package comprising a die that is directly bonded to a substrate but Wu ‘474 teaches the direct bond process but is Wu ‘474 does not provide details with regards to the dimensions of the pads to be bonded. Chen ‘339 teaches a direct bond process for a die to a substrate (Para 0029 of Chen ‘339 teaches that 101 may be a wafer) and provides details on pad widths and spacing; Chen ‘339 presents (Para [0026]) a width range for the direct bond connections. Therefore, the ordinary artisan would have been motivated to modify Wu ‘474 in the manner set forth above, at least, because the widths of the direct bond connections as taught by Chen ‘339 in Para [0051] these pad dimensions can support a process which simplify the bonding process and therefore lead to reduced costs.
As incorporated, the maximum bonding connection width taught by Chen ‘339 would be used as the maximum width in redistribution chip pads (pads 46 of Wu ‘474) and upper coupling pads (pads 36) of Wu ‘474.
Wu ‘474 as modified by Chen ‘339 fails to explicitly disclose a first interval adjacent ones of the plurality of redistribution chip pads is less than the first maximum width, and a second interval adjacent ones of the plurality of upper coupling pads is less than the second maximum width.
Nevertheless, in a related endeavor, (Fig 1A of Chen ‘266), Chen ‘266 teaches wherein an interval between adjacent ones of the plurality of bonding pads (Fig 1A and Para [0015] of Chen ‘266 teaches a pad pitch of 5µm).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use wherein an interval between adjacent ones of the plurality of bonding pads as taught by Chen ‘266 in the semiconductor package of Wu ‘474 as modified by Chen ‘339. Wu ‘474 as modified by Chen ‘339 discloses a semiconductor device comprising a die that is direct bonded to a substrate and further teaches pad widths and Wu ‘474 as modified by Chen ‘339 is open to the interval spacing between those pads. Chen ‘266 also teaches a direct bond process and provides details on interval spacing between bond pads. The ordinary artisan would have been motivated to modify, therefore, Wu ‘474 as modified by Chen ‘339 in the manner set forth above, at least, because as taught in by Chen ‘266 (Para [0072]) using the taught constant pitch between bond pads provides an increased bonding are that can reduce device contact resistance due to misalignment or warping that may occur during bonding.
As incorporated the pad spacing of Chen ‘266 would be used as the interval spacing of the redistribution chip pads (pads 46) and upper coupling pads (pads 36) of Wu ‘474 as modified by Chen ‘339.
Therefore the combination of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 further discloses wherein an interval (5µm as taught by Chen ‘266) between adjacent ones of the plurality of redistribution chip pads (pads 46 of Wu ‘474) is less than the first maximum width (10 µm of Chen ‘339), and
a second interval (5µm as taught by Chen ‘266) adjacent ones of the plurality of upper coupling pads (pads 36 of Wu ‘474) is less than the second maximum width (10 µm of Chen ‘339).
With respect to Claim 39 Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 discloses all limitations of the semiconductor package of claim 36, and Wu ‘474 discloses further comprising: a molding layer (58, Fig 9, Para [0035]) on the redistribution substrate (28)(58 on 28 disclosed in Fig 9), wherein the molding layer (58) covers the semiconductor chip (42)(58 covering 42 disclosed in Fig 9 and Para [0035]), and the molding layer (58) is in direct contact with the top surface of the base dielectric layer (38, Note that Fig 7 does not number what appears to be the top layer of the redistribution substrate but Fig 3 and Para [0025] disclose 38 as top layer of lower redistribution substrate), a sidewall (right side of 58 as shown in Fig 10) of the molding layer (58) is aligned with a sidewall (right side of 28 as shown in Fig 10) of the redistribution substrate (28).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Wu ‘474 in view of Chen ‘339 as further evidenced by Ran He and T. Suga, ("Effects of Ar plasma and Ar fast atom bombardment (FAB) treatments on Cu/polymer hybrid surface for wafer bonding," 2014 International Conference on Electronics Packaging (ICEP), Toyama, 2014, pp. 78-81, doi: 10.1109/ICEP.2014.6826665, hereinafter He et al).
With respect to Claim 34 Wu ‘474 as modified by Chen ‘339 discloses all limitations in the semiconductor package of claim 26, and Wu ‘474 as modified by Chen ‘339 with further evidence from He et al. disclose wherein the first maximum width is different from the second maximum width. (Figs 2c and 2d of He et al. disclose coupling of upper and lower pads where the pad widths are different). A person having ordinary skill in the art would recognize that normal variations in the manufacturing process will result in pads being of different widths even if their targeted design width is the same and that these pads of different widths could still be formed into a successful hybrid bond.
Claims 35 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Wu ‘474 in view of Chen ‘339 and in further view of Hu et al. (US 2021/0057309 A1, hereinafter Hu ‘309), in view of the following arguments.
With respect to Claim 35 Wu ‘474 as modified by Chen ‘339 discloses all limitation of the semiconductor package of claim 26, and Wu ‘474 discloses further wherein each of the first base dielectric layer (38) and the second base dielectric layer (62) includes a photosensitive polymer layer (Para [0021] discloses 38 as a photosensitive polymer layer and Para [0037] discloses 62 as a photosensitive polymer layer), and the first protection layer (dielectric layer of 44 in contact with 48).
But Wu ‘474 as modified by Chen ‘339 fails to explicitly disclose the first protection layer comprises different material from the first base dielectric layer.
Nevertheless, Hu ‘309 teaches (Fig 3A of Hu ‘309) the first protection layer (BD1, Fig 3A of Hu ‘309, Para [0018]) comprises different material (Para 0018 of Hu ‘309 discloses BD1 as silicon oxide).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing data, absent unexpected results, to use the protection layer comprises a different material of Hu ‘309 in the semiconductor package of Wu ‘474 as modified by Chen ‘339. Wu ‘474 as modified by Chen ‘339 discloses a semiconductor package comprising a die with a redistribution layer that is made of conductive layers and dielectric layers but does not provide explicit details on the composition of the dielectric material. Hu ‘309 teaches a die with a redistribution layer and provides details of the composition of the dielectric material. The ordinary artisan would have been motivated to modify Wu ‘474 as modified by Chen ‘339 in the manner set forth above, at least, because this layer silicon oxide is a well-known material providing the well-known advantage of dielectric protection to conductive structures in a redistribution layer.
As incorporated, the use of silicon oxide as the dielectric in a die redistribution layer as taught by Hu ‘309 would be used as the dielectric material in layers of redistribution layers of 44 of Wu ‘474 as modified by Chen ‘339.
Therefore the first protection layer (dielectric layer of 44 in contact with 48 of Wu ‘474 as modified by Chen ‘339) would comprises a different material (silicon oxide) from the first base dielectric layer (38 which is a photosensitive polymer layer as described above).
Claims 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Wu ‘474 in view of Chen ‘339 in view of Chen ‘266 and in further view of Hu ‘309, in view of the following arguments.
With respect to Claim 37 Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 discloses all limitations of the semiconductor package of claim 36, and Wu’474 teaches the same photosensitive polymer (Para [0021] discloses 38 as BCB and Para [0031] discloses 48 as BCB as described above)
But Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 fails to explicitly disclose wherein the protection layer comprises different material from the same photosensitive polymer.
Nevertheless, Hu ‘309 teaches (Fig 3A of Hu ‘309) the protection layer (BD1, Fig 3A of Hu ‘309, Para [0018]) comprises different material (Para 0018 of Hu ‘309 discloses BD1 as silicon oxide).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing data, absent unexpected results, to use the protection layer comprises a different material of Hu ‘309 in the semiconductor package of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266. Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 discloses a semiconductor package comprising a die with a redistribution layer that is made of conductive layers and dielectric layers but does not provide explicit details on the composition of the dielectric material. Hu ‘309 teaches a die with a redistribution layer and provides details of the composition of the dielectric material. The ordinary artisan would have been motivated to modify Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 in the manner set forth above, at least, because this layer silicon oxide is a well-known material providing the well-known advantage of dielectric protection to conductive structures in a redistribution layer.
As incorporated, the use of silicon oxide as the dielectric in a die redistribution layer as taught by Hu ‘309 would be used as the dielectric material in layers of redistribution layers of 44 of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266.
Therefore the first protection layer (dielectric layer of 44 in contact with 48 of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266) would comprises a different material (silicon oxide) from the same photosensitive polymer (Para [0021] discloses 38 as BCB and Para [0031] discloses 48 as BCB as described above).
With respect to Claim 38 Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 discloses all limitations of the semiconductor package of claim 36,
but Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 fails to explicitly disclose wherein the protection layer includes a silicon oxide layer.
Nevertheless, Hu ‘309 teaches (Fig 3A of Hu ‘309) the protection layer (BD1, Fig 3A of Hu ‘309, Para [0018]) includes a silicon oxide layer (Para 0018 of Hu ‘309 discloses BD1 as silicon oxide).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing data, absent unexpected results, to use the protection layer includes a silicon oxide layer of Hu ‘309 in the semiconductor package of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266. Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 discloses a semiconductor package comprising a die with a redistribution layer that is made of conductive layers and dielectric layers but does not provide explicit details on the composition of the dielectric material. Hu ‘309 teaches a die with a redistribution layer and provides details of the composition of the dielectric material. The ordinary artisan would have been motivated to modify Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 in the manner set forth above, at least, because this layer silicon oxide is a well-known material providing the well-known advantage of dielectric protection to conductive structures in a redistribution layer.
As incorporated, the use of silicon oxide as the dielectric in a die redistribution layer as taught by Hu ‘309 would be used as the dielectric material in layers of redistribution layers of 44 (protection layer) of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266.
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Wu ‘474 in view of Chen ‘339 in view of Chen ‘266, in further view of Yu et al. (US 2017/0301650 A1, hereinafter Yu ‘650), in view of the following arguments.
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With respect to Claim 40 Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 discloses all limitations of the semiconductor package of claim 36,
But Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 fails to explicitly disclose wherein each of the plurality of upper coupling pads includes: a first via part that penetrates a portion of the base dielectric layer, and a first pad part that is connected to the first via part in the base dielectric layer, wherein each of the plurality of redistribution chip pads includes: a second via part that penetrates the protection layer, and a second pad part that is in the redistribution dielectric layer.
Nevertheless, in a related endeavor (Figs 1-17 of Yu ‘650), Yu ‘650 teaches wherein each of the plurality of upper coupling pads (31, Fig 17 of Yu ‘650, Para [0017]) includes:
a first via part (via part of 31 as shown in Fig 17 of Yu ‘650) that penetrates a portion (layer 28 as shown in Fig 17 of Yu ‘650) of the base dielectric layer (28/32, fig 17 of Yu ‘650, Para [0016 and 0018])(Fig 17 of Yu ‘650 discloses the first via part of 31 penetrates through layer 28), and
a first pad part (pad part of 31 as shown in Fig 17 of Yu ‘650) that is connected to the first via part (via part of 31 as shown in Fig 17 of Yu ‘650) in the base dielectric layer (28/32)(Fig 17 of Yu ‘650 discloses pad part of 31 connected to via part of 31),
wherein each of the plurality of redistribution chip pads (131, Fig 17 of Yu ‘650, Para [0025]) includes:
a second via part (via part of 131 as shown in Fig 17 of Yu ‘650) that penetrates the protection layer (first protection layer as shown in annotated Fig 8 of Yu ‘650, hereinafter 1PL)(annotated Fig 8 of Yu ‘650 discloses via part of 131 penetrates the protection layer 1PL), and
a second pad part (pad part of 131 as shown in Fig 17 of Yu ‘650) that is in the redistribution dielectric layer (132, Fig 17 of Yu ‘650, Para [0025]) (annotated Fig 8 of Yu ‘650 discloses pad part of 131 is in the redistribution layer 132).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yu ‘650’s teaching of wherein each of the plurality of upper coupling pads includes: a first via part that penetrates a portion of the base dielectric layer, and a first pad part that is connected to the first via part in the base dielectric layer, wherein each of the plurality of redistribution chip pads includes: a second via part that penetrates the protection layer, and a second pad part that is in the redistribution dielectric layer into Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266’s device. Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 discloses a semiconductor device comprising a die that is direct bonded to a redistribution substrate. Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 also discloses a protection layer and a dielectric layer on the die and discloses die bond pads and redistribution layer pads. Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 speaks to the vias connected pads to the die but it does not explicitly disclose the shape details of via and pads in the protection layer and the dielectric layer. Yu ‘650 teaches a semiconductor device comprising a die that is direct bonded to a redistribution substrate, a protection layer and a dielectric layer on the die and discloses die bond pads and redistribution layer pads and teaches the shape details of via and pads in the protection layer and the dielectric layer. Therefore, the ordinary artisan would have been motivated to modify Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 in the manner set forth above, at least, because, as Yu ‘650 teaches the well-known advantage of using conductive pads and vias through dielectric materials to enable electrical connections that are insulated from parasitic capacitance issues.
As incorporated, teachings of Yu ‘650 of the shapes (via part and pad part) of the plurality of upper coupling pads penetrating the base dielectric layer would be used in as via parts and pad parts of pads upper coupling pads (36) as they penetrate base dielectric layer (38) of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 and the teachings of Yu ‘650 of the and the shapes (via part and pad part) of the plurality of redistribution chip pads as they penetrate the protection layer and redistribution layer would be used in the redistribution chip pads (46) as they penetrate the protection layer (dielectric layer of 44 in contact with 48) and the redistribution layer (48) of Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266.
Claims 41-45 are rejected under 35 U.S.C. 103 as being unpatentable over Wu ‘474 in view of Yu ‘650 in view of Hu ‘309, in view of Chen ‘339 and in further view of Chen ‘266, in view of the following arguments.
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With respect to Claim 41 Wu ‘474 discloses a semiconductor package (Fig 1-15), comprising:
a redistribution substrate (28, Fig 2, Para [0019]) including a base dielectric layer (38, Fig 2 and 3, Para [0019]) and a plurality (disclosed in Fig 2) of upper coupling pads (pads 36, Fig 3, Para [0019]) in the base dielectric layer (38); and
a semiconductor chip (42, Fig 5, Para [0029]) on the redistribution substrate (28), the semiconductor chip (42) including a semiconductor substrate (43, Fig 5, Para [0029]), a plurality of chip pads (chip pads of 42 disclosed in Para [0030] but are not shown in Figures), a protection layer (dielectric layer of 44 in contact with 48, Fig 5, Para [0029]) covering the plurality of chip pads (chip pads disclosed in Para [0030] but are not shown in Figures)(Fig 7 discloses dielectrics of 44 cover bottom of die 42), a redistribution dielectric layer (48, Fig 5, Para [0031]) on the protection layer (dielectric layer of 44 in contact with 48), and a plurality (disclosed in Figs 5 and 7) of redistribution chip pads (pads 46, Fig 5, Para [0031]) that penetrate the redistribution dielectric layer (48)(46 penetrating 48 disclosed in Fig 7 and Para [0031]) and the protection layer (dielectric layer of 44 in contact with 48) and are connected to the plurality of chip pads (chip pads of 42 disclosed in Para [0030] but are not shown in Figures) (Para [0030] discloses that 46 are die pillars are mechanically and electrically connected to 42 chip pads and the protection layer is on layer 48 as described above, therefore 46 penetrates the protection layer (dielectric layer of 44) and are connected to chip pads of 42); and
a molding layer (58, Fig 9, Para [0035]) covering a top surface (top of 42) of the semiconductor chip (42)(Fig 9 and Para [0035] disclose 58 higher than top of 42),
wherein the first pad part (tops of 36) in each of the plurality of upper coupling pads (pads 36) provides first pad parts (tops of 36) of the plurality of upper coupling pads (pads 36)(tops of 36 being top of pads 36 is disclosed in Fig 7),
wherein the second pad part (tops of 46) in each of the plurality of redistribution chip pads (pads 46) provides second pad parts of the plurality of redistribution chip pads (pads 46)(tops of 46 being top of pads 46 is disclosed in Fig 7),
wherein the first pad parts (tops of 36) of the plurality of upper coupling pads (pads 36) are in direct contact (Fig 5 and Para [0034] disclose top of 46 in direct contact with top of 36) with the second pad parts (tops of 46) of the plurality of redistribution chip pads (pads of 46),
wherein the base dielectric layer (38) includes a first photosensitive polymer layer (Para [0021] discloses 38 as a photosensitive polymer layer), wherein the redistribution dielectric layer (48) includes a second photosensitive polymer layer (Para [0031] discloses 48 as a photosensitive polymer layer),
wherein the protection layer (dielectric layer of 44 in contact with 48), and
wherein a top surface (top surface of photosensitive polymer layer of 38) of the first photosensitive polymer layer (photosensitive polymer layer of 38) is in direct contact with a top surface (top surface of photosensitive polymer layer of 48) of the second photosensitive polymer layer (photosensitive polymer layer of 48) (Fig 5 and Para [0034] disclose top of 38 in direct contact with top of 48),
the first pad part (tops of 36) of each of the plurality of upper coupling pads (pads 36) has a first width (first width of 36 shown in annotated Fig 7), and
But Wu ‘474 fails to explicitly disclose wherein each of the plurality of upper coupling pads includes: a first via part that penetrates a portion of the base dielectric layer, and a first pad part that is in the base dielectric layer, wherein each of the plurality of redistribution chip pads includes: a second pad part that is in the redistribution dielectric layer,
Nevertheless, in a related endeavor (Figs 1-17 of Yu ‘650), Yu ‘650 teaches wherein each of the plurality of upper coupling pads (31, Fig 17 of Yu ‘650, Para [0017]) includes: a first via part (via part of 31 as shown in Fig 17 of Yu ‘650) that penetrates a portion (layer 28 as shown in Fig 17 of Yu ‘650) of the base dielectric layer (28/32, fig 17 of Yu ‘650, Para [0016 and 0018])(Fig 17 of Yu ‘650 discloses the first via part of 31 penetrates through layer 28), and a first pad part (pad part of 31 as shown in Fig 17 of Yu ‘650) that is connected to the first via part (via part of 31 as shown in Fig 17 of Yu ‘650) in the base dielectric layer (28/32)(Fig 17 of Yu ‘650 discloses pad part of 31 connected to via part of 31), wherein each of the plurality of redistribution chip pads (131, Fig 17 of Yu ‘650, Para [0025]) includes: a second via part (via part of 131 as shown in Fig 17 of Yu ‘650) that penetrates the protection layer (first protection layer as shown in annotated Fig 8 of Yu ‘650, hereinafter 1PL)(annotated Fig 8 of Yu ‘650 discloses via part of 131 penetrates the protection layer 1PL), and a second pad part (pad part of 131 as shown in Fig 17 of Yu ‘650) that is in the redistribution dielectric layer (132, Fig 17 of Yu ‘650, Para [0025]) (annotated Fig 8 of Yu ‘650 discloses pad part of 131 is in the redistribution layer 132).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yu ‘650’s teaching of wherein each of the plurality of upper coupling pads includes: a first via part that penetrates a portion of the base dielectric layer, and a first pad part that is connected to the first via part in the base dielectric layer, wherein each of the plurality of redistribution chip pads includes: a second via part that penetrates the protection layer, and a second pad part that is in the redistribution dielectric layer into Wu ‘474’s device. Wu ‘474 discloses a semiconductor device comprising a die that is direct bonded to a redistribution substrate. Wu ‘474 also discloses a protection layer and a dielectric layer on the die and discloses die bond pads and redistribution layer pads. Wu ‘474 speaks to the vias connected pads to the die but it does not explicitly disclose the shape details of via and pads in the protection layer and the dielectric layer. Yu ‘650 teaches a semiconductor device comprising a die that is direct bonded to a redistribution substrate, a protection layer and a dielectric layer on the die and discloses die bond pads and redistribution layer pads and teaches the shape details of via and pads in the protection layer and the dielectric layer. Therefore, the ordinary artisan would have been motivated to modify Wu ‘474 in the manner set forth above, at least, because, as Yu ‘650 teaches the well-known advantage of using conductive pads and vias through dielectric materials to enable electrical connections that are insulated from parasitic capacitance issues.
As incorporated, teachings of Yu ‘650 of the shapes (via part and pad part) of the plurality of upper coupling pads penetrating the base dielectric layer would be used in as via parts and pad parts of pads upper coupling pads (36) as they penetrate base dielectric layer (38) of Wu ‘474 and the teachings of Yu ‘650 of the and the shapes (via part and pad part) of the plurality of redistribution chip pads as they penetrate the protection layer and redistribution layer would be used in the redistribution chip pads (46) as they penetrate the protection layer (dielectric layer of 44 in contact with 48) and the redistribution layer (48) of Wu ‘474.
Wu ‘474 as modified by Yu ‘650 fails to explicitly disclose wherein the protection layer includes silicon oxide
Nevertheless, Hu ‘309 teaches (Fig 3A of Hu ‘309) the protection layer (BD1, Fig 3A of Hu ‘309, Para [0018]) includes a silicon oxide layer (Para 0018 of Hu ‘309 discloses BD1 as silicon oxide).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing data, absent unexpected results, to use the protection layer includes a silicon oxide layer of Hu ‘309 in the semiconductor package of Wu ‘474 as modified by Yu ‘650. Wu ‘474 as modified by Yu ‘650 discloses a semiconductor package comprising a die with a redistribution layer that is made of conductive layers and dielectric layers but does not provide explicit details on the composition of the dielectric material. Hu ‘309 teaches a die with a redistribution layer and provides details of the composition of the dielectric material. The ordinary artisan would have been motivated to modify Wu ‘474 as modified by Yu ‘650 in the manner set forth above, at least, because this layer silicon oxide is a well-known material providing the well-known advantage of dielectric protection to conductive structures in a redistribution layer.
As incorporated, the use of silicon oxide as the dielectric in a die redistribution layer as taught by Hu ‘309 would be used as the dielectric material in layers of redistribution layers of 44 (protection layer) of Wu ‘474 as modified by Yu ‘650.
Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 fails to explicitly disclose upper coupling pads has a first maximum width,
Nevertheless, in a related endeavor (Fig 3 of Chen ‘339), Chen ‘339 teaches a pad has a maximum width (Para [0026] of Chen ‘339 teaches a maximum top width of bond via 120 as 10µm).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chen ‘339’s maximum pad width into Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309’s device. Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 teaches a semiconductor package comprising a die that is directly bonded to a substrate but Wu ‘474 teaches the direct bond process but is Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 does not provide details with regards to the dimensions of the pads to be bonded. Chen ‘339 teaches a direct bond process for a die to a substrate (Para 0029 of Chen ‘339 teaches that 101 may be a wafer) and provides details on pad widths and spacing; Chen ‘339 presents (Para [0026]) a width range for the direct bond connections. Therefore, the ordinary artisan would have been motivated to modify Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 and further modified by Yu ‘650 in the manner set forth above, at least, because the widths of the direct bond connections as taught by Chen ‘339 in Para [0051] these pad dimensions can support a process which simplify the bonding process and therefore lead to reduced costs.
As incorporated, the maximum pad widths of upper coupling pads as taught by Chen ‘339 would be used as the maximum width of upper coupling pads (pads of 36) of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309.
Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 fails to explicitly disclose a first interval between adjacent ones of the plurality of upper coupling pads is less than the first maximum width.
Nevertheless, in a related endeavor, (Fig 1A of Chen ‘266), Chen ‘266 teaches wherein an interval between adjacent ones of the plurality of first redistribution chip pads (Fig 1A and Para [0015] of Chen ‘266 teaches a pad pitch of 5µm).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use wherein an interval between adjacent ones of the plurality of first redistribution chip pads as taught by Chen ‘266 in the semiconductor package of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339. Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 discloses a semiconductor device comprising a die that is direct bonded to a substrate and further teaches pad widths and Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 is open to the interval spacing between those pads. Chen ‘266 also teaches a direct bond process and provides details on interval spacing between bond pads. The ordinary artisan would have been motivated to modify, therefore, Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 in the manner set forth above, at least, because as taught in by Chen ‘266 (Para [0072]) using the taught constant pitch between bond pads provides an increased bonding are that can reduce device contact resistance due to misalignment or warping that may occur during bonding.
As incorporated the teaching of the pad spacing of Chen ‘266 would be used as the interval spacing of first upper coupling pads (36) and the first redistribution chip pads (pads 46) of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339.
Therefore, the combination of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 further discloses wherein an interval (5µm as taught by Chen ‘266) between adjacent ones of the plurality of first redistribution chip pads (pads 46 of Wu ‘474) is less than the first maximum width (10 µm of Chen ‘339).
With respect to Claim 42 Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 discloses all limitations of the semiconductor package of claim 41, and Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 further discloses wherein the second pad part (tops of 46) of each of the plurality of redistribution chip pads (46) has a second width (second width of 46 shown in annotated Fig 7), and Chen ‘339 teaches a pad has a maximum width (Para [0026] of Chen ‘339 teaches a maximum top width of bond via 120 as 10µm)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teachings of Chen ‘339’s maximum pad width into Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266’s device. Chen ‘339 teaches bond connections for direct bonding of a chip to a substrate (Para 0029 of Chen ‘339 teaches that 101 may be a wafer). Chen ‘339 presents (Para [0026]) a width range for the direct bond connections. Therefore, the ordinary artisan would have been motivated to modify Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 in the manner set forth above, at least, because the widths of the direct bond connections, as by Chen ‘339 teaches in Para [0051] these pad dimensions can support a process which simplify the bonding process and therefore lead to reduced costs..
As incorporated, the maximum pad width as taught by Chen ‘339 would be used as the maximum width in each of the plurality of redistribution chip pads (46) and the second pad part (pad of 31) of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266.
Therefore the combination of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 discloses and the first maximum width (width of pads of 36 as modified above) is equal to the second maximum width (width of pads of 46 as modified above) (Para [0026] of Chen ‘339 teaches a maximum width for 10 µm for both pads).
With respect to Claim 43 Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 discloses all limitations of the semiconductor package of claim 41, and Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 further discloses wherein the second pad part (tops of 46) of each of the plurality of redistribution chip pads (46) has a second width (second width of 46 shown in annotated Fig 7),
But Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 fails to explicitly disclose a second maximum width.
Nevertheless, Chen ‘339 teaches a pad has a maximum width (Para [0026] of Chen ‘339 teaches a maximum top width of bond via 120 as 10µm).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate further teachings of Chen ‘339’s maximum pad width into Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266’s device. Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 teaches a semiconductor package comprising a die that is directly bonded to a substrate but Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 does not provide details with regards to the dimensions of the pads to be bonded. Chen ‘339 teaches a direct bond process for a die to a substrate (Para 0029 of Chen ‘339 teaches that 101 may be a wafer) and provides details on pad widths and spacing; Chen ‘339 presents (Para [0026]) a width range for the direct bond connections. Therefore, the ordinary artisan would have been motivated to modify Wu ‘474 as modified by Chen ‘339 and further modified by Chen ‘266 and further modified by Yu ‘650 in the manner set forth above, at least, because the widths of the direct bond connections as taught by Chen ‘339 in Para [0051] these pad dimensions can support a process which simplify the bonding process and therefore lead to reduced costs.
As incorporated, the maximum pad widths of taught by Chen ‘339 would be used as the maximum width of redistribution chip pads (pads of 46) of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266.
Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 fail to explicitly disclose wherein a second interval between adjacent ones of the plurality of redistribution chip pads is less than the first maximum width.
Chen ‘266 teaches wherein an interval between adjacent ones of bonding pads (Fig 1A and Para [0015] of Chen ‘266 teaches a pad pitch of 5µm).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to further use the teachings of Chen ‘266 wherein an interval between adjacent ones of bonding pads in the semiconductor package of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266. Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 discloses a semiconductor device comprising a die that is direct bonded to a substrate and further teaches pad widths and Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 is open to the interval spacing between those pads. Chen ‘266 also teaches a direct bond process and provides details on interval spacing between bond pads. The ordinary artisan would have been motivated to modify, therefore, Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 in the manner set forth above, at least, because as taught in by Chen ‘266 (Para [0072]) using the taught constant pitch between bond pads provides an increased bonding are that can reduce device contact resistance due to misalignment or warping that may occur during bonding.
As incorporated the teaching of the pad spacing of Chen ‘266 would be used as the second interval spacing of redistribution chip pads (46) of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266.
Therefore, the combination of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 further discloses wherein a second interval (5µm as taught by Chen ‘266 as incorporated above) between adjacent ones of the plurality of redistribution chip pads (pads 46 of Wu ‘474) is less than the first maximum width (10 µm of Chen ‘339 as incorporated above).
With respect to Claim 44 Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 discloses all limitations of the semiconductor package of claim 41, and Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 further discloses wherein the second pad part (tops of 46) of each of the plurality of redistribution chip pads (46) has a second width (second width of 46 shown in annotated Fig 7), and Chen ‘339 teaches a pad has a maximum width (Para [0026] of Chen ‘339 teaches a maximum top width of bond via 120 as 10µm)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teachings of Chen ‘339’s maximum pad width into Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266’s device. Chen ‘339 teaches bond connections for direct bonding of a chip to a substrate (Para 0029 of Chen ‘339 teaches that 101 may be a wafer). Chen ‘339 presents (Para [0026]) a width range for the direct bond connections. Therefore, the ordinary artisan would have been motivated to modify Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 in the manner set forth above, at least, because the widths of the direct bond connections, as by Chen ‘339 teaches in Para [0051] these pad dimensions can support a process which simplify the bonding process and therefore lead to reduced costs..
As incorporated, the maximum pad width as taught by Chen ‘339 would be used as the second maximum width in each of the plurality of redistribution chip pads (46) and the second pad part (pad of 31) of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266.
Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 fail to explicitly disclose wherein a second interval between adjacent ones of the plurality of redistribution chip pads is less than the second maximum width.
Chen ‘266 teaches wherein an interval between adjacent ones of bonding pads (Fig 1A and Para [0015] of Chen ‘266 teaches a pad pitch of 5µm).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to further use the teachings of Chen ‘266 wherein an interval between adjacent ones of bonding pads in the semiconductor package of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266. Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 discloses a semiconductor device comprising a die that is direct bonded to a substrate and further teaches pad widths and Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 is open to the interval spacing between those pads. Chen ‘266 also teaches a direct bond process and provides details on interval spacing between bond pads. The ordinary artisan would have been motivated to modify, therefore, Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 in the manner set forth above, at least, because as taught in by Chen ‘266 (Para [0072]) using the taught constant pitch between bond pads provides an increased bonding are that can reduce device contact resistance due to misalignment or warping that may occur during bonding.
As incorporated the teaching of the pad spacing of Chen ‘266 would be used as the second interval spacing of redistribution chip pads (46) of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266.
Therefore, the combination of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 further discloses wherein a second interval (5µm as taught by Chen ‘266 as incorporated above) between adjacent ones of the plurality of redistribution chip pads (pads 46 of Wu ‘474) is less than the second maximum width (10 µm of Chen ‘339 as incorporated above).
With respect to Claim 45 Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 discloses all limitations of the semiconductor package of claim 41, and Chen ‘339 further teaches wherein a width of the first pad part (width of 120b, Fig 3 of Chen ‘330, Para [0035]) of each of the plurality of upper coupling pads (120b/214, Fig 3 of Chen ‘339, Para [0035]) increases in a direction from a bottom surface (bottom of 116) toward a top surface (top of 116) of the base dielectric layer (116, Fig 3 of Chen ‘339, Para [0035])(Fig 3 of Chen ‘339 discloses that the width of pad part 120b increases in width from the bottom of 116 to the top of 116), and a width of the second pad part (width of 220b, Fig 3 of Chen ‘339, Para [0035]) of each of the plurality of redistribution chip pads (220b/214, Fig 3 of Chen ‘339, Para [0035]) increases with an increasing distance from the plurality of chip pads (214, Fig 3 of Chen ‘339, Para [0035])(Fig 3 of Chen ‘339 discloses 220b increases in width as it increases in distance from pad 214).
Therefore it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, to use the additional teachings of Chen ‘339 wherein a width of the first pad part of each of the plurality of upper coupling pads increases in a direction from a bottom surface toward a top surface of the base dielectric layer, and a width of the second pad part of each of the plurality of redistribution chip pads increases with an increasing distance from the plurality of chip pads in the package of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266. The ordinary artisan would have been motivated to modify Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266 in the manner set forth above, at least, because as taught in by Chen ‘339 (Para [0051]) in using this method the process of bonding pads is simplified and the cost thereof is reduced.
As incorporated the chip pads with a tapered shape as taught by Chen ‘339 would be used as the shape of upper coupling pads (36) and redistribution chip pads (46) of Wu ‘474 as modified by Yu ‘650 and further modified by Hu ‘309 and further modified by Chen ‘339 and further modified by Chen ‘266.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898