DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/13/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
6. Claims 1, 10, 18, 19 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Wegener (U.S. Publication 2013/0262809) (Wegener hereinafter) in view of Zhao (U.S. Patent 9,760,538) (Zhao hereinafter).
7. As per claim 1, Wegener teaches one or more processors, comprising: circuitry, in response to an application programming interface (API) call indicating one or more memory locations that store one or more indices of non-zero values within one or more sparse matrices of data, cause instructions to be executed by the one or more processors to compress the one or more sparse matrices of data [“Memory system operations are extended for a data processor by an application programming interface (API), including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system.” ¶ 0011; “The APAX SOURCE register contains the 32-bit or 64-bit start address of the array to be compressed. ¶ 0065; array mapped to 2D matrix as identified as an example array dimension in Table 2; “The three sample portions of application programs provided just above call operations of the API that use the parameters of the API. ¶ 0129] using one or more indices.
Wegener does not explicitly disclose but Zhou discloses in response to the API call, generate one or more compressed arrays corresponding to the one or more sparse matrices of data by using the one or more indices of the non-zero values stored in the one or more memory locations [“A structured compressed representation of the matrix, either structured CSC or structured CSR, of the matrix is created by encoding information about the non-zero entries into a composite array (A.sub.vc or A′.sub.vr) and an index array (A.sub.r or A′.sub.c) as described above (step 62). The structured compressed representation is processed (step 63),” col. 14, lines 57 – 63];
store the non-zero values of the one or more sparse matrices of data in the one or more compressed arrays that are accessible to the one or more processors to perform sparse matrix multiply operations [“The structured compressed representation is processed (step 63), such as by performing SpMV, as described below with reference to FIG. 7, or SpMTV, as described below with reference to FIG. 8, though other kinds of processing are also possible … A summation calculator, a function for summing together results of multiplication of the values of the non-zero arrays described in step 76 below,” col. 14, line 62 – col. 15, line 13; SpMV and SpMTV indicate matrix multiplication]; and
generate an output indicating whether the non-zero values were stored successfully in the one or more compressed arrays [“The user device 38 can communicate with the server 33 through the network 15, receive commands from performing computations, and output the results of the computations back to the user device,” col. 13, lines 20 - 23].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener and Zhou available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener to include the capability of matrix and vector multiplication operations as taught by Zhou, thereby providing a mechanism to enhance system efficiency by minimizing potential storage and processing latencies.
8. As per claim 10, it is a system claim having similar limitations as cited in claim 1. Thus, claim 10 is also rejected under the same rationale as cited in the rejection of claim 1 above.
9. As per claim 18, it is a media claim having similar limitations as cited in claim 1. Thus, claim 18 is also rejected under the same rationale as cited in the rejection of claim 1 above.
10. As per claim 19, Wegener and Zhao teach the non-transitory computer-readable medium of claim 18. Wegener further generate one or more instructions to compress one or more sparse matrices of data [“Memory system operations are extended for a data processor by an application programming interface (API), including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system.” ¶ 0011; “The APAX SOURCE register contains the 32-bit or 64-bit start address of the array to be compressed. ¶ 0065; array mapped to 2D matrix as identified as an example array dimension in Table 2; “The three sample portions of application programs provided just above call operations of the API that use the parameters of the API. ¶ 0129] in response to the API call using one or more indices, included in the API call, indicating one or more locations of one or more values within the one or more sparse matrices [“Parameters of the API can include indicators of data type, size of a sample set, and compressed data location (destination for a compression operation, source for a decompression operation), uncompressed location (destination for a decompression operation, source for a compression operation), and a selected compression mode, such as lossless, fixed rate, or fixed quality modes,” ¶ 0012; compressed data location and uncompressed locations mapped to indices indicating one or more locations], wherein in response to API call, the one or more processors are to cause the compressed one or more sparse matrices, and the one or more indices, to be stored in storage accessible to the one or more processors to perform one or more matrix operations [“Operations of the API include engines that move data between the compressed data location and the uncompressed location, in conjunction with which one of compression and decompression is performed, as specified by the parameters of the API,” ¶ 0012].
11. As per claim 26, Wegener teaches a method comprising: receiving, in response to an application programming interface (API) call an indication of one or more memory locations that store one or more indices of non-zero values within one or more matrices of data [“Parameters of the API can include indicators of data type, size of a sample set, and compressed data location (destination for a compression operation, source for a decompression operation), uncompressed location (destination for a decompression operation, source for a compression operation), and a selected compression mode, such as lossless, fixed rate, or fixed quality modes,” ¶ 0012; compressed data location and uncompressed locations mapped to indices indicating one or more locations].
Wegener does not explicitly disclose but Zhao discloses in response to the API call, generating one or more compressed arrays corresponding to the one or more matrices by using the memory locations that store the indices of the non-zero values [“A structured compressed representation of the matrix, either structured CSC or structured CSR, of the matrix is created by encoding information about the non-zero entries into a composite array (A.sub.vc or A′.sub.vr) and an index array (A.sub.r or A′.sub.c) as described above (step 62). The structured compressed representation is processed (step 63),” col. 14, lines 57 – 63];
causing the one or more compressed arrays to be stored in memory accessible to the one or more processors to perform the matrix multiply and accumulate (MMA) operations [“The structured compressed representation is processed (step 63), such as by performing SpMV, as described below with reference to FIG. 7, or SpMTV, as described below with reference to FIG. 8, though other kinds of processing are also possible … A summation calculator, a function for summing together results of multiplication of the values of the non-zero arrays described in step 76 below,” col. 14, line 62 – col. 15, line 13; SpMV and SpMTV indicate matrix multiplication]; and
generating an output that indicates whether the one or more compressed arrays to perform the MMA operations were stored successfully [“The user device 38 can communicate with the server 33 through the network 15, receive commands from performing computations, and output the results of the computations back to the user device,” col. 13, lines 20 - 23].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener and Zhou available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener to include the capability of matrix and vector multiplication operations as taught by Zhou, thereby providing a mechanism to enhance system efficiency by minimizing potential storage and processing latencies.
12. Claims 4, 5, 13, 14, 21, 22, 29 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Wegener and Zhao in view of Araki (U.S. Publication 2019/0050371) (Araki hereinafter).
13. As per claim 4, Wegener and Zhao teach the one or more processors of claim 1. Wegener and Zhao do not explicitly disclose but Araki discloses wherein the circuitry in response to the API call is to perform a sparse matrix multiplication operation with one or more graphics processing cores [“The present invention may be applied to a use for, for example, calculation of sparse matrix vector multiplication products using a vector calculator. In addition, the present invention may be applied to a use for calculation of sparse matrix vector multiplication products using a GPU (Graphics Processing Unit).” ¶ 0068].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener, Zhao and Araki available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener and Zhao to include the capability of matrix and vector storage operations as taught by Araki, thereby providing a mechanism to enhance system efficiency by utilizing less storage resources and facilitating faster data processing.
14. As per claim 5, Wegener and Zhao teach the one or more processors of claim 1. Wegener and Zhao do not explicitly disclose but Araki discloses wherein to compress includes to store the non-zero values of the one or more sparse matrices of data in the one or more compressed arrays that are accessible to one or more graphics processing units [“FIG. 8 exemplifies a sparse matrix storing method in CRS (Compressed Row Storage) format. In the sparse matrix storing method in CRS format, values of elements which are not zero (referred to as “non-zero element(s)” hereinafter) are stored in a one-dimensional array … In addition, column indexes of the non-zero elements in the original matrix are also stored in a one dimensional array in a similar manner.” ¶ 0010].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener, Zhao and Araki available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener and Zhao to include the capability of matrix and vector storage operations as taught by Araki, thereby providing a mechanism to enhance system efficiency by utilizing less storage resources and facilitating faster data processing.
15. As per claim 13, it is a system claim having similar limitations as cited in claims 4 and 5. Thus, claim 13 is also rejected under the same rationale as cited in the rejection of claims 4 and 5 above.
16. As per claim 14, it is a system claim having similar limitations as cited in claim 5. Thus, claim 14 is also rejected under the same rationale as cited in the rejection of claim 5 above.
17. As per claim 21, it is a media claim having similar limitations as cited in claim 4. Thus, claim 21 is also rejected under the same rationale as cited in the rejection of claim 4 above.
18. As per claim 22, it is a media claim having similar limitations as cited in claim 5. Thus, claim 22 is also rejected under the same rationale as cited in the rejection of claim 5 above.
19. As per claim 29, it is a method claim having similar limitations as cited in claim 4. Thus, claim 29 is also rejected under the same rationale as cited in the rejection of claim 4 above.
20. As per claim 30, it is a method claim having similar limitations as cited in claim 5. Thus, claim 30 is also rejected under the same rationale as cited in the rejection of claim 5 above.
21. Claims 6, 15, 23 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Wegener and Zhao in view of Hejl et al. (U.S. Publication 2013/0268856) (Hejl hereinafter).
22. As per claim 6, Wegener and Zhao teach the one or more processors of claim 1. Wegener and Zhao do not explicitly disclose but Hejl discloses wherein the one or more processors, in response to receiving the API call, are to cause one or more compilers of one or more graphics processing units to generate one or more instructions to cause one or more graphics processing units to perform compression operations [“the client computer 450 may be instructed to CPU-transform data before physical submission to a GPU. For example, the client CPU may transform the virtual GPU command stream in a manipulation of at least one of a coordinate space rotation, a data amplification, a data compression, a data optimization, and an illumination evaluation to hardware specific API level commands via a device specific native interpreter before submission to a client graphics processing unit (GPU).” ¶ 0039; interpreter mapped to compiler].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener, Zhao and Hejl available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener and Zhao to include the capability of generation of device-specific API commands as taught by Hejl, thereby providing a mechanism to enhance system applicability by expanding its usability to additional platforms.
23. As per claim 15, it is a system claim having similar limitations as cited in claim 6. Thus, claim 15 is also rejected under the same rationale as cited in the rejection of claim 6 above.
24. As per claim 23, it is a media claim having similar limitations as cited in claim 6. Thus, claim 23 is also rejected under the same rationale as cited in the rejection of claim 6 above.
25. As per claim 31, it is a method claim having similar limitations as cited in claim 6. Thus, claim 31 is also rejected under the same rationale as cited in the rejection of claim 6 above.
26. Claims 7, 8, 16, 17, 24, 25, 32 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Wegener and Zhao in view of Fok et al. (U.S. Publication 2022/0012598) (Fok hereinafter).
27. As per claim 7, Wegener and Zhao teach the one or more processors of claim 1. Wegener and Zhao do not explicitly disclose but Fok discloses wherein the one or more processors, in response to receiving the API call, are to compress the one or more sparse matrices of data by compressing one or more rows of the one or more matrices [“At step 1004 of the method 1000, a compressed representation of a second data structure may be obtained. In some embodiments, the second data structure comprises a matrix. A matrix is a rectangular or two - dimensional data structure that may include multiple elements arranged in rows and columns. In some examples, a matrix may include data in a single - dimensional structure with metadata (another data structure) that includes the rectangular (width and/or length) dimension (s) of the structure. In other embodiments, a matrix may include higher - dimensional elements (3, 4, 5, etc. dimensions) which may be reduced down to a vector of matrices/vectors of matrices/ vectors. In some embodiments, a matrix may be an array/vector of row/column vectors,” ¶ 0118].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener, Zhao and Fok available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener and Zhao to include the capability of matrix and vector storage operations as taught by Fok, thereby providing a mechanism to enhance system efficiency by minimizing otherwise necessary system maintenance and modification.
28. As per claim 8, Wegener and Zhao teach the one or more processors of claim 1. Wegener and Zhao do not explicitly disclose but Fok discloses wherein the one or more processors, in response to receiving the API call, are to cause one or more columns of the one or more sparse matrices to be compressed [“At step 1004 of the method 1000, a compressed representation of a second data structure may be obtained. In some embodiments, the second data structure comprises a matrix. A matrix is a rectangular or two - dimensional data structure that may include multiple elements arranged in rows and columns. In some examples, a matrix may include data in a single - dimensional structure with metadata (another data structure) that includes the rectangular (width and/or length) dimension (s) of the structure. In other embodiments, a matrix may include higher - dimensional elements (3, 4, 5, etc. dimensions) which may be reduced down to a vector of matrices/vectors of matrices/ vectors. In some embodiments, a matrix may be an array/vector of row/column vectors,” ¶ 0118].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener, Zhao and Fok available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener and Zhao to include the capability of matrix and vector storage operations as taught by Fok, thereby providing a mechanism to enhance system efficiency by minimizing otherwise necessary system maintenance and modification.
29. As per claim 16, it is a system claim having similar limitations as cited in claim 7. Thus, claim 16 is also rejected under the same rationale as cited in the rejection of claim 7 above.
30. As per claim 17, it is a system claim having similar limitations as cited in claim 8. Thus, claim 17 is also rejected under the same rationale as cited in the rejection of claim 8 above.
31. As per claim 24, it is a media claim having similar limitations as cited in claim 7. Thus, claim 24 is also rejected under the same rationale as cited in the rejection of claim 7 above.
32. As per claim 25, it is a media claim having similar limitations as cited in claim 8. Thus, claim 25 is also rejected under the same rationale as cited in the rejection of claim 8 above.
33. As per claim 32, it is a method claim having similar limitations as cited in claim 7. Thus, claim 32 is also rejected under the same rationale as cited in the rejection of claim 7 above.
34. As per claim 33, it is a method claim having similar limitations as cited in claim 8. Thus, claim 33 is also rejected under the same rationale as cited in the rejection of claim 8 above.
35. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wegener and Zhao in view of Nurvitadhi et al. (U.S. Publication 2020/0051203) (Nurvitadhi hereinafter).
36. As per claim 9, Wegener and Zhao teach the one or more processors of claim 1. Wegener and Zhao do not explicitly disclose but Nurvitadhi discloses wherein to compress is to cause the one or more sparse matrices of data to be stored in a compressed format in a vector, array, or table, wherein the compressed format is accessible to one or more drivers of one or more graphics processing units [“A graphics processing unit comprising: one or more streaming multiprocessors; and a shared memory for storage of data; wherein the one or more streaming multiprocessors are to: detect sparse matrices; compress one or more detected sparse matrices to generate one or more compressed matrices, including compressing a first sparse matrix to generate a first compressed matrix; store the one or more compressed sparse matrices in the shared memory; and upon receiving an instruction for a neural network operation including the first sparse matrix, obtain the first compressed matrix from the shared memory, decompress the first compressed matrix to generate the first sparse matrix, and utilize the decompressed first sparse matrix in the neural network operation.” Cl. 26; “The graphics processing unit of claim 26, wherein the one or more compressed matrices are available for each of the one or more streaming multiprocessors.” Cl. 27].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener, Zhao and Nurvitadhi available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener and Zhao to include the capability of sparse matrix processing using GPUs as taught by Nurvitadhi, thereby providing a mechanism to enhance system efficiency by leveraging high performance processor capabilities.
37. Claims 20 and 28 rejected under 35 U.S.C. 103 as being unpatentable over Wegener and Zhao in view of Lagudu et al. (U.S. Publication 2022/0197973) (Lagudu hereinafter).
38. As per claim 20, Wegener and Zhao teach the non-transitory computer-readable medium of claim 18. Wegener and Zhao do not explicitly disclose but Lagudu discloses wherein to compress includes to store the non-zero values of the one or more sparse matrices of data in a data structure based, at least in part, on one or more indications of one or more non-zero values in a data structure that is accessible to one or more threads of one or more graphics processing cores [“The matrices in many applications implemented in the processing system 100 are sparse, i.e., most of the entries in the matrices have a value of zero. The sparse matrices are therefore compressed to conserve space in memory 105. Some embodiments of the processing system 100 represent sparse matrices in a compressed sparse row (CSR) format that represents a sparse matrix by three one-dimensional arrays: (1) a first array of entries that indicate the nonzero values of the sparse matrix, (2) a second array of entries that indicate the column indices of the nonzero values in the sparse matrix, and (3) a third array of entries that indicate the number of nonzero values in each row of the sparse matrix,” ¶ 0024].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener, Zhao and Lagudu available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener and Zhao to include the capability of matrix and vector storage operations as taught by Lagudu, thereby providing a mechanism to enhance system efficiency by minimizing potential storage and processing latencies.
39. As per claim 28, it is a method claim having similar limitations as cited in claim 20. Thus, claim 28 is also rejected under the same rationale as cited in the rejection of claim 20 above.
40. Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Wegener and Zhao in view of Narayanamoorthy et al. (U.S. Publication 2020/0334323) (Narayanamoorthy hereinafter).
41. As per claim 34, Wegener and Zhao teach the one or more processors of claim 1. Wegener and Zhao do not explicitly disclose but Narayanamoorthy discloses wherein matrix multiply operations include at least one or more instructions to perform a multiplication operation using one of more graphics processing units based, at least in part, on one or more indications of non-zero values of the one or more sparse matrices of data and two or more matrices containing compressed data [“A processor comprising: a cache to store data; a plurality of cores coupled to the cache, a core of the plurality of cores comprising: execution circuitry to perform multiply-accumulate operations with a first source matrix and a second source matrix to generate a result matrix responsive to an instruction, wherein the first source matrix is a sparse matrix having non-zero data elements located at certain positions, wherein the first source matrix is stored in a compressed format that identifies the positions of the non-zero data elements in the first source matrix, the execution circuitry further comprising: a plurality of multiply-accumulate circuits to perform a plurality of fused multiply-add operations to multiply the non-zero data elements of the first source matrix by corresponding data elements of the second source matrix identified based on the positions in the compressed format to generate a plurality of products, and to add the plurality of products to accumulated values to generate data elements of the result matrix,” Cl. 1].
It would have been obvious to one of ordinary skill in the art, having the teachings of Wegener, Zhao and Narayanamoorthy available before the effective filing date of the claimed invention, to modify the capability of data compression via API as disclosed by Wegener and Zhao to include the capability of sparse-dense matrix multiplication as taught by Narayanamoorthy, thereby providing a mechanism to enhance system efficiency by leveraging the sparsity of a sparse input matrix [Narayanamoorthy ¶ 0005].
Response to Arguments
Claim Rejections - 35 USC § 101
42. Applicant’s arguments have been fully considered and are persuasive. The subject rejections have been withdrawn.
Claim Rejections - 35 USC § 103
43. Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
44. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C WOOD whose telephone number is (571)272-5285. The examiner can normally be reached Monday - Friday, 8:00 am - 4:30 pm.
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/WILLIAM C WOOD/Examiner, Art Unit 2193
/Chat C Do/Supervisory Patent Examiner, Art Unit 2193
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