DETAILED ACTION
The current Office Action is in response to the papers submitted 09/03/2026. Claims 1 - 31 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 - 31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10, 18, and 26 discloses one or more intermediate code instructions indicative of decompressing matrices that comprise information enabling second instructions to be compiled that cause the matrices to be decompressed when the second instructions are performed by one or more accelerators. It is unclear how the intermediate code instructions are indicative of decompression when it is the second instructions that perform decompression when performed by one or more accelerators. It would seem the intermediate code instructions are indicative of the second instructions since the intermediate code instructions comprise information enabling the second instructions to be compiled.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 - 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Frumkin et al. (Pub. No.: US 2020/0342632) referred to as Frumkin in view of Wikipedia (Just-in-time compilation) referred to as Wikipedia.
Regarding claim 1, Frumkin teaches one or more processors [140’, Fig 1B; Paragraph 0060], comprising:
circuitry [20, Figs 1A and 1B] to, in response to an application programming interface (API) call [Paragraphs 0283, 0306, and 0346; The processes performed are in response to calls to an API that enable applications to perform the requested processes] indicating one or more matrices to decompress [104, Figs 1A and 1B; Paragraphs 0046 – 0047; The decompressor circuit in the processor decompresses an indicated compressed matrix data array]:
execute one or more intermediate code instructions indicative of decompressing the one or more matrices, wherein the one or more intermediate code instructions comprise information enabling one or more second instructions to be executed to cause the one or more matrices to be decompressed when the one or more second instructions [Fig 8; Paragraphs 0049 – 0050, 0052, 0054, 0128, and 0143 – 0152; The decompressing operation involves multiple steps. Each step represents one or more lines of instructions. A current line of instructions that is being executed is information itself that enables a next line of instructions to be executed when a current line of instruction has been executed. Such as a read instruction allows the read data to be analyzed for a decompression step] are performed by one or more accelerators [140’, Fig 1B].
However, Frumkin may not specifically disclose the limitation(s) of compiling one or more intermediate code instructions that comprise information enabling one or more second instructions to be compiled to cause an operation to be performed.
Wikipedia discloses compiling one or more intermediate code instructions that comprise information enabling one or more second instructions to be compiled to cause an operation to be performed [Page 2, Overview; Instruction code is compiled as needed showing one instruction is compiled which then enables another instruction to be compiled in the order of program execution].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing data of the claimed invention to incorporate Wikipedia in Frumkin, because the compilation can be optimized to be targets to specific hardware and software of the system, statistics can be collected about the program being compiled allowing the program to be rearranged and recompiled to improve performance, and allows for inlining of library functions without losing the advantaged of dynamic linking and with less overhead [Page 2, Overview].
Claims 10, 18, and 26 are corresponding system and medium claims of claim 1 and are rejected using the same prior art and similar reasoning. Frumkin teaches the system [100, Fig 1] comprising memory to store instructions [Paragraph 0017; The instructions of how the system operates are stored in memory] and method [Paragraph 0017].
Regarding claims 2, 11, 19, and 27, Frumkin teaches the circuitry [20, Figs 1A and 1B] is to generate the one or more second instructions [Paragraph 0283; The API calls generate tasks which are considered the one or more second instructions] to decompress one or more matrices [104, Figs 1A and 1B; Paragraphs 0046 – 0047; The decompressor circuit in the processor decompresses a compressed matrix data array].
Wikipedia discloses generating instructions based at least one or more capabilities of the one or more accelerators [Page 2, Overview; The compiled instructions are generated instructions based on the hardware and software of the system].
Regarding claims 3, 20, and 28, Frumkin teaches in response to the API call [Paragraphs 0283, 0306, and 0346], the circuitry [20, Figs 1A and 1B] is to decompress the one or more matrices as a part of a library of APIs [Paragraphs 0300; Multiple APIs is a library of APIs] to perform one or more sparse matrix multiplication operations [Paragraphs 0073 and 0193; The matrix operations include matrix multiplication].
Regarding claims 4, 12, 21, and 29, Frumkin teaches the circuitry is to decompress the one or more matrices of data in response to performing a sparse matrix multiplication operation with one or more graphics processing cores [140’, Fig 1B; Paragraphs 0059 and 0193; The decompression is based in part on the stored matrix. The decompression is based in part on the matrix multiplication since the matrix multiplication operation was used in generating the stored matrix that is decompressed after it is compressed].
Regarding claims 5, 13, 22, 30, Frumkin teaches decompressing includes converting a compressed matrix [10, Figs 1A and 1B] to a sparse matrix [106a, Figs 1A and 1B] based on indications of non-zero values [102, Figs 1A and 1B] stored in memory [Paragraph 0048] accessible to one or more graphics processing cores [140 and 140’, Fig 1B; Either processor can be a GPU and the stored non-zero value is accessible by the GPUs].
The generating a zero as a value based on stored indices values of non-zero values in claim 13 is covered by the converting a compressed matrix to a sparse matrix based on indications of non-zero values in claim 5. A sparse matrix is a matrix with zero values. The zero values are based on indications of non-zero values which are the same as the indices values of non-zero values.
Regarding claims 6, 14, 23, and 31, Frumkin teaches decompressing includes storing zero as a value of one or more matrix values based at least on stored index values of non-zero values [Paragraphs 0004, 0011, 0044, 0047, 0049, 0051; The result of the decompression is a matrix that contains nonzero and zero values based on stores indices of nonzero values in a matrix].
Regarding claims 7, 15, and 24, Frumkin teaches decompressing [20, Fig 1A and 1B] includes generating a product matrix [106a – 106d, Figs 1A and 1B] based on a result of a sparse matrix multiplication operation [140’, Fig 1B; Paragraphs 0059 and 0193; The decompression is based in part on the stored matrix. The decompression is based in part on the matrix multiplication since the matrix multiplication operation was used in generating the stored matrix that is decompressed] and index values of non-zero values of a compressed matrix [10, Figs 1A and 1B; Paragraphs 0004, 0011, 0044, 0047, 0049, 0051; The result of the decompression is a matrix that contains nonzero and zero values based on stored indices of nonzero values in a compressed matrix].
Regarding claims 8, 16, and 25, Frumkin teaches decompressing includes using a scatter vector to generate a product matrix that includes zero values of a sparse matrix [104, Figs 1A and 1B; Paragraphs 0207 – 0209; A matrix is comprised of zero and nonzero values. The decompression includes obtaining the compressed matrix for decompression. The compressed matrix is scattered across registers including zero and nonzero values resulting in a 16x8 matrix].
Regarding claims 9 and 17, Frumkin teaches one or more outputs of an API [Paragraphs 0283, 0306, and 0346; The processes performed are in response to calls to an API that enable applications to perform the requested processes] are to cause the one or more processors [140’, Fig 1B; Paragraph 0060] to convert a result of a compressed matrix multiplication [104, Figs 1A and 1B; Paragraphs 0059 and 0193; The decompression is based in part on the stored matrix. The decompression is based in part on the matrix multiplication since the matrix multiplication operation was used in generating the stored matrix that is decompressed after it is compressed] into a sparse matrix [106a, Figs 1A and 1B] based at least on index values of non-zero elements of an input matrix [10, Figs 1A and 1B; Paragraphs 0004, 0011, 0044, 0047, 0049, 0051; The result of the decompression is a matrix that contains nonzero and zero values based on stored indices of nonzero values in a compressed matrix] of the compressed matrix multiplication [104, Figs 1A and 1B; Paragraphs 0059 and 0193; The decompression is based in part on the stored matrix. The decompression is based in part on the matrix multiplication since the matrix multiplication operation was used in generating the stored matrix that is decompressed after it is compressed].
Response to Arguments
Applicant's arguments filed 09/03/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 8 - 12 that the claims are allowable since Frumkin fails to teach the amended limitations. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138
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