DETAILED ACTION
This Office Action is in response to the Applicant’s Remarks filed on 10/27/2025.
Currently, claims 1-18 and 21-22 are pending in the application. Currently, claims 5-8 and 15-16 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/27/2025 has been entered.
Response to Amendments
Applicant' s arguments with respect to claim(s) 1, 3, 4, 11, 21, and 22 have been considered but are moot because the cited prior art does teach the limitations of the amended independent claims (see prior art rejections below). Applicant’s arguments with respect to claim(s) 12-14, 17, and 18 have been considered and are persuasive (see allowable subject matter below).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being obvious over WANG (Foreign Pub. No. CN 110571195 A (English translation attached)) in view of LIAW et al. (US Pub. No. 2021/0202498).
Regarding independent claim 1, Wang teaches a memory device, comprising:
a first pull-down (PD) transistor (Fig. 3D, top right PD, ¶¶ [0090] & [0172]), a second PD transistor (Fig. 3D, bottom left PD, ¶¶ [0090] & [0172]), a first pass-gate (PG) transistor (Fig. 3D, top left PG, ¶¶ [0090] & [0172]), and a second PG transistor (Fig. 3D, top right PG, ¶¶ [0090] & [0172]) arranged in a first direction (vertical from the view of Fig. 3D) and share sharing a first active area (Fig. 3D, 2011 + 2014, ¶ [0087]) protruding from a material layer (Fig. 4C, Wang’s fins protrude from the substrate 200, ¶ [0087]); and
a first pull-up (PU) transistor (Fig. 3D, top PU, ¶¶ [0090] & [0172]), a second PU transistor (Fig. 3D, bottom PU, ¶¶ [0090] & [0172]), a first dielectric structure (Fig. 3D, 2071, ¶ [0145]), and a second dielectric structure (Fig. 3D, 2072, ¶ [0145]) arranged in the first direction and sharing a second active area (Fig. 3D, 2012 + 2013, ¶ [0087]) protruding from the material layer (Fig. 4C, Wang’s fins protrude from the substrate 200, ¶ [0087]), wherein:
the first PU transistor and the first PD transistor share a first gate structure (Fig. 3D, 208b, ¶ [0174]) extending in a second direction perpendicular to the first direction;
the second PU transistor and the second PD transistor share a second gate structure (Fig. 3D, 208a, ¶ [0174]) extending in the second direction;
the first dielectric structure and a third gate structure (Fig. 3D, 208c, ¶ [0177]) of the first PG transistor extend in the second direction and are aligned with each other in the second direction (Fig. 3D); and
the second dielectric structure and a fourth gate structure (Fig. 3D, 208d, ¶ [0178]) of the second PG transistor extend in the second direction and are aligned with each other in the second direction (Fig. 3D),
However, Wang does not explicitly teach that the first dielectric structure is separated from the first gate structure and the second gate structure.
However, Liaw is a pertinent art that teaches the first dielectric structure (Fig. 5, 14, ¶ [0027]) is separated (Fig. 6, each metal gate electrode 134 is separated from isolation structures 14 by gate spacers 116 (¶ [0031])) from the first gate structure (Fig. 4, left 134, ¶ [0031]) and the second gate structure (Fig. 4, right 134, ¶ [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s device according to the teaching of Liaw (Fig. 5) in order to electrically separate various active regions (Liaw ¶ [0027]).
Regarding claim 3, Wang modified by Liaw teaches the memory device of claim 1, wherein the first dielectric structure (Fig. 3D, 2071, ¶ [0145]) is separated (Fig. 6, each metal gate electrode 134 is separated from isolation structures 14 by gate spacers 116 (¶ [0031]))from the third gate structure (Fig. 3D, 208c, ¶ [0177]) in the second direction (horizontal from the view of Fig. 3D) and the second dielectric structure (Fig. 3D, 2072, ¶ [0145]) is separated from the fourth gate structure (Fig. 3D, 208d, ¶ [0178]) in the second direction.
Claim 4 is rejected under 35 U.S.C. 103 as being obvious over WANG (Foreign Pub. No. CN 110571195 A (English translation attached)) in view of LIAW et al. (US Pub. No. 2021/0202498) and further in view of LIAW’15 (US Pub. No. 2015/0243667)
Regarding claim 4, Wang modified by Liaw teaches the memory device of claim 1.
However, Wang modified by Liaw does not explicitly teach a node conductor extending in the first direction and between the active area and the second active area in a top view, wherein the node conductor is electrically coupled to a source/drain feature between the second PU transistor and the second dielectric structure.
However, Liaw’15 is a pertinent art that teaches a node conductor (Fig. 5, Storage-node bar) extending in the first direction (Fig. 5, Liaw’15’s storage node bar extends in at least the horizontal and vertical directions) and between the first active area (Fig. 5, 222A + 224A, ¶ [0033]) and the second active area (Fig. 5, 226A + 228A. ¶ [0033]) in a top view, wherein the node conductor is electrically coupled to a source/drain feature (Fig. 5, the location of Liaw’15’s storage node bar corresponds to the location of Wang’s source and drains) between the second PU transistor (Fig. 5, PU-2, ) and the second dielectric structure (the space between Liaw’15’s gates 236A and 234A (¶ [0033]) would correspond to the location of Wang’s insulating layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang modified by Liaw’s device to further comprise additional node conductors according to the teaching of Liaw’15 (Fig. 5) in order to connect SRAM cells to peripheral logic circuits while improving device manufacturability (Liaw’15 ¶¶ [0041]-[0042]).
Claim 11 is rejected under 35 U.S.C. 103 as being obvious over WANG (Foreign Pub. No. CN 110571195 A (English translation attached)) in view of LIAW et al. (US Pub. No. 2021/0202498) and further in view of YIN et al. (US Pub. No. 2017/0018302).
Regarding claim 11, Wang modified by Liaw teaches the memory device of claim 1, and Wang teaches:
a first SRAM cell (Fig. 3D) comprises the first PD transistor (Fig. 3D, top right PD, ¶¶ [0090] & [0172]), the second PD transistor (Fig. 3D, bottom left PD, ¶¶ [0090] & [0172]), the first PG transistor (Fig. 3D, top left PG, ¶¶ [0090] & [0172]), the second PG transistor (Fig. 3D, top right PG, ¶¶ [0090] & [0172]), the first PU transistor (Fig. 3D, top PU, ¶¶ [0090] & [0172]), and the second PU transistor (Fig. 3D, bottom PU, ¶¶ [0090] & [0172]);
However, Wang modified by Liaw does not explicitly teach that the memory device further comprises a second SRAM cell that is adjacent to and a mirror image of the first SRAM cell with respect to an axis along the second direction, wherein the first active area and the second active area extend continuously from the first SRAM cell to the second SRAM cell.
However, Yin is a pertinent art that teaches the memory device (Fig. 2) further comprises a second SRAM (Fig. 2, 100b, ¶ [0026]) cell that is adjacent to and a mirror image of the first SRAM cell (Fig. 2, 100a, ¶ [0026]) with respect to an axis along the second direction (Fig. 2, D2, ¶ [0026]), wherein the first active area (Fig. 2, AR1, ¶ [0017]) and the second active area (Fig. 2, AR2, ¶ [0017]) extend continuously from the first SRAM cell to the second SRAM cell (Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang modified by Liaw’s memory device according to the teaching of Yin (Fig. 2) in order to arrange the SRAM units more densely (Yin ¶ [0026]).
Claim 21 is rejected under 35 U.S.C. 103 as being obvious over WANG (Foreign Pub. No. CN 110571195 A (English translation attached)) in view of BAO et al. (US Pub. No. 2022/0108983).
Regarding independent claim 21, Wang teaches a memory device, comprising:
a first NMOS transistor (Fig. 3D, top right PD, ¶¶ [0090], [0121] & [0172]), a second NMOS transistor (Fig. 3D, bottom left PD, ¶¶ [0090], [0121] & [0172]), a third NMOS transistor (Fig. 3D, top left PG, ¶¶ [0090], [0121] & [0172]), and a fourth NMOS transistor (Fig. 3D, top right PG, ¶¶ [0090], [0121] & [0172]) arranged in a first direction (vertical in the view of Fig. 3D) and share a first active area (Fig. 3D, 2011 + 2014, ¶ [0087]); and
a first PMOS transistor (Fig. 3D, top PU, ¶¶ [0090], [0120] & [0172]), a second PMOS transistor (Fig. 3D, bottom PU, ¶¶ [0090] & [0172]), a first dielectric structure (Fig. 3D, 2071, ¶ [0145]), and a second dielectric structure (Fig. 3D, 2072, ¶ [0145]) arranged in the first direction and sharing a second active area (Fig. 3D, 2012 + 2013, ¶ [0087]), wherein
the first active area and the second active area arranged in a second direction perpendicular (horizontal in the view of Fig. 3D) to the first direction;
wherein the first active area is separated from the second active area (Figs. 3D & 4A-4C, Wang’s fins 2011, 2012, 2013, and 2014 are all horizontally separated from each other by the isolation structure 210 (¶ [0097])) in the second direction;
a first gate structure (Fig. 3D, 208b, ¶ [0174]) extending across the first active area and aligned with the first dielectric structure in the second direction (Fig. 3D);
a second gate structure (Fig. 3D, 208a, ¶ [0174]) extending across the first active area and the second active area in the second direction;
a third gate structure (Fig. 3D, 208c, ¶ [0177]) extending across the first active area and the second active area in the second direction; and
a fourth gate structure (Fig. 3D, 208d, ¶ [0178]) extending across the first active area and aligned with the second dielectric structure in the second direction (Fig. 3D).
However, Wang does not explicitly teach that the first active area comprises first channel layers, second channel layers, third channel layers, and fourth channel layers; wherein the second active area comprises fifth channel layers and sixth channel layers;
However, Bao is a pertinent art that teaches the first active area comprises first channel layers (Fig. 5H, 508 + 510, ¶ [0057] teaches a plurality of nanosheets that would act as the active area for Bao’s device), second channel layers, third channel layers, and fourth channel layers; wherein the second active area comprises fifth channel layers and sixth channel layers (Wang modified by Bao would have a plurality of Bao’s nanosheets in each of Wang’s gate structures and would therefore fulfill this limitation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s device to include a stacked nanosheet structure according the teaching of Bao (Fig. 5H) in order to increase density and performance (Bao ¶ [0020]).
Claim 22 is rejected under 35 U.S.C. 103 as being obvious over WANG (Foreign Pub. No. CN 110571195 A (English translation attached)) in view of BAO et al. (US Pub. No. 2022/0108983) and further in view of NELSON et al. (US Pub. No. 2018/0219015).
Regarding claim 22, Wang teaches the memory device of claim 21.
However, Wang does not explicitly teach a power supply conductor extending in the second direction and under the second gate structure and the third gate structure, wherein the power supply conductor is electrically coupled to a source/drain feature between the second gate structure and the third gate structure.
However, Nelson is a pertinent art that teaches a power supply conductor (Fig. 3, 380, ¶ [0035]) extending in the second direction and under the second gate structure (Fig. 3, 320, ¶ [0033]) and the third gate structure (Fig. 3, 330, ¶ [0033]), wherein the power supply conductor is electrically coupled to a source/drain (Fig. 3, 324, ¶ [0033]) feature between the second gate structure and the third gate structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s memory device according to the teaching of Nelson (Fig. 3) in order to improve signaling characteristics (Nelson ¶ [0035]).
Allowable subject matter
Claims 2, 9, and 10 are objected to as being dependent upon a rejected base claim (claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
With respect to dependent claim 2, the cited prior art does not anticipate or make obvious, inter alia, the step of: “the first dielectric structure is in contact with the third gate structure and the second dielectric structure is in contact with the fourth gate structure”.
With respect to dependent claim 9, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the first dielectric structure and the second dielectric structure extend continuously from the first SRAM cell to the second SRAM cell”.
Claim 10 is dependent on claim 9.
Claims 12-14, 17, and 18 are allowed.
The following is an examiner' s statement of reasons for allowance:
⦁ Regarding independent claim 12, none of the prior art of record teaches or suggests, alone or in combination, a top surface of the first dielectric structure and a top surface of the second dielectric structure are higher than top surfaces of the source/drain features; and a dielectric layer under the second active area, the first dielectric structure and the second dielectric structure, wherein the first dielectric structure and the second dielectric structure interface with the dielectric layer, wherein the second gate structure and the third gate structure are between the first dielectric structure and the second dielectric structure in the first direction, wherein the first dielectric structure is aligned with the first gate structure in the second direction and the second dielectric structure is aligned with the fourth gate structure in the second direction, in combination with the remaining limitations of independent claim 12.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
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/R.P.S./
Examiner, Art Unit 2813
/KHAJA AHMAD/Primary Examiner, Art Unit 2813