DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed December 29th, 2025. Claims 1-3, 7, 11-17 and 19-27 are pending, of which claims 11-16 are currently rejected. Claims 4-6, 8-10, 18 have been cancelled by Applicant.
Response to Arguments
The amendment filed December 29th, 2025 has been entered. Claims 1-3, 5-7, 11-17 and 19-27 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every claim objection previously set forth in the Non-Final Office Action mailed September 10th, 2025.
Claim Objections
Applicant has amended the claims to address the objections as previously set forth in the Office Action mailed September 10th, 2025. Therefore, the previous objections to the Claims have been withdrawn.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are persuasive. Therefore, new grounds of rejection as necessitated by amendments have been made.
See Claim Rejections - 35 USC § 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Palchaudhuri et al. ("Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations", 2017) (hereinafter “Palchaudhuri”) in view of Llamocca et al. (“Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic”, 2010) (hereinafter “Llamocca”).
Regarding claim 11, Palchaudhuri teaches:
A device, comprising:
a clock circuit configured to provide clock signals (Palchaudhuri: Pg. 531 Fig. 7 shared clock signal between registers i.e., parallel clock input);
first adder circuits configured to receive input signals and provide a first sequence of adder sums based on the input signals (Palchaudhuri: Pg. 531 Fig. 8 Stage 1 adders of pipelined adder tree to provide a first sequence of adder sums); and
first register circuits, each of the first register circuits connected to an adder circuit of the first adder circuits to receive at least one adder sum of the first sequence of adder sums from the adder circuit (Palchaudhuri: Pg. 531 Fig. 8 pipeline registers at green boxes collect output of first stage adders, the output being a first sequence of sums), wherein the first register circuits are configured to be clocked in parallel by the clock signals to clock in the first sequence of adder sums (Palchaudhuri: Pg. 531 Fig. 8 registers after stage 1 adders; Fig. 7 shows shared clock signal between registers to provide a parallel clock input).
Palchaudhuri does not explicitly teach:
wherein the clock circuit clocks register circuits situated at different adder tree levels in parallel at the same time.
However, Llamocca teaches register circuits at different levels of the adder tree (Llamocca: Pg. 5 Fig. 3 as shown below, each level of registers being indicated with an arrow) being clocked in parallel at the same time (Llamocca: Pg. 8 Col. 1 Lines 3-4 entire PPC is clocked at 300 MHz and all peripherals run at 100 MHz, meaning all registers are clocked at the same time across all levels of the adder tree).
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It would be obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the clocking pattern across all adder tree levels as taught by Llamocca with the clock circuit, first adder circuit, first register circuits as taught by Palchaudhuri as both teachings are directed towards adder tree configurations within an FPGA environment. One with ordinary skill in the art would be motivated to combine the teachings because having less clocks to run the system would result in a smaller hardware footprint (Llamocca: Pg. 3 Col. 1 last paragraph).
Regarding claim 13, Palchaudhuri in view of Llamocca further teaches:
The device of claim 11, comprising:
second adder circuits configured to receive the first sequence of adder sums from the first register circuits and provide a second sequence of adder sums based on the first sequence of adder sums (Palchaudhuri: Pg. 531 Fig. 8 first stage adders produce a first sequence of adders that are provided through first register circuits to second stage adders to produce a second sequence of sums based on the first sequence of sums); and
second register circuits, each of the second register circuits connected to an adder circuit of the second adder circuits to receive at least one adder sum of the second sequence of adder sums from the adder circuit of the second adder circuits, wherein the second register circuits are configured to be clocked in parallel by the clock signals to sequentially clock in the second sequence of adder sums (Palchaudhuri: Pg. 531 Fig. 8 second register circuits store second sequence of sums from stage 2 adders; Fig. 7 shared clock signal between registers i.e., parallel clock input).
Regarding claim 14, Palchaudhuri in view of Llamocca further teaches:
The device of claim 13, comprising a third adder circuit configured to receive the second sequence of adder sums from the second register circuits and provide a third sequence of adder sums (Palchaudhuri: Pg. 531 Fig. 8 third stage adder to take in second sequence of sums from second register circuits and provide a third sequence of sums).
Regarding claim 15, Palchaudhuri in view of Llamocca teaches clocking of register circuits for an adder tree having full adders including 6 bit and 7 bit full adders (Palchaudhuri: Pg. 531 Col. 2 Section 2.2.1 Lines 1-2 each ADD block is a 24-bit adder which can act as an adder of smaller bit-width i.e., a 6 bit or 7 bit full adder by grounding unneeded inputs as is known in the art; Pg. 531 Col. 2 Section 2.2 adders are full adders).
Regarding claim 16, Palchaudhuri in view of Llamocca teaches clocking of register circuits for an adder tree having full adders including 8 bit, 9 bit, and 10 bit full adders (Palchaudhuri: Pg. 531 Col. 2 Section 2.2.1 Lines 1-2 each ADD block is a 24-bit adder which can act as an adder of smaller bit-width i.e., 8 bit, 9 bit, or 10 bit full adder by grounding unneeded inputs as is known in the art; Pg. 531 Col. 2 Section 2.2 adders are full adders).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Palchaudhuri in view of Llamocca, further in view of Langhammer.
While Palchaudhuri in view of Llamocca teaches the device of claim 11, Palchaudhuri in view of Llamocca does not explicitly teach inputs to adders being provided by multiplexers.
However, Langhammer teaches multiplexers being used to direct operands from registers to adder circuitries (Langhammer: Col. 4 Lines 53-67).
It would be obvious to combine the multiplexers to provide inputs to the adders as taught by Langhammer with the device as taught by Palchaudhuri in view of Llamocca as all teachings are directed towards efficient arithmetic computation. The improvement of Langhammer lies in reducing the need to use resources from outside the computation area, therefore reducing latency (Langhammer: Col. 1 Lines 43-48).
Allowable Subject Matter
Claims 1-3, 7, 17 and 19-27 are allowed. The following is a statement of reasons for the indication of allowable subject matter.
Applicant claims a device as in claim 1 comprises:
a first adder having first adder input terminals and first adder output terminals, the first adder receives a first group of first input values at the first adder input terminals during a first clock cycle, and a first group of second input values at the first adder input terminals during a second clock cycle;
a second adder having second adder input terminals and second adder output terminals, the second adder receives a second group of first input values at the second adder input terminals during the first clock cycle and a second group of second input values at the second adder input terminals during the second clock cycle,
a first register having first register input terminals and first register output terminals, the first register input terminals coupled to the first adder output terminals, the first register stores a first summation result of the first group of first input values during the second clock cycle;
a second register having second register input terminals and second register output terminals, the second register input terminals coupled to the first adder output terminals, the second register stores a first summation result of the first group of second input values during a third clock cycle;
a third register having third register input terminals, and third register output terminals, the third register input terminals coupled to the second adder output terminals, the third register stores a second summation result of the second group of first input values during the second clock cycle;
a fourth register having fourth register input terminals and fourth register output terminals, the fourth register input terminals coupled to the second adder output terminals, the fourth register stores a second summation result of the second group of second input values during the third clock cycle;
a third adder having third adder input terminals and third adder output terminals and configured to receive register output signals from the first register output terminals, the second register output terminals, the third register output terminals, and the fourth register output terminals at the third adder input terminals,
wherein the third adder calculates a first sum of the first summation result of the first group of first input values from the first register and the second summation result of the second group of first input values from the third register during the third clock cycle and the third adder calculates a second sum of the first summation result of the first group of second input values from the second register and the second summation result of the second group of second input values from the fourth register during a fourth clock cycle.
Vasilyev et al. (US 2018/0329685 A1) (hereinafter “Vasilyev”) teaches a device with a first adder (Vasilyev: Fig. 14 ALU that is expanded upon in Fig. 5, Fig. 5 element 501 as first adder with input and output terminals; ¶ 0102 several inputs obtained from each of the registers R1 through R5, including first, second, third and fourth inputs for summation), first register (Fig. 14 R2 as first register, that is coupled to ALU, in Fig. 5 output of 501 is sent to register as discussed in ¶ 0102 and registers may be written to i.e., for computed sums or read from i.e., for operands at any point), second register (Fig. 14 R3 as second register, that is coupled to ALU, in Fig. 5 output of 501 is sent to register as discussed in ¶ 0102 and registers may be written to i.e., for computed sums or read from i.e., for operands at any point), second adder (Fig. 5 is expanded view of ALU from Fig. 14, Fig. 5 element 502 as second adder with input and output terminals) and first adder to calculate a first sum and second sum (¶ 0052 operation of instant ALU may occur as is done with ALU of Fig. 4; ¶ 0041 first adder computes sum of first two input values; ¶ 0050 dual input ALU, first and second inputs on first computation process/cycle, third and fourth inputs on second computation process/cycle; ¶ 0102 registers may be written to or read from at any point, operands i.e., sums may be stored in registers of register space). Vasilyev is silent as to a third adder, a third register or a fourth register as well as the various corresponding clock cycles of the various operations.
Palchaudhuri teaches a first and second adder, and first and third register circuits for storing sums of adders in the adder tree (Pg. 531 Fig. 8 stage 1 adders of pipelined adder tree and various levels of registers in order to store sums). Palchaudhuri is silent as to a second register to collect a summation of second input values from the first adder, and a fourth register to collect a summation of second input values from a second adder.
Llamocca teaches an adder tree structure with layers of registers between the adders, as well as clocking registers in parallel (Llamocca: Pg. 5 Fig. 3 as shown below, each level of registers being indicated with an arrow) being clocked in parallel at the same time (Llamocca: Pg. 8 Col. 1 Lines 3-4 entire PPC is clocked at 300 MHz and all peripherals run at 100 MHz, meaning all registers are clocked at the same time across all levels of the adder tree). Llamocca is silent as to a second register to collect a summation of second input values from the first adder, and a fourth register to collect a summation of second input values from a second adder.
Hartley et al. (5084834) (hereinafter “Hartley”) teaches a digital-serial linear combining apparatus that uses clocked registers to provide operands to a digit-serial signal adder tree. Although Hartley teaches an adder tree and registers, Hartley is silent as to the specific structure as claimed in claim 1.
C. Fan et al., (“A hierarchical multiplier-free architecture for HEVC transform”, 2015) (hereinafter “Fan”) teaches a hierarchical multiplier-free architecture that comprises an adder tree with registers between each level of adders for carrying out a multiplication operation (Pg. 1002 Fig. 3). Fan is silent as to a first and second register to store summation operations results from a first adder based on first and second group of input values.
Claims 2-3, 7, and 21-24, dependent on claim 1, are therefore also allowable.
Claims 17, 19-20, and 25-27 are allowable for the same reasons as claims 1-3, 7, and 21-24.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151