DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated February 3, 2026, in which no claims were amended has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-7, and 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chandhok (U.S. Pub. 2020/0090987).
Regarding claims 1-3 and 6-7, Chandhok [Figs.1A-J’] discloses an integrated circuit structure, comprising:
a plurality of conductive lines [110] in a dielectric layer [104], individual ones of the plurality of conductive lines along a direction and spaced at a same interval [Figs.1A-C]; and
a conductive structure [110’] in the dielectric layer, the conductive structure laterally between but not in contact with a pair of the plurality of conductive lines [Fig.1F,1J’];
further comprising a conductive via [via portion of 128’] above and coupled to the conductive structure [110’] [Fig.1J’];
further comprising a conductive line [trench portion of 128’] above and coupled to the conductive via, the conductive line along a direction orthogonal to the direction of the plurality of conductive lines [Fig.1J’].
Regarding claims 6-7, Chandhok [Figs.1A-J’] discloses an integrated circuit structure, comprising:
wherein the conductive structure is a rerouting signal line [In reference to the claim language referring to “a rerouting signal line”, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In the instant case, the conductive structure [110’] of Chandhok is capable of being a rerouting signal line.];
wherein the conductive structure is fabricated by an inline circuit edit process [In reference to the limitation “fabricated by an inline circuit edit process”, the language describes the conductive structure as formed by a method.] See MPEP 2113. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). [The resulting conductive structure of the claim is met by the conductive structure [110’] of Chandhok.].
Regarding claims 11-15, Chandhok [Figs.1,8] discloses a computing device, comprising:
a board [802] [Fig.8]; and
a component coupled to the board, the component [804,806] including an integrated circuit structure [Figs.1J’], comprising:
a plurality of conductive lines in a dielectric layer, individual ones of the plurality of conductive lines along a direction and spaced at a same interval; and
a conductive structure in the dielectric layer, the conductive structure laterally between but not in contact with a pair of the plurality of conductive lines [Discussed above in the treatment of Claim 1];
further comprising: a memory [DRAM] coupled to the board [Fig.8];
further comprising: a communication chip [806] coupled to the board;
wherein the component is a packaged integrated circuit die [804,806];
wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor [Fig.8].
Regarding claims 16-20, Chandhok [Figs.1,8] [Discussed above in the treatment of claims 11-15] discloses a computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
forming a plurality of conductive lines in a dielectric layer using a masked lithography process, individual ones of the plurality of conductive lines along a direction and spaced at a same interval; and
forming a conductive structure in the dielectric layer using a maskless lithography process, the conductive structure laterally between but not in contact with a pair of the plurality of conductive lines;
[In reference to the limitations “the integrated circuit structure fabricated according to a method comprising… forming a plurality of conductive lines in a dielectric layer using a masked lithography process… forming a conductive structure in the dielectric layer using a maskless lithography process”, the language describes the claimed structure as formed by a method.] See MPEP 2113. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). [The resulting claimed conductive lines and conductive structures are met by the conductive lines and conductive structures of Chandhok.];
further comprising: a memory coupled to the board [Discussed above in the treatment of claims 11-15];
further comprising: a communication chip coupled to the board [Discussed above in the treatment of claims 11-15];
wherein the component is a packaged integrated circuit die [Discussed above in the treatment of claims 11-15];
wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor [Discussed above in the treatment of claims 11-15].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandhok (U.S. Pub. 2020/0090987) in view of Lin (U.S. Pub. 2021/0097228).
Regarding claim 4, Chandhok discloses wherein the conductive structure [110’] has a bottommost surface above a bottommost surface of at least some of the plurality of conductive lines [110] [Fig.1H]. However, Lin [Fig.4] discloses and makes obvious an integrated circuit structure wherein the conductive structure [342] has a bottommost surface above a bottommost surface of the plurality of conductive lines [341,343]. It would have been obvious to provide the relative heights of the conductive structure as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandhok (U.S. Pub. 2020/0090987) in view of Jeng (U.S. Pub. 2019/0139895).
Regarding claim 5, Chandhok fails to explicitly disclose wherein the conductive structure has a width less than a width of individual ones of the plurality of conductive lines, the width along a direction orthogonal to the direction of the plurality of conductive lines. However, Jeng [Fig.1M] discloses and makes obvious an integrated circuit structure wherein the conductive structure [L2] has a width less than a width of individual ones of the plurality of conductive lines [L3,L4], the width along a direction orthogonal to the direction of the plurality of conductive lines. It would have been obvious to provide the relative widths of the conductive structure as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BAC H AU/Primary Examiner, Art Unit 2898
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