Prosecution Insights
Last updated: April 19, 2026
Application No. 17/743,948

INLINE CIRCUIT EDIT

Final Rejection §102§103
Filed
May 13, 2022
Examiner
AU, BAC H
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
92%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
660 granted / 817 resolved
+12.8% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
31 currently pending
Career history
848
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
48.8%
+8.8% vs TC avg
§102
29.6%
-10.4% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 817 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s response dated February 24, 2026, in which no claims were amended, cancelled, or added, has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 5, 11, and 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mignot et al. (U.S. Pub. 2022/0005762), hereafter “Mignot”. Regarding claim 1, Mignot [Fig.8] discloses an integrated circuit structure, comprising: a first conductive line [M1] and a second conductive line [Trench portion above V0] in a first dielectric layer [114], the second conductive line laterally spaced apart from the first conductive line; and a first conductive via [152] and a second conductive via [Via structure on left edge, above trench portion above V0] in a second dielectric layer [120], the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via [152] vertically over and connected to the first conductive line [M1], and the second conductive via [Via structure on left edge, above trench portion above V0] vertically over but separated from the second conductive line [Fig.8]. Regarding claims 2, 3, and 5, Mignot [Fig.8] discloses an integrated circuit structure wherein the second conductive via [Via structure on left edge, above trench portion above V0] is separated from the second conductive line by a portion of the second dielectric layer [120]; wherein the second conductive via is separated from the second conductive line by an etch stop layer [118] between the first dielectric layer [114] and the second dielectric layer [120], and wherein the first conductive via [152] extends through the etch stop layer [Fig.8]; wherein the second conductive via is fabricated to be separated from the second conductive line by an inline circuit edit process [In reference to the limitation “…is fabricated to be separated from the second conductive line by an inline circuit edit process”, the language describes the structure as formed by a method.] See MPEP 2113. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). [The resulting product of the claim is the structure claimed, met by the second conductive via and the second conductive line of Mignot.]. Regarding claim 11, Mignot [Fig.8] [Para.49] discloses a computing device, comprising: a board [Para.49]; and a component coupled to the board, the component including an integrated circuit structure [100] [Para.26], comprising: a first conductive line [M1] and a second conductive line [Trench portion above V0] in a first dielectric layer [114], the second conductive line laterally spaced apart from the first conductive line; and a first conductive via [152] and a second conductive via [Via structure on left edge, above trench portion above V0] in a second dielectric layer [120], the second dielectric layer over the first dielectric layer [114], the second conductive via laterally spaced apart from the first conductive via, the first conductive via [152] vertically over and connected to the first conductive line [M1], and the second conductive via [Via structure on left edge, above trench portion above V0] vertically over but separated from the second conductive line [Fig.8]. Regarding claims 14-15, Mignot [Fig.8] [Para.49] discloses a computing device wherein the component is a packaged integrated circuit die [Fig.8] [Paras.26,49]; wherein the component is selected from the group consisting of a processor [Para.49], a communications chip, and a digital signal processor. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mignot et al. (U.S. Pub. 2022/0005762) in view of Gstrein et al. (U.S. Pat. 9754778), hereafter “Gstrein”. Regarding claims 12-13, Mignot [Para.49] discloses the resulting integrated circuit can be part an end product including a computing device, but fails to explicitly disclose the computing device further comprising: a memory coupled to the board; further comprising: a communication chip coupled to the board. However, Gstrein [Fig.8] discloses a computing device [1000] further comprising: a memory [DRAM] coupled to the board [1002]; further comprising: a communication chip [1006] coupled to the board. It would have been obvious to provide the memory and communication chip to the computing device as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Allowable Subject Matter Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of wherein the first conductive via is in a first via opening and the second conductive via is in a second via opening, and wherein a residual resist material is in the second via opening but not in the first via opening. Response to Arguments Applicant's arguments filed February 24, 2026, have been fully considered but they are not persuasive. Applicant asserts Examiner points to M2 line as reading on Applicant’s claimed “second via”. This assertion is respectfully traverses. As seen above as well as in the previous Office Action, Examiner clearly points to the via structure, “…a second conductive via [Via structure on left edge, above trench portion above V0] in a second dielectric layer [120]” in Fig.8 of Mignot. Line M2 in Fig.8 is located in the top right corner, not the “left edge, above the trench portion above V0”. As seen in Fig.8, both the trench portion above V0 and the via structure above the trench portion are on the left edge of the device in Fig.8. It is not understood where line M2 is even discussed in the Office Action, let alone being pointed to as reading on the claimed “second via” as asserted by Applicant. Applicant’s assertion is not persuasive. Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made Final. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BAC H AU/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

May 13, 2022
Application Filed
Mar 23, 2023
Response after Non-Final Action
Nov 15, 2025
Non-Final Rejection — §102, §103
Feb 24, 2026
Response Filed
Mar 22, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
92%
With Interview (+10.8%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 817 resolved cases by this examiner. Grant probability derived from career allow rate.

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