DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Final office action is in response to application 17/743,954, amendment and remarks filed on 11/07/2025. Claims 1, 6, 11 and 16 are currently amended and claim 2 is cancelled by Applicant. Claims 1 and 3-20 are currently pending in this application.
Response to Arguments
3. Applicant's arguments filed 11/07/2025 have been fully considered. The rejection of claims 1, 3-5, and 11-15 are withdrawn. With respect to claims 6-10 and 16-20, the amendment and remarks filed 11/07/2025 are not persuasive. Examiner’s response to Applicant’s remarks filed 11/07/2025 appears below:
4a. With respect to independent claim 6, and similarly recited independent claim 16, Applicant asserts, with reference to Kim’s Figure 4, that Kim does not disclose a conductive structure laterally between a plurality of conductive lines and in direct physical contact with a pair of the plurality of lines, as now recited in claims 6 and 16, respectively. Examiner respectfully disagrees.
4b. With respect to independent claim 6, and similarly recited independent claim 16, Examiner points out that Fig 6 of Kim discloses a plurality of conductive lines P21 and P22 with a conductive structure P11 laterally between conductive lines P21 and P22 as shown in Fig 6, where vias V1 and V2 physically connect conductive structure P11 to conductive lines P21 and P22. Therefore, KIM clearly discloses a conductive structure laterally between a plurality of conductive lines and in direct physical contact with a pair of the plurality of lines, as now recited in claims 6 and 16, respectively. Thus, Examiner maintains the rejections of independent claims 6 and 16, as Applicant’s amendment and remarks are not persuasive.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 6-7, 16 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by KIM (US PG Pub No. 2019/0122984).
7. With respect to independent claim 6, KIM teaches:
An integrated circuit structure (integrated circuit, Abstract; see semiconductor package, para 77), comprising:
a plurality of conductive lines along a direction and spaced at a same interval (see tracks of conductive layers, Abstract; conductive patterns, para 5; see conductive patterns and conductive layers, para 23 see conductive tracks in parallel on first conductive layer, and conductive patterns running along same direction, para 5; see conductive pattern along the track, para 29; tracks spaced apart each at regular intervals, para 30; see conducive patterns P21 and P22 of Fig 6 which are spaced apart, para 57); and
a conductive structure laterally between and in direct physical contact (see vias which connect lateral pattern P11 and conductive lines P21 and P22, Fig 6, para 57-58; see conductive structure/pattern P11 which is positioned laterally between conductive lines/patterns P21 and P22, see Fig 6 and para 57-58) with a pair of the plurality of conductive lines (laterally between conductive lines/patterns P21 and P22, see Fig 6 and para 57-58; see conductive patterns aligned with tracks, para 5; see conductive patterns aligned with track and between first and second conductive patterns, para 5).
8. With respect to claim 7, KIM teaches:
The integrated circuit structure of claim 6, wherein the conductive structure is in a location that violates a design rule of the plurality of conductive lines (see pitch between tracks determined according to design rules, para 30; conductive patterns in locations of design rule violation, para 30; conductive pattern may violate distance rules, para 59).
9. With respect to independent claim 16, KIM teaches:
A computing device (integrated circuit and package, Abstract; see semiconductor package, para 77), comprising:
a board (see board, IC package, para 77); and
a component coupled to the board, the component including an integrated circuit structure (see integrated circuit as a component in package, para 77), comprising:
a plurality of conductive lines along a direction and spaced at a same interval (see tracks of conductive layers, Abstract; conductive patterns, para 5; see conductive patterns and conductive layers, para 23 see conductive tracks in parallel on first conductive layer, and conductive patterns running along same direction, para 5; see conductive pattern along the track, para 29; tracks spaced apart each at regular intervals, para 30); and
a conductive structure laterally between and in direct physical contact ((see vias which connect lateral pattern P11 and conductive lines P21 and P22, Fig 6, para 57-58; see conductive structure/pattern P11 which is positioned laterally between conductive lines/patterns P21 and P22, see Fig 6 and para 57-58) with a pair of the plurality of conductive lines (see conductive patterns aligned with tracks, para 5; see conductive patterns aligned with track and between first and second conductive patterns, para 5).
10. With respect to claim 19, KIM teaches:
The computing device of claim 16, wherein the component is a packaged integrated circuit die (integrated circuit, Abstract; see semiconductor package, para 77; see board, IC package, para 77; see integrated circuit as a component in package, para 77).
11. With respect to claim 20, KIM teaches:
The computing device of claim 16, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (see KIM: dynamic array, functional chips as part of chip package, para 170-175).
Claim Rejections - 35 USC § 103
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
13. Claim(s) 9 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US PG Pub No. 2019/0122984) in view of Becker et al. (US PG Pub No. 2011/0161909).
14. With respect to claim 9, KIM fails to teach:
The integrated circuit structure of claim 6, wherein a location of the plurality of conductive lines is fabricated using a masked lithography process.
However, Becker teaches:
The integrated circuit structure of claim 6, wherein a location of the plurality of conductive lines is fabricated using a masked lithography process (see layer conductive structures manufactured using a optimized lithographic process, para 130-132).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Becker’s use of masked lithography into the invention of KIM because: (1) KIM’s use of masks suggests a lithography process for the addition of conductive structures, (2) Becker suggests that masked lithography can be used for conductive traces and tracks that will not need to be changed and/or cannot be edited during a circuit editing process.
15. With respect to claim 17, KIM fails to teach:
The computing device of claim 16, further comprising: a memory coupled to the board.
However, Becker teaches:
The computing device of claim 16, further comprising: a memory coupled to the board (see Becker: see memory region as part of circuit package, para 172).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Becker’s use memory for providing information/data on configuration of the chip architecture, which would provide an advantage to KIM by enabling KIM to store data on chip architecture and configuration details.
16. With respect to claim 18, while KIM fails to teach the limitations below, Becker teaches:
The computing device of claim 16, further comprising: a communication chip coupled to the board (see Becker: dynamic array, functional chips as part of chip package, para 170-175).
(for motivation to combine references, please see rejection of claim 17).
17. Claim(s) 8 and 10 and is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US PG Pub No. 2019/0122984) in view Gu et al. (US PG Pub No. 2005/0227484).
18. With respect to claim 8, Kim fails to teach:
The integrated circuit structure of claim 6, wherein a location of the conductive structure is fabricated using a maskless lithography process.
However, Gu teaches:
The integrated circuit structure of claim 6, wherein a location of the conductive structure is fabricated using a maskless lithography process (see editing circuit without need to modify lithography mask, para 4).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Gu’s circuit editing process into the invention of KIM/Becker for at least the following reason(s): Gu’s circuit editing process allows for changes to circuitry without having to re-create a circuit or reproduce a new mask, which is advantageous in the art because new circuit and mask production costs additional time and money.
19. With respect to claim 10, Kim fails to teach:
The integrated circuit structure of claim 6, wherein the conductive structure is fabricated by an inline circuit edit process.
However, Gu teaches:
The integrated circuit structure of claim 6, wherein the conductive structure is fabricated by an inline circuit edit process (see circuit editing process, para 8-9, 33, 56; creating a new conductive structure in space between conductors, para 56; see editing circuit without need to modify lithography mask, para 4).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Gu’s circuit editing process into the invention of KIM/Becker for at least the following reason(s): Gu’s circuit editing process allows for changes to circuitry without having to re-create a circuit or reproduce a new mask, which is advantageous in the art because new circuit and mask production costs additional time and money.
Allowable Subject Matter
20. Claims 1, 3-5 and 11-15 are allowed over the prior art of record.
21. With respect to independent claims 1 and 3-5, the prior art made of record fails to teach the combination of steps recited in claim 1, including the following particular combination of steps as recited in claim 1, as follows:
a white space track included within the plurality of line tracks, the white space track having a width along a second direction greater than a width of an individual one of the plurality of line tracks, the second direction orthogonal to the first direction; and
a conductive structure along the white space track, wherein the conductive structure comprises a conductive line over a pair of conductive vias, and wherein the conductive line of the conductive structure has a width along the second direction greater than a width of an adjacent one of the plurality of conductive structures along the second direction.
22. With respect to independent claims 11-15, the prior art made of record fails to teach the combination of steps recited in claim 11, including the following particular combination of steps as recited in claim 11, as follows:
a white space track included within the plurality of line tracks, the white space
track having a width along a second direction greater than a width of an individual one of the plurality of line tracks, the second direction orthogonal to the first direction; and
a conductive structure along the white space track, wherein the conductive
structure comprises a conductive line over a pair of conductive vias, and wherein the
conductive line of the conductive structure has a width along the second direction greater than a width of an adjacent one of the plurality of conductive structures along the second direction.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851