DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 17/743,954, RCE filed on 06/26/2026. Claims 6 and 16 are currently amended and claim 2 is cancelled by Applicant. Claims 1, 3-5 and 11-15 were previously indicated as allowable by Examiner in the Final office action mailed 03/26/2026, and is maintained herein. Claims 1 and 3-20 are currently pending in this application.
Response to Arguments
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/26/2026 has been entered.
4. Applicant's arguments filed 05/26/2026 have been fully considered.
With respect to Applicant’s remarks asserting that Kim fails to disclose the features of independent claims 6 and 16, those remarks have been considered but are moot because the new ground(s) of rejection for independent claims 6 and 16 no longer relies on any teaching from Kim with respect to matters specifically challenged in the argument.
5. With respect to dependent claims rejected in view of prior art references Becker and/or Gu, it does not appear that Applicant specifically challenged the teachings from those references in Applicant’s remarks filed 05/26/2026. Therefore, Examiner will treat Applicant’s remarks filed 05/26/2026, with respect to remarks made challenging the Kim reference alone, as moot in view of Examiner’s new ground(s) of rejection.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claim(s) 6 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Shin et al. (US PG Pub No. 2015/0145015).
8. With respect to independent claim 6, Shin teaches:
An integrated circuit structure (see interconnect structure, para 35; semiconductor memory device including cell array structure, para 2; semiconductor structure, para 77-80), comprising:
a plurality of conductive lines along a direction and spaced at a same interval (see Fig 4, conductive lines and/or structures VS/SP which appear as a pair on one side of structures WL/SSL and also appear on far side of these structures in Fig 4; vertical structures VS/SP are spaced apart in an interval with respect to the standard width of the structures between them, see Fig 4, para 45-52); and
a conductive structure laterally between and in direct physical contact with sidewalls of a pair of the plurality of conductive lines (see VS/SP structures having a sidewall which are in direct physical contact with structures WL/SSL/GSL which are disposed between the vertical structures VS/SP, see discussion of sidewall spacers and/or sidewall of conductive structure VS/SP, para 69-70; see electrical/conductive connection between BL structures and substrate via the VS/SP structures).
9. With respect to independent claim 16, Shin teaches:
A computing device (see interconnect structure, para 35; semiconductor memory device including cell array structure, para 2; semiconductor structure, para 77-80), comprising:
a board (see chip on board, in-line package, array package, para 136; where substrate 10 of Fig 4 can be a board for chip, or sit on a board as a chip-on-board structure, para 135-137); and
a component coupled to the board, the component including an integrated circuit structure (see 3D semiconductor memory device attached to chip-on-board substrate structure, as shown in Fig 4, para 40-46), comprising:
a plurality of conductive lines along a direction and spaced at a same interval (see Fig 4, conductive lines and/or structures VS/SP which appear as a pair on one side of structures WL/SSL and also appear on far side of these structures in Fig 4; vertical structures VS/SP are spaced apart in an interval with respect to the standard width of the structures between them, see Fig 4, para 45-52); and
a conductive structure laterally between and in direct physical contact with sidewalls of a pair of the plurality of conductive lines (see VS/SP structures having a sidewall which are in direct physical contact with structures WL/SSL/GSL which are disposed between the vertical structures VS/SP, see discussion of sidewall spacers and/or sidewall of conductive structure VS/SP, para 69-70; see electrical/conductive connection between BL structures and substrate via the VS/SP structures).
10. With respect to claim 17, Shin teaches:
The computing device of claim 16, further comprising:
a memory coupled to the board (see 3D semiconductor memory device attached to chip-on-board substrate structure, as shown in Fig 4, para 40-46).
11. With respect to claim 18, Shin teaches:
The computing device of claim 16, further comprising: a communication chip coupled to the board (see memory system including interface for communication network for sending/receiving from a communication network, para 132; see memory system including 3D semiconductor memory can be or include a microprocessor or digital signal processor, para 130).
12. With respect to claim 19, Shin teaches:
The computing device of claim 16, wherein the component is a packaged integrated circuit die (see packaged IC memory package/die, para 136).
13. With respect to claim 20, Shin teaches:
The computing device of claim 16, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (see memory system including 3D semiconductor memory can be or include a microprocessor or digital signal processor, para 130).
Claim Rejections - 35 USC § 103
14. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
15. Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US PG Pub No. 2015/0145015) in view of Becker et al. (US PG Pub No. 2011/0161909).
16. With respect to claim 7, Shin appears to be silent regarding:
The integrated circuit structure of claim 6, wherein the conductive structure is in a location that violates a design rule of the plurality of conductive lines.
However, Becker teaches:
The integrated circuit structure of claim 6, wherein the conductive structure is in a location that violates a design rule of the plurality of conductive lines (see design rules for metal tracks across device, and patterns from neighboring shapes that print improperly due to proximity and constraints, para 140-145; see semiconductor chip structure including structure including conductive lines on substrate, para 163; see design that violates these design rules, para 94).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Becker’s use of design rules, impacting conductive structures and their adjacency to neighboring structures and conductive lines, into the invention of Shin for at least the following reason(s): Shin’s semiconductor structure is improved by maintaining design criteria for the placement of conductive lines and traces to adjacent neighboring circuit structures by utilizing the design rule checking process as deployed in Becker, thus improving the semiconductor design and structure process of Shin.
17. With respect to claim 9, Shin fails to teach:
The integrated circuit structure of claim 6, wherein a location of the plurality of conductive lines is fabricated using a masked lithography process.
However, Becker teaches:
The integrated circuit structure of claim 6, wherein a location of the plurality of conductive lines is fabricated using a masked lithography process (see layer conductive structures manufactured using a optimized lithographic process, para 130-132).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Becker’s use of masked lithography into the invention of Shin because: (1) Shin’s use of wafer-level fabrication (Shin, para 136) and utilization of horizontal/vertical semiconductor layers (Shin, para 137) suggests a necessary and practically ubiquitous manufacturing/fabrication process for the addition/inclusion of conductive structures as taught by both Shin (conductivity type for semiconductor layers, Abstract; conductive patterns, para 46) and Becker (conductive segments, Abstract, para 8-10); and (2) Becker suggests that masked lithography can be used for conductive traces and tracks that is subject to changes and/or cannot be changed and/or cannot be edited during a circuit editing process.
18. Claim(s) 8 and 10 and is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US PG Pub No. 2015/0145015) in view Gu et al. (US PG Pub No. 2005/0227484).
19. With respect to claim 8, Shin fails to teach:
The integrated circuit structure of claim 6, wherein a location of the conductive structure is fabricated using a maskless lithography process.
However, Gu teaches:
The integrated circuit structure of claim 6, wherein a location of the conductive structure is fabricated using a maskless lithography process (see editing circuit without need to modify lithography mask, para 4).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Gu’s circuit editing process into the invention of Shin for at least the following reason(s): Gu’s circuit editing process allows for changes to circuitry without having to re-create a circuit or reproduce a new mask, which is advantageous in the art because new circuit and mask production costs additional time and money.
20. With respect to claim 10, Shin fails to teach:
The integrated circuit structure of claim 6, wherein the conductive structure is fabricated by an inline circuit edit process.
However, Gu teaches:
The integrated circuit structure of claim 6, wherein the conductive structure is fabricated by an inline circuit edit process (see circuit editing process, para 8-9, 33, 56; creating a new conductive structure in space between conductors, para 56; see editing circuit without need to modify lithography mask, para 4).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Gu’s circuit editing process into the invention of Shin for at least the following reason(s): Gu’s circuit editing process allows for changes to circuitry without having to re-create a circuit or reproduce a new mask, which is advantageous in the art because new circuit and mask production costs additional time and money.
Allowable Subject Matter
21. Claims 1, 3-5 and 11-15 are allowed over the prior art of record.
22. With respect to independent claims 1 and 3-5, the prior art made of record fails to teach the combination of steps recited in claim 1, including the following particular combination of steps as recited in claim 1, as follows:
a white space track included within the plurality of line tracks, the white space track having a width along a second direction greater than a width of an individual one of the plurality of line tracks, the second direction orthogonal to the first direction; and
a conductive structure along the white space track, wherein the conductive structure comprises a conductive line over a pair of conductive vias, and wherein the conductive line of the conductive structure has a width along the second direction greater than a width of an adjacent one of the plurality of conductive structures along the second direction.
23. With respect to independent claims 11-15, the prior art made of record fails to teach the combination of steps recited in claim 11, including the following particular combination of steps as recited in claim 11, as follows:
a white space track included within the plurality of line tracks, the white space
track having a width along a second direction greater than a width of an individual one of the plurality of line tracks, the second direction orthogonal to the first direction; and
a conductive structure along the white space track, wherein the conductive
structure comprises a conductive line over a pair of conductive vias, and wherein the
conductive line of the conductive structure has a width along the second direction greater than a width of an adjacent one of the plurality of conductive structures along the second direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
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