Prosecution Insights
Last updated: April 20, 2026
Application No. 17/744,374

OPTIMIZED PHASE CHANGE MEMORY STRUCTURE TO IMPROVE NUCLEATION TIME VARIATION

Non-Final OA §102§103§112
Filed
May 13, 2022
Examiner
GEBREMARIAM, SAMUEL A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
685 granted / 825 resolved
+15.0% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
19 currently pending
Career history
844
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
36.5%
-3.5% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 825 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 11-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/03/2025. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is unclear how a contact angle of heterogeneous nucleation is calculated and it is further unclear how the angle is measured. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Breitwisch et al., US 2009/0196094. Regarding claim 1, Breitwisch discloses (fig. 3A and related text) a memory device comprising an array of memory cells ([0004], [0045]) including layers of material, comprising: a first electrode layer (202); a phase change material (PCM) layer (208), having a first interface (fig. 3A) with the first electrode layer comprising a first electrode/PCM interface (fig. 3A); and a second electrode layer (210), having a second interface with the phase change material layer (208) comprising a PCM/second electrode interface (fig. 3A); wherein the first electrode/PCM interface and the PCM/second electrode interface are non-flat (3A) and configured to reduce statistical variation of nucleation time (since Breitwisch teaches the same structure as claimed hence Breitwisch structure is capable of being configured to reduce statistical variation of nucleation time as claimed). Regarding claim 17, Breitwisch discloses (figs. 1-2 and 3A and related text) a system comprising: a memory controller (fig. 2); and a memory device (106a-…106d), communicatively coupled with the memory controller (fig. 2), including an array of memory cells (fig. 2) including layers of material, comprising: a first electrode layer (202); a phase change material (PCM) layer (208), having a first interface (fig. 3A) with the first electrode layer (202) comprising a first electrode/PCM interface (fig. 3A); and a second electrode layer (210), having a second interface with the phase change material layer (208) comprising a PCM/second electrode interface (fig. 3A); wherein the first electrode/PCM interface and the PCM/second electrode interface are non-flat (fig. 3A) and configured to reduce statistical variation of nucleation time (since Breitwisch teaches the same structure as claimed hence Breitwisch structure is capable of being configured to reduce statistical variation of nucleation time as claimed). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-3, 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Breitwisch. Regarding claim 2, Breitwisch does not disclose . (Original) The memory device of claim 1, wherein the layers of materials are formed using a deposition process and wherein at least one of the first electrode/PCM interface and the PCM/second electrode interface comprises a serrated or rough surface with a root mean square (RMS) range of 0.3-3 nanometers introduced by a dry etch or ion treatment after deposition of the first electrode layer and before deposition of the second electrode layer. Regarding claim 3, Breitwisch discloses the first electrode/PCM interface and the PCM/second electrode interface comprises patterned structures (fig. 3A). However, Breitwisch does not explicitly disclose having a feature size of 0.3-3 nanometers. Parameters such as feature size in the art of semiconductor process are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize an appropriate feature size appropriate for the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233. The limitation “the layers of materials are formed using a deposition process and wherein at least one of formed by lithography or etching” is considered a product-by-process claim. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Regarding claim 9, Breitwisch does not explicitly disclose the memory device comprises a three-dimensional (3D memory device) having a plurality of decks, each comprising the layer structure of claim 1. However, a functioning memory device requires designing a three-dimensional memory device. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to design a three-dimensional appropriate for the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233. Regarding claim 19, Breitwisch discloses the first electrode/PCM interface and the PCM/second electrode interface comprises patterned structures (fig. 3A). However, Breitwisch does not explicitly disclose having a feature size of 0.3-3 nanometers. Parameters such as feature size in the art of semiconductor process are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize an appropriate feature size appropriate for the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233. The limitation “the layers of materials are formed using a deposition process and wherein at least one of formed by lithography or etching” is considered a product-by-process claim. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Allowable Subject Matter Claims 4-8, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

May 13, 2022
Application Filed
Feb 06, 2023
Response after Non-Final Action
Dec 13, 2025
Non-Final Rejection — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+8.9%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 825 resolved cases by this examiner. Grant probability derived from career allow rate.

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