DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 01 June 2026 has been entered. Claims 1-4, 6-26 remain pending in the application.
Interview
Examiner attempted to contact Applicant to coordinate an interview to incorporate allowable subject matter into the independent claims and discuss the drawings.
Drawings
The drawings are objected to because they fail to comply with CFR 1.84(a)(1) and (p)(1) as Figs. 2-10 contain lines, reference numbers, and words that are illegible and not secured by black ink. Special attention to those letters and number in subscripts.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the respective portions" of the S/H capacitor in line 13, p. 6. There is insufficient antecedent basis for this limitation in the claim. Claims 15-20 inherit the deficiency by reasons of dependence, and are similarly rejected.
The term “substantially equal” in claim 21 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear to what “substantial” degree of “equality” each segment’s total capacitance needs to achieve. For example, the metes and bounds of the claim are indefinite as it is unclear if equality could be achieved if the total capacitance of each segment is within a certain range of difference that it would be considered substantially equal, if when the circuit is active the effective total capacitance of each segment at certain points of execution is equal, or other.
Claim 22 recites the limitation "the analog input voltages" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 23 recites the limitation "the first capacitance portion" in line 1 and “the plurality of capacitor segments” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 24 recites the limitation "the first capacitance portion" in lines 1-2, “the second capacitance portions” in lines 2-3, and “the reference voltage” in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 25 recites the limitation "the second capacitance portion" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-11, 14-16, 18-26 are rejected under 35 U.S.C. 103 as being unpatentable over US 20210158854 A1 Sinangil (hereinafter “Sinangil”) in view of US 10447291 B1 Thomas (hereinafter “Thomas”) .
Regarding claim 1, Sinangil teaches:
Apparatus (Fig. 2A, 200, [0035]) for scaling and summing ([0018], [0026]) a plurality of weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), wherein each analog signal comprises a voltage associated with a respective plurality of coupled bit-cell outputs (Fig. 1, 110, [0023]) within an in-memory computing (IMC) array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]), the apparatus comprising:
a plurality of signal divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]), each signal divider circuit (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026]) configured to process a respective weighted-data-representative analog signal to produce an output signal (Figs. 3A & 3B, 228, [0041]) having a value scaled in accordance with the respective weighting value (Figs. 2A & 3A & 3B, 222, 224, [0026-0030]); and
an analog to digital converter (ADC) (Figs. 3A & 3B & 4, 270, [0046]);
wherein, during a measurement phase of operation (Fig. 5, 530, 540, [0052-0053], [0055]), the corresponding output signals (Figs. 3A & 3B, 228, [0041]) to provide an accumulated analog signal for digitization by the ADC ([0059]), the ADC configured to generate therefrom a digital output representing a summation of the weighted-data-representative analog signals (Figs. 3A & 3B & 4, output from 270, [0046]; Fig. 3B referred to as NOUT[3:0]; Fig. 2A, 64 4-bit outputs NOUT0[3:0] to NOUT15[3:0], [0029]).
Although Sinangil discloses an analog to digital converter (ADC), they appear to be silent to disclose a sample-and-hold (S/H) capacitor network integrated within the ADC; signals are sampled onto respective portions of the S/H capacitor network and are combined within the S/H capacitor network.
Thomas discloses a sample-and-hold (S/H) capacitor network integrated within (Fig. 1 “22” co. 3 ln. 54-67, co. 4 ln. 1-13 with selected capacitors “38A-E” co. 4 ln. 51-64) the ADC; signals are sampled onto respective portions of the S/H capacitor network and are combined within the S/H capacitor network (co. 4 ln. 25-42).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil with Thomas’ sample-and-hold (S/H) capacitor network in the SAR ADC circuit because they are in the claimed invention’s same field of endeavor of analog to digital converters (co. 1, lines 11-50). It would have been obvious to one of ordinary skill in the art to implement Thomas’ S/H capacitor network as the network more advantageously provides selectable gain/full-scale-range by segmenting the sampling capacitors and using an amount appropriate for the user-supplied gain range (co. 2 ln. 66-67, co. 3 ln. 1-3). One of ordinary skill in the art would look to Thomas’ S/H capacitor network before the effective filing date to benefit from the performance advantages in noise, resolution, and linearity over approaches that digitally scale the output code (co. 3 ln. 3-10), and thus it would have been obvious to make the modification and achieve the predictable results of sampling and combining.
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein
the signal divider circuits comprise voltage divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]).
Regarding claim 3, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein:
each bit-cell output (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]) is provided via a respective output capacitor (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]); and
the signal divider circuits comprise charge divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]).
Regarding claim 4, the teachings addressed in the claim 3 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 3, wherein:
each analog signal represents a charge stored across a respective plurality of coupled bit-cell output capacitors (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026], [0045]) within the IMC array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]); and
each of the plurality of signal divider circuits has a substantially similar total capacitance ([0026-0027]
9
*
C
u
), and respective output capacitor having a capacitance selected to provide the corresponding scaled output signal in response to a transfer thereto of a portion of the charge stored across the respective plurality of coupled bit-cell output capacitors ([0026-0027], [0045]
2
0
,
2
1
,
2
2
,
2
3
).
Regarding claim 6, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein:
the analog signals comprise N analog signals to be binary weighted (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), where N is an integer greater than 1 (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0026] N=4), the apparatus comprising:
a least significant bit (LSB) signal divider circuit (Figs. 2A & 3A & 3B, Cm[0] 1*Cu, [0045]) having a total capacitance of C ([0026-0027]
C
u
) and an output capacitor of
C
/
2
N
-
1
([0026-0027]
1
*
C
u
), the LSB signal divider circuit being configured to process a LSB- representative analog signal ([0019], [0039], [0058]); and
a most significant bit (MSB) signal divider circuit (Figs. 2A & 3A & 3B, Cm[3] 8*Cu, [0045]) having a total capacitance of C ([0026-0027]
C
u
) and an output capacitor of C ([0026-0027]
8
*
C
u
), the MSB signal divider circuit being configured to process a MSB- representative analog signal ([0019], [0039], [0058]).
Regarding claim 7, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, comprising:
a LSB+1 signal divider circuit (Figs. 2A & 3A & 3B, Cm[1] 2*Cu, [0045]) having a total capacitance of C ([0026-0027]
C
u
) and an output capacitor of C/N ([0026-0027]
2
*
C
u
), the LSB signal divider circuit being configured to process a LSB+1-representative analog signal ([0019], [0039], [0058]); and
a most significant bit (MSB) signal divider circuit (Figs. 2A & 3A & 3B, Cm[3] 8*Cu, [0045]) having a total capacitance of C ([0026-0027]
C
u
) and an output capacitor of C/2 ([0026-0027]
8
*
C
u
), the MSB signal divider circuit being configured to process a MSB- representative analog signal ([0019], [0039], [0058]).
Regarding claim 8, the teachings addressed in the claim 3 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 3, wherein:
at least some of the columns of bit-cells (Figs. 3A & 3B, RBL[3] – RBL[0], [0026]) disposed therein a respective disconnect switch (Figs. 3A & 3B, S0B, [0040-0041]) for disconnecting a first portion of the column of bit cells (Figs. 3A & 3B, 222, [0040], [0028]) from a remaining portion of the column of bit-cells (Figs. 3A & 3B, 224, [0039-0041]) such that an analog signal provided by the remaining portion of the column of bit-cells is scaled to a weighting associated with the column ([0041], [0044-0045]).
Regarding claim 9, the teachings addressed in the claim 8 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 8, further comprising:
a plurality of switches (Figs. 3A & 3B, S1 in each RBL[3] – RBL[0], [0041], [0056-0057]) configured to couple the remaining portions of the columns of bit-cells (Figs. 3A & 3B, 224, [0039-0041]) to each other to provide thereby an analog signal representing a weighted accumulated result ([0057-0058]).
Regarding claim 10, Sinangil teaches:
An analog scaling and summing apparatus (Fig. 2A, 200, [0018], [0026], [0035]) for capacitor-based in-memory computing (IMC) ([0005]), wherein each bit-cell (Fig. 1, 110, [0023]) in a NxM array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]) provides at a respective output capacitor (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]) a voltage level ([0058]) associated with a weighted respective portion of an IMC operation (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), wherein a column of bit-cell output capacitors storing voltage levels associated with the same weight are coupled together (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026], [0039], [0045]) to provide for that weight a respective weighted-data-representative analog signal ([0040-0041]), the apparatus comprising:
a plurality of signal divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]), each signal divider circuit (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026]) configured to process a respective weighted-data-representative analog signal of a respective column of bit-cell output capacitors to produce an output signal (Figs. 3A & 3B, 228, [0041]) across a respective output capacitor of a capacitance value scaled in accordance with the respective weighting value (Figs. 2A & 3A & 3B, 222, 224, [0026-0030]);
an analog to digital converter (ADC) (Figs. 3A & 3B & 4, 270, [0046]);
wherein, during a measurement phase of operation (Fig. 5, 530, 540, [0052-0053], [0055]), corresponding output signals (Figs. 3A & 3B, 228, [0041]) to provide an accumulated analog signal for digitization by the ADC ([0059]), the ADC configured to generate therefrom a digital output representing a summation of the weighted-data-representative analog signals (Figs. 3A & 3B & 4, output from 270, [0046]; Fig. 3B referred to as NOUT[3:0]; Fig. 2A, 64 4-bit outputs NOUT0[3:0] to NOUT15[3:0], [0029]).
Although Sinangil discloses an analog to digital converter (ADC), they appear to be silent to disclose a sample-and-hold (S/H) capacitor network integrated within the ADC; signals are sampled onto respective portions of the S/H capacitor network and are combined within the S/H capacitor network.
Thomas discloses a sample-and-hold (S/H) capacitor network integrated within (Fig. 1 “22” co. 3 ln. 54-67, co. 4 ln. 1-13 with selected capacitors “38A-E” co. 4 ln. 51-64) the ADC; signals are sampled onto respective portions of the S/H capacitor network and are combined within the S/H capacitor network (co. 4 ln. 25-42).
The motivation to combine with respect to claim 1 similarly applies.
Regarding claim 11, the teachings addressed in the claim 10 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 10, wherein:
each column of weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]) represent respective binary-weighted data bits of an accumulated result of the IMC operation ([0019-0020], [0022-0023], [0025-0026], [0028-0030], [0042] [0059]).
Regarding claim 14, Sinangil teaches:
Apparatus (Fig. 2A, 200, [0035]) for scaling and summing ([0018], [0026]) a plurality of weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), wherein each weighted-data-representative analog signal (Fig. 1, 110, [0023]) comprises one of an electronic voltage, current, or charge ([0019], [0023-0025]) provided by a respective column of coupled bit-cells (Figs. 2A & 3A & 3B, columns of 110 in 190[3] – 190[0], [0026-0031]) within an in-memory computing (IMC) array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]), the apparatus comprising:
at least some of the columns of coupled bit-cells (Figs. 3A & 3B, RBL[3] – RBL[0], [0026]) having disposed therein a respective disconnect switch (Figs. 3A & 3B, S0B, [0040-0041]) for disconnecting a first portion of the column of bit cells (Figs. 3A & 3B, 222, [0040], [0028]) from a remaining portion of the column of bit-cells (Figs. 3A & 3B, 224, [0039-0041]) such that analog signal provided by the remaining portion of the column of bit-cells is scaled to a weighting associated with the column ([0041], [0044-0045]);
an analog to digital converter (ADC) (Figs. 3A & 3B & 4, 270, [0046]);
switches (Figs. 3A & 3B, S1 in each RBL[3] – RBL[0], [0041], [0056-0057]) configured to couple, during a measurement phase of operation (Fig. 5, 530, 540, [0052-0053], [0055]), the scaled analog signals provided by the remaining portions of ([0041], [0044-0045]),
an accumulated analog signal for digitization by the ADC ([0059]), the ADC configured to generate therefrom a digital output representing a summation of the weighted-data-representative analog signals (Figs. 3A & 3B & 4, output from 270, [0046]; Fig. 3B referred to as NOUT[3:0]; Fig. 2A, 64 4-bit outputs NOUT0[3:0] to NOUT15[3:0], [0029]).
Although Sinangil discloses an analog to digital converter (ADC), they appear to be silent to disclose a sample-and-hold (S/H) capacitor network integrated within the ADC; signals are sampled onto the respective portions of the S/H capacitor network and are combined within the S/H capacitor network.
Thomas discloses a sample-and-hold (S/H) capacitor network integrated within (Fig. 1 “22” co. 3 ln. 54-67, co. 4 ln. 1-13 with selected capacitors “38A-E” co. 4 ln. 51-64) the ADC; signals are sampled onto the respective portions of the S/H capacitor network and are combined within the S/H capacitor network (co. 4 ln. 25-42).
The motivation to combine with respect to claim 1 similarly applies.
Regarding claim 15, the teachings addressed in the claim 14 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 14, wherein:
each of the bit-cells comprises an output capacitor (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]) for storing a charge indicative of a bit- cell operation ([0056] precharge pch applied to parallel combination of computation and compensation capacitors); and
each of the bit-cell columns being associated with a respective data weighting value ([0026-0027], [0045]
2
0
,
2
1
,
2
2
,
2
3
).
Regarding claim 16, the teachings addressed in the claim 15 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 15, wherein
each column is associated with a remaining portion of bit-cell output capacitors (Figs. 3A & 3B, 224, [0039-0041]) proportional to the weight of the column ([0027-0028], [0044-0045]).
Regarding claim 18, the teachings addressed in the claim 15 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 15, wherein
the analog signals comprise N binary weighted analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), where N is an integer greater than 1, the apparatus comprising N columns of respective coupled bit-cell output capacitors within the IMC array (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0026] N=4).
Regarding claim 19, the teachings addressed in the claim 15 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 15, wherein
the weighted-data-representative analog signals comprise at least most significant bit (MSB) (Figs. 2A & 3A & 3B, Cm[3] 8*Cu, [0045], [0058]) and least significant bit (LSB) binary weighted data- representative analog signals (Figs. 2A & 3A & 3B, Cm[0] 1*Cu, [0045], [0058]).
Regarding claim 20, the teachings addressed in the claim 19 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 19, wherein
the weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]) further comprise at least one additional binary weighted data-representative analog signal (Figs. 2A & 3A & 3B, Cm[2] 4*Cu and Cm[1] 2*Cu, [0045], [0058]).
Regarding claim 21, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein:
the ADC (Figs. 3A & 3B & 4, 270, [0046]) comprises a successive-approximation register (SAR) ADC in which the S/H capacitor network also serves as a feedback digital-to-analog converter (DAC); and
wherein the S/H capacitor network is partitioned into a plurality of capacitor segments, each capacitor segment configured to take as an input a respective one of the weighted-data representative analog signals (Figs. 3A & 3B & 4, 270, [0046]), each capacitor segment having a total capacitance substantially equal to a total capacitance of each other capacitor segment, and each capacitor segment being further divided into (i) a first capacitance portion that is processed by the SAR ADC and (ii) a second capacitance portion that is not processed, the first capacitance portions being selectively coupled together to perform scaling and summation ([0018], [0026]) of the sampled signals within the ADC (Figs. 3A & 3B & 4, output from 270, [0046]; Fig. 3B referred to as NOUT[3:0]; Fig. 2A, 64 4-bit outputs NOUT0[3:0] to NOUT15[3:0], [0029]) while the second capacitance portions remain uncoupled at a reference voltage and are discharged before a subsequent sampling.
Sinangil appears to be silent to disclosing a successive-approximation register (SAR) ADC in which the S/H capacitor network also serves as a feedback digital-to-analog converter (DAC); and wherein the S/H capacitor network is partitioned into a plurality of capacitor segments, each capacitor segment configured to take as an input, each capacitor segment having a total capacitance substantially equal to a total capacitance of each other capacitor segment, and each capacitor segment being further divided into (i) a first capacitance portion that is processed by the SAR ADC and (ii) a second capacitance portion that is not processed, the first capacitance portions being selectively coupled together to perform scaling and summation of the sampled signals within the ADC while the second capacitance portions remain uncoupled at a reference voltage and are discharged before a subsequent sampling.
Thomas discloses a successive-approximation register (SAR) ADC (Fig. 1 “10” co. 3 ln. 47-58) in which the S/H capacitor network (Fig. 1 “22” co. 3 ln. 54-67, co. 4 ln. 1-13 with selected capacitors “38A-E” co. 4 ln. 51-64) also serves as a feedback digital-to-analog converter (DAC) (co. 9 ln. 16-30, 55-65); and
wherein the S/H capacitor network is partitioned into a plurality of capacitor segments (Fig. 1 “26A-N” co. 3 ln. 59-67, co. 4 ln. 1-3, any subset of capacitors with “38A-E” co. 4 ln. 51-64), each capacitor segment configured to take as an input (co. 9 ln. 8-15
V
i
n
), each capacitor segment having a total capacitance substantially equal to a total capacitance of each other capacitor segment (co. 4 ln. 65-67, co. 5 ln. 1-13 for example when Fig. 1 “26A” N = 32 (
C
s
/
32
) and Fig. 1 “38E” (
C
/
32
)), and each capacitor segment being further divided into (i) a first capacitance portion (Fig. 1 “26A” co. 3 ln. 59-67, co. 4 ln. 1-3) that is processed by the SAR ADC (co. 4 ln. 45-64) and (ii) a second capacitance portion (Fig. 1 “38A-E” co. 4 ln. 51-64) that is not processed (co. 4 ln. 43-51), the first capacitance portions being selectively coupled together (co. 4 ln. 25-31), sampled signals (co. 4 ln. 25-42), while the second capacitance portions remain uncoupled at a reference voltage (co. 4 ln. 43-64) and are discharged before a subsequent sampling (co. 4 ln. 32-64).
The motivation to combine with respect to claim 1 similarly applies.
Regarding claim 22, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein
the analog input voltage corresponding to each weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]).
Sinangil appears to be silent to disclosing is sampled at a bottom plate of sampling capacitors of the S/H capacitor network, and SAR feedback codes are applied to an opposing plate to perform successive approximation conversion.
Thomas discloses is sampled at a bottom plate of sampling capacitors of the S/H capacitor network (Fig. 1 “34” co. 4 ln. 32-42 capacitor plate corresponding to marked reference numbers “38A-E”), and SAR feedback codes (Fig. 1 output of “16” to “36A-E” co. 4 ln. 51-64) are applied to an opposing plate (Fig. 1 “34” co. 4 ln. 32-42 capacitor plate corresponding to unmarked side of reference numbers “38A-E”) to perform successive approximation conversion (co. 3 ln. 49-52).
The motivation to combine with respect to claim 1 similarly applies.
Regarding claim 23, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1.
Sinangil appears to be silent to disclosing the first capacitance portion of each capacitor segment corresponds to a binary-weighted capacitance across the plurality of capacitor segments.
Thomas discloses the first capacitance portion (Fig. 1 “26A” co. 3 ln. 59-67, co. 4 ln. 1-3) of each capacitor segment (Fig. 1 “26A-N” co. 3 ln. 59-67, co. 4 ln. 1-3, any subset of capacitors with “38A-E” co. 4 ln. 51-64) corresponds to a binary-weighted capacitance (Fig. 1 “
C
s
/
N
” co. 4 ln. 65-67, co. 5 ln. 1-13) across the plurality of capacitor segments (Fig. 1 “26A-N” co. 3 ln. 59-67, co. 4 ln. 1-3, any subset of capacitors with “38A-E” co. 4 ln. 51-64).
The motivation to combine with respect to claim 1 similarly applies.
Regarding claim 24, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein,
during the measurement phase (Fig. 5, 530, 540, [0052-0053], [0055]).
Sinangil appears to be silent to disclosing only the first capacitance portions are coupled together on one side of the capacitor segments and the second capacitance portions remain shorted to the reference voltage on that side.
Thomas discloses only the first capacitance portions are coupled together on one side (Fig. 1 “26A-N” co. 3 ln. 59-67, co. 4 ln. 1-3) of the capacitor segments (Fig. 1 “26A-N” co. 3 ln. 59-67, co. 4 ln. 1-3, any subset of capacitors with “38A-E” co. 4 ln. 51-64) and the second capacitance portions (Fig. 1 “38A-E” co. 4 ln. 51-64) remain shorted to the reference voltage on that side (Fig. 1 “32” co. 4 ln. 4-13).
The motivation to combine with respect to claim 1 similarly applies.
Regarding claim 25, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1.
Sinangil appears to be silent to disclosing the second capacitance portions are discharged before future sampling to reduce sampling error attributable to residual charge.
Thomas discloses the second capacitance portions (Fig. 1 “38A-E” co. 4 ln. 51-64) are discharged before future sampling to reduce sampling error attributable to residual charge (co. 4 ln. 32-64).
The motivation to combine with respect to claim 1 similarly applies.
Regarding claim 26, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein,
the plurality of weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026] signals) correspond to outputs of a plurality of parallel columns or bit lines (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026] bit line columns) representing weighted portions of a computation result (Fig. 2A “NOUTO[3:0]”, Fig. 3B “NOUT[3:0]” [0039]), and the ADC is shared across the plurality of parallel columns or bit lines (Fig. 3B “270” [0046]).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sinangil in view of Thomas, and further in view of US 20230004350 A1 Li (hereinafter “Li”).
Regarding claim 12, the teachings addressed in the claim 11 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 11, wherein:
during a reset phase of operation, the charge stored in each of the columns of bit-cell output capacitors ([0056] precharge pch applied to parallel combination of computation and compensation capacitors) is substantially removed;
during an evaluate phase of operation (Fig. 3C, 310, 320, [0056]), the charge stored in each of the columns of bit-cell output capacitors provides a corresponding contribution to a total charge of the respective column ([0056] total charge); and
during the measurement phase of operation (Fig. 3C, 330, 340, [0057-0059]), each of the weighted-data-representative analog signals is scaled in accordance with its weighting level ([0058]) to provide thereby a weighted portion of an analog signal representing an accumulated result to be processed by the ADC ([0059]).
Sinangil is silent with disclosing during a reset phase of operation, charge is substantially removed.
Thomas and the combination of Sinangil in view of Thomas are silent with disclosing during a reset phase of operation, charge is substantially removed.
Li teaches during a reset phase of operation, charge is substantially removed ([0089]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil in view of Thomas with Li’s reset phase where charge is substantially removed because they are in the claimed invention’s same field of endeavor of compute in memory array architectures ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the reset phase as Li’s method more advantageously allows for charges held in the capacitor to be discharged in preparation for processing of next set of inputs ([0089]). A person of ordinary skill in the art would look to Li’s reset phase to utilize an efficient method for resetting data to more accurately and correctly process next rounds of data, and thus it would have been obvious to make the modification.
Regarding claim 13, Sinangil teaches:
An analog scaling and summing apparatus (Fig. 2A, 200, [0018], [0026], [0035]) for capacitor-based in-memory computing (IMC) ([0005]), wherein each bit-cell (Fig. 1, 110, [0023]) in a NxM array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]) provides at a respective output capacitor (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]) a voltage level ([0058]) associated with a weighted respective portion of an IMC operation (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), wherein a column of bit-cell output capacitors storing voltage levels associated with the same weight are coupled together (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026], [0039], [0045]) to provide for that weight a respective weighted-data-representative analog signal ([0040-0041]), the apparatus comprising:
a plurality of signal divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]), each signal divider circuit (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026]) configured to process a respective weighted-data-representative analog signal to produce an output signal (Figs. 3A & 3B, 228, [0041]) having a value scaled in accordance with the respective weighting value (Figs. 2A & 3A & 3B, 222, 224, [0026-0030]); and
a successive approximation register (SAR) analog to digital converter (ADC) (Figs. 3A & 3B & 4, 270, [0046]); wherein
during a reset phase of operation, the charge stored in each of the columns of bit-cell output capacitors ([0056] precharge pch applied to parallel combination of computation and compensation capacitors) is substantially removed;
during an evaluate phase of operation (Fig. 3C, 310, 320, [0056]), the charge stored in each of the columns of bit-cell output capacitors provides a corresponding contribution to a total charge of the respective column ([0056] total charge); and
during the measurement phase of operation (Fig. 3C, 330, 340, [0057-0059]), switches within one or more of the columns of bit-cell output capacitors are activated to disconnect (Fig. 3B, S0A, S0B, [0057] S0A and S0B switched off) at least a portion of the bit-cell output capacitors (Fig. 3B, 222, [0040]), wherein the remaining portions of bit-cell output capacitors for each column (Fig. 3B, 224, [0040-0041]) have a total capacitance reflecting the weighting value of the column (Fig. 3B, Cm[j] in 224, [0058]), and wherein the corresponding output signals (Figs. 3A & 3B, 228, [0041]) of the signal divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]), to provide an accumulated analog signal for digitization by the ADC ([0059]), the ADC configured to generate therefrom a digital output representing a summation of the weighted-data-representative analog signals (Figs. 3A & 3B & 4, output from 270, [0046]; Fig. 3B referred to as NOUT[3:0]; Fig. 2A, 64 4-bit outputs NOUT0[3:0] to NOUT15[3:0], [0029]).
Although Sinangil discloses an analog to digital converter (ADC), they appear to be silent to disclose a successive approximation register (SAR) analog to digital converter (ADC) comprising a sample-and-hold (S/H) capacitor network integrated within the ADC; signals are sampled onto respective portions of the S/H capacitor network and are combined within the S/H capacitor network.
Thomas discloses a successive approximation register (SAR) analog to digital converter (ADC) (Fig. 1 “10” co. 3 ln. 47-58) comprising a sample-and-hold (S/H) capacitor network integrated within (Fig. 1 “22” co. 3 ln. 54-67, co. 4 ln. 1-13 with selected capacitors “38A-E” co. 4 ln. 51-64) the ADC; signals are sampled onto respective portions of the S/H capacitor network and are combined within the S/H capacitor network (co. 4 ln. 25-42).
The motivation to combine with respect to claim 1 similarly applies.
Thomas and the combination of Sinangil in view of Thomas are silent with disclosing during a reset phase of operation, charge is substantially removed.
Li teaches during a reset phase of operation, charge is substantially removed ([0089]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil in view of Thomas with Li’s reset phase where charge is substantially removed because they are in the claimed invention’s same field of endeavor of compute in memory array architectures ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the reset phase as Li’s method more advantageously allows for charges held in the capacitor to be discharged in preparation for processing of next set of inputs ([0089]). A person of ordinary skill in the art would look to Li’s reset phase to utilize an efficient method for resetting data to more accurately and correctly process next rounds of data, and thus it would have been obvious to make the modification.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sinangil in view of Thomas in view of Li, and further in view of US 4405916 A Hornak et al. (hereinafter “Hornak”).
Regarding claim 17, the teachings addressed in the claim 15 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 15, further comprising
a plurality of parasitic offset switches
S
P
O
configured to compensate for weighted parasitic capacitance of the disconnect switches (Figs. 3A & 3B, S0B, [0040-0041]).
Sinangil is silent with disclosing a plurality of parasitic offset switches
S
P
O
configured to compensate for weighted parasitic capacitance.
Thomas and Sinangil in view of Thomas are silent with disclosing a plurality of parasitic offset switches
S
P
O
configured to compensate for weighted parasitic capacitance.
Li and Sinangil in view of Thomas in view of Li are silent with disclosing a plurality of parasitic offset switches
S
P
O
configured to compensate for weighted parasitic capacitance.
Hornak teaches a plurality of parasitic offset switches
S
P
O
(Fig. 2, 22, 23; Col. 3, lines 57-68, Col. 4, lines 1-14) configured to compensate for weighted parasitic capacitance ([Abstract]; Col. 2, lines 30-41; Col. 3, lines 57-67; Col. 4, lines 50-67).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil in view of Thomas in view of Li with Hornak’s parasitic switches because they are in the claimed invention’s same field of endeavor of bit cell architectures ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the parasitic switches as Li’s switches more advantageously allow for higher switching speeds by controlling the routing of current (Col. 1, lines 45-61; Col. 2, lines 42-58; Col. 3, lines 10-36). A person of ordinary skill in the art would look to Hornak’s parasitic switches to utilize an efficient method for routing current to more accurately and correctly process data at higher speeds, and thus it would have been obvious to make the modification.
Response to Arguments
Drawings. The drawings objections are maintained for Figs. 2-10. Special attention to phrases in the drawings and letters/numbers found in the subscripts.
35 USC 112(b). The rejections are withdrawn based on the amendment to the claims. A new ground of rejection is made as necessitated by the amendment.
35 USC 102. Applicant’s arguments, see Remarks p. 12, filed 01 June 2026, with respect to the rejection(s) of claim(s) 1-4, 6-9, 14-16, 18-20 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, as necessitated by the amendment to the claims, a new ground(s) of rejection is made in view of Thomas.
35 USC 103. As necessitated by the amendment to the claims, a new grounds of rejection is made in view of Thomas.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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