DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because they fail to comply with CFR 1.84(a)(1) and (p)(1) as Figs. 1-10 contain lines, reference numbers, and words that are illegible and not secured by black ink.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14, the phrase “an electronic voltage, current, or charge” renders the claim indefinite because it is unclear whether the limitations following the phrase configure the part of the claimed invention differently. It is not clear whether the apparatus is configured for all, or whether the apparatus is configured for one individually of voltage, individually of current, or individually of charge. See MPEP § 2173.05(d). Claims 15-20 are rejected for reasons of dependence on claim 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-9, 14-16, 18-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20210158854 A1 Sinangil (hereinafter “Sinangil”).
Regarding claim 1, Sinangil teaches:
Apparatus (Fig. 2A, 200, [0035]) for scaling and summing ([0018], [0026]) a plurality of weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), wherein each analog signal comprises a voltage associated with a respective plurality of coupled bit-cell outputs (Fig. 1, 110, [0023]) within an in-memory computing (IMC) array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]), the apparatus comprising:
a plurality of signal divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]), each signal divider circuit (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026]) configured to process a respective weighted-data-representative analog signal to produce an output signal (Figs. 3A & 3B, 228, [0041]) having a value scaled in accordance with the respective weighting value (Figs. 2A & 3A & 3B, 222, 224, [0026-0030]);
wherein, during a measurement phase of operation (Fig. 5, 530, 540, [0052-0053], [0055]), the signal divider circuit output signals are coupled to an input of an analog to digital converter (ADC) (Figs. 3A & 3B & 4, 270, [0046]) configured to generate therefrom a digital output representing a summation of the weighted-data-representative analog signals (Figs. 3A & 3B & 4, output from 270, [0046]; Fig. 3B referred to as NOUT[3:0]; Fig. 2A, 64 4-bit outputs NOUT0[3:0] to NOUT15[3:0], [0029]).
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein
the signal divider circuits comprise voltage divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]).
Regarding claim 3, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein:
each bit-cell output (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]) is provided via a respective output capacitor (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]); and
the signal divider circuits comprise charge divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]).
Regarding claim 4, the teachings addressed in the claim 3 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 3, wherein:
each analog signal represents a charge stored across a respective plurality of coupled bit-cell output capacitors (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026], [0045]) within the IMC array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]); and
each of the plurality of signal divider circuits has a substantially similar total capacitance ([0026-0027]
9
*
C
u
), and respective output capacitor having a capacitance selected to provide the corresponding scaled output signal in response to a transfer thereto of a portion of the charge stored across the respective plurality of coupled bit-cell output capacitors ([0026-0027], [0045]
2
0
,
2
1
,
2
2
,
2
3
).
Regarding claim 6, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, wherein:
the analog signals comprise N analog signals to be binary weighted (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), where N is an integer greater than 1 (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0026] N=4), the apparatus comprising:
a least significant bit (LSB) signal divider circuit (Figs. 2A & 3A & 3B, Cm[0] 1*Cu, [0045]) having a total capacitance of C ([0026-0027]
C
u
) and an output capacitor of
C
/
2
N
-
1
([0026-0027]
1
*
C
u
), the LSB signal divider circuit being configured to process a LSB- representative analog signal ([0019], [0039], [0058]); and
a most significant bit (MSB) signal divider circuit (Figs. 2A & 3A & 3B, Cm[3] 8*Cu, [0045]) having a total capacitance of C ([0026-0027]
C
u
) and an output capacitor of C ([0026-0027]
8
*
C
u
), the MSB signal divider circuit being configured to process a MSB- representative analog signal ([0019], [0039], [0058]).
Regarding claim 7, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 1, comprising:
a LSB+1 signal divider circuit (Figs. 2A & 3A & 3B, Cm[1] 2*Cu, [0045]) having a total capacitance of C ([0026-0027]
C
u
) and an output capacitor of C/N ([0026-0027]
2
*
C
u
), the LSB signal divider circuit being configured to process a LSB+1-representative analog signal ([0019], [0039], [0058]); and
a most significant bit (MSB) signal divider circuit (Figs. 2A & 3A & 3B, Cm[3] 8*Cu, [0045]) having a total capacitance of C ([0026-0027]
C
u
) and an output capacitor of C/2 ([0026-0027]
8
*
C
u
), the MSB signal divider circuit being configured to process a MSB- representative analog signal ([0019], [0039], [0058]).
Regarding claim 8, the teachings addressed in the claim 3 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 3, wherein:
at least some of the columns of bit-cells (Figs. 3A & 3B, RBL[3] – RBL[0], [0026]) disposed therein a respective disconnect switch (Figs. 3A & 3B, S0B, [0040-0041]) for disconnecting a first portion of the column of bit cells (Figs. 3A & 3B, 222, [0040], [0028]) from a remaining portion of the column of bit-cells (Figs. 3A & 3B, 224, [0039-0041]) such that an analog signal provided by the remaining portion of the column of bit-cells is scaled to a weighting associated with the column ([0041], [0044-0045]).
Regarding claim 9, the teachings addressed in the claim 8 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 8, further comprising:
a plurality of switches (Figs. 3A & 3B, S1 in each RBL[3] – RBL[0], [0041], [0056-0057]) configured to couple the remaining portions of the columns of bit-cells (Figs. 3A & 3B, 224, [0039-0041]) to each other to provide thereby an analog signal representing a weighted accumulated result ([0057-0058]).
Regarding claim 14, Sinangil teaches:
Apparatus (Fig. 2A, 200, [0035]) for scaling and summing ([0018], [0026]) a plurality of weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), wherein each weighted-data-representative analog signal (Fig. 1, 110, [0023]) comprises an electronic voltage, current, or charge ([0019], [0023-0025]) provided by a respective column of coupled bit-cells (Figs. 2A & 3A & 3B, columns of 110 in 190[3] – 190[0], [0026-0031]) within an in- memory computing (IMC) array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]), the apparatus comprising:
at least some of the columns of coupled bit-cells (Figs. 3A & 3B, RBL[3] – RBL[0], [0026]) having disposed therein a respective disconnect switch (Figs. 3A & 3B, S0B, [0040-0041]) for disconnecting a first portion of the column of bit cells (Figs. 3A & 3B, 222, [0040], [0028]) from a remaining portion of the column of bit-cells (Figs. 3A & 3B, 224, [0039-0041]) such that analog signal provided by the remaining portion of the column of bit-cells is scaled to a weighting associated with the column ([0041], [0044-0045]); and
switches (Figs. 3A & 3B, S1 in each RBL[3] – RBL[0], [0041], [0056-0057]) configured to couple the remaining portions of columns of bit-cells (Figs. 3A & 3B, 224, [0039-0041]) to each other to provide thereby an analog signal representing an accumulated result ([0057-0058]).
Regarding claim 15, the teachings addressed in the claim 14 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 14, wherein:
each of the bit-cells comprises an output capacitor (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]) for storing a charge indicative of a bit- cell operation ([0056] precharge pch applied to parallel combination of computation and compensation capacitors); and
each of the bit-cell columns being associated with a respective data weighting value ([0026-0027], [0045]
2
0
,
2
1
,
2
2
,
2
3
).
Regarding claim 16, the teachings addressed in the claim 15 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 15, wherein
each column is associated with a remaining portion of bit-cell output capacitors (Figs. 3A & 3B, 224, [0039-0041]) proportional to the weight of the column ([0027-0028], [0044-0045]).
Regarding claim 18, the teachings addressed in the claim 15 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 15, wherein
the analog signals comprise N binary weighted analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), where N is an integer greater than 1, the apparatus comprising N columns of respective coupled bit-cell output capacitors within the IMC array (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0026] N=4).
Regarding claim 19, the teachings addressed in the claim 15 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 15, wherein
the weighted-data-representative analog signals comprise at least most significant bit (MSB) (Figs. 2A & 3A & 3B, Cm[3] 8*Cu, [0045], [0058]) and least significant bit (LSB) binary weighted data- representative analog signals (Figs. 2A & 3A & 3B, Cm[0] 1*Cu, [0045], [0058]).
Regarding claim 20, the teachings addressed in the claim 19 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 19, wherein
the weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]) further comprise at least one additional binary weighted data-representative analog signal (Figs. 2A & 3A & 3B, Cm[2] 4*Cu and Cm[1] 2*Cu, [0045], [0058]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Sinangil, and further in view of US 7379012 B2 Sutardja (hereinafter “Sutardja”).
Regarding claim 5, the teachings addressed in the claim 2 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 2, wherein:
the signal divider circuit is integrated with a sample and hold circuit within the ADC (see claim 1 mapping).
Sinangil is silent with disclosing the signal divider circuit is integrated with a sample and hold circuit within the ADC.
Sutardja teaches the signal divider circuit is integrated with a sample and hold circuit within (Fig. 11A, 254; Col. 15, lines 21-34) the ADC.
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil with Sutardja’s sample and hold circuit because they are in the claimed invention’s same field of endeavor of analog to digital converters (Col. 1, lines 15-18). It would have been obvious to one of ordinary skill in the art to implement the sample and hold circuit as Sutardja’s sample and hold circuit more advantageously
allows for analog signals to be held for time until required for processing (Col. 15, lines 21-40). A person of ordinary skill in the art would look to Sutardja’s sample and hold circuit in order to utilize an efficient component for processing data to leverage the timing capabilities of delaying, yielding more accurate and correct calculations, and thus it would have been obvious to make the modification.
Regarding claim 10, Sinangil teaches:
An analog scaling and summing apparatus (Fig. 2A, 200, [0018], [0026], [0035]) for capacitor-based in-memory computing (IMC) ([0005]), wherein each bit-cell (Fig. 1, 110, [0023]) in a NxM array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]) provides at a respective output capacitor (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]) a voltage level ([0058]) associated with a weighted respective portion of an IMC operation (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), wherein a column of bit-cell output capacitors storing voltage levels associated with the same weight are coupled together (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026], [0039], [0045]) to provide for that weight a respective weighted-data-representative analog signal ([0040-0041]), the apparatus comprising:
a plurality of signal divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]), each signal divider circuit (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026]) configured to process a respective weighted-data-representative analog signal of a respective column of bit-cell output capacitors to produce an output signal (Figs. 3A & 3B, 228, [0041]) across a respective output capacitor of a capacitance value scaled in accordance with the respective weighting value (Figs. 2A & 3A & 3B, 222, 224, [0026-0030]);
wherein, during a measurement phase of operation (Fig. 5, 530, 540, [0052-0053], [0055]), the output capacitors of the signal divider circuits are coupled (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]) to a sample and hold circuit associated with an input of an analog to digital converter (ADC) (Figs. 3A & 3B & 4, 270, [0046]) configured to generate therefrom a digital output representing a summation of the weighted-data-representative analog signals (Figs. 3A & 3B & 4, output from 270, [0046]; Fig. 3B referred to as NOUT[3:0]; Fig. 2A, 64 4-bit outputs NOUT0[3:0] to NOUT15[3:0], [0029]).
Sinangil is silent with disclosing a sample and hold circuit associated with an ADC.
Sutardja teaches a sample and hold circuit associated (Fig. 11A, 254; Col. 15, lines 21-34) with an ADC.
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil with Sutardja’s sample and hold circuit because they are in the claimed invention’s same field of endeavor of analog to digital converters (Col. 1, lines 15-18). It would have been obvious to one of ordinary skill in the art to implement the sample and hold circuit as Sutardja’s sample and hold circuit more advantageously
allows for analog signals to be held for time until required for processing (Col. 15, lines 21-40). A person of ordinary skill in the art would look to Sutardja’s sample and hold circuit in order to utilize an efficient component for processing data to leverage the timing capabilities of delaying, yielding more accurate and correct calculations, and thus it would have been obvious to make the modification.
Regarding claim 11, the teachings addressed in the claim 10 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 10, wherein:
each column of weighted-data-representative analog signals (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]) represent respective binary-weighted data bits of an accumulated result of the IMC operation ([0019-0020], [0022-0023], [0025-0026], [0028-0030], [0042] [0059]).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sinangil in view of Sutardja, and further in view of US 20230004350 A1 Li (hereinafter “Li”).
Regarding claim 12, the teachings addressed in the claim 11 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 11, wherein:
during a reset phase of operation, the charge stored in each of the columns of bit-cell output capacitors ([0056] precharge pch applied to parallel combination of computation and compensation capacitors) is substantially removed;
during an evaluate phase of operation (Fig. 3C, 310, 320, [0056]), the charge stored in each of the columns of bit-cell output capacitors provides a corresponding contribution to a total charge of the respective column ([0056] total charge); and
during the measurement phase of operation (Fig. 3C, 330, 340, [0057-0059]), each of the weighted-data-representative analog signals is scaled in accordance with its weighting level ([0058]) to provide thereby a weighted portion of an analog signal representing an accumulated result to be processed by the ADC ([0059]).
Sinangil is silent with disclosing during a reset phase of operation, charge is substantially removed.
Sutardja and the combination of Sinangil in view of Sutardja are silent with disclosing during a reset phase of operation, charge is substantially removed.
Li teaches during a reset phase of operation, charge is substantially removed ([0089]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil in view of Sutardja with Li’s reset phase where charge is substantially removed because they are in the claimed invention’s same field of endeavor of compute in memory array architectures ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the reset phase as Li’s method more advantageously allows for charges held in the capacitor to be discharged in preparation for processing of next set of inputs ([0089]). A person of ordinary skill in the art would look to Li’s reset phase in order to utilize an efficient method for resetting data in order to more accurately and correctly process next rounds of data, and thus it would have been obvious to make the modification.
Regarding claim 13, Sinangil teaches:
An analog scaling and summing apparatus (Fig. 2A, 200, [0018], [0026], [0035]) for capacitor-based in-memory computing (IMC) ([0005]), wherein each bit-cell (Fig. 1, 110, [0023]) in a NxM array of bit-cells (Fig. 2A, 230 segment, [0026], [0040]) provides at a respective output capacitor (Figs. 2A & 3A & 3B, Cm[0] to Cm[3] corresponding to Cn[0] to Cn[3], [0040]) a voltage level ([0058]) associated with a weighted respective portion of an IMC operation (Figs. 2A & 3A & 3B, 190[3] RBL[3], 190[2] RBL[2], 190[1] RBL[1], 190[0] RBL[0], [0019], [0022-0023], [0026]), wherein a column of bit-cell output capacitors storing voltage levels associated with the same weight are coupled together (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026], [0039], [0045]) to provide for that weight a respective weighted-data-representative analog signal ([0040-0041]), the apparatus comprising:
a plurality of signal divider circuits (Figs. 2A & 3A & 3B, 222 and 224, [0039-0040]), each signal divider circuit (Fig. 3A, dashed oval of Cn[j] and Cm[j] in individual column for singular example, [0026]) configured to process a respective weighted-data-representative analog signal to produce an output signal (Figs. 3A & 3B, 228, [0041]) across a respective output capacitor (Figs. 2A & 3A & 3B, 222, 224, [0026-0030]) selectively controlled by a successive approximation register (SAR) analog to digital converter (ADC) (Figs. 3A & 3B & 4, 270, [0046]); wherein
during a reset phase of operation, the charge stored in each of the columns of bit-cell output capacitors ([0056] precharge pch applied to parallel combination of computation and compensation capacitors) is substantially removed;
during an evaluate phase of operation (Fig. 3C, 310, 320, [0056]), the charge stored in each of the columns of bit-cell output capacitors provides a corresponding contribution to a total charge of the respective column ([0056] total charge); and
during the measurement phase of operation (Fig. 3C, 330, 340, [0057-0059]), switches within one or more of the columns of bit-cell output capacitors are activated to disconnect (Fig. 3B, S0A, S0B, [0057] S0A and S0B switched off) at least a portion of the bit-cell output capacitors (Fig. 3B, 222, [0040]), wherein the remaining portions of bit-cell output capacitors for each column (Fig. 3B, 224, [0040-0041]) have a total capacitance reflecting the weighting value of the column (Fig. 3B, Cm[j] in 224, [0058]), wherein the remaining coupled capacitors in each column are coupled together ([0057] S1 switched on and connects all Cm[j]) and to an input of the ADC ([0059]).
Sinangil is silent with disclosing selectively controlled by a successive approximation register (SAR); and during a reset phase of operation, charge is substantially removed.
Sutardja teaches selectively controlled by a successive approximation register (SAR) (Fig. 10, 204; Col. 14, lines 50-63; Col. 4, lines 54-63).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil with Sutardja’s successive approximation register (SAR) because they are in the claimed invention’s same field of endeavor of analog to digital converters (Col. 1, lines 15-18). It would have been obvious to one of ordinary skill in the art to implement the successive approximation register (SAR) as Sutardja’s successive approximation register (SAR) more advantageously allows for successive approximation of an analog input signal by selectively generating switch signals to control capacitances (Col. 5, lines 63-67; Col. 6, lines 1-6, 56-61). A person of ordinary skill in the art would look to Sutardja’s successive approximation register (SAR) in order to utilize an efficient component for processing data to leverage the selecting capabilities, yielding more accurate and correct calculations, and thus it would have been obvious to make the modification.
Sutardja and the combination of Sinangil in view of Sutardja are silent with disclosing during a reset phase of operation, charge is substantially removed.
Li teaches during a reset phase of operation, charge is substantially removed ([0089]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil in view of Sutardja with Li’s reset phase where charge is substantially removed because they are in the claimed invention’s same field of endeavor of compute in memory array architectures ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the reset phase as Li’s method more advantageously allows for charges held in the capacitor to be discharged in preparation for processing of next set of inputs ([0089]). A person of ordinary skill in the art would look to Li’s reset phase in order to utilize an efficient method for resetting data in order to more accurately and correctly process next rounds of data, and thus it would have been obvious to make the modification.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sinangil in view of Sutardja in view of Li, and further in view of US 4405916 A Hornak et al. (hereinafter “Hornak”).
Regarding claim 17, the teachings addressed in the claim 15 analysis and rejection are incorporated, and Sinangil teaches the apparatus of claim 15, further comprising
a plurality of parasitic offset switches
S
P
O
configured to compensate for weighted parasitic capacitance of the disconnect switches (Figs. 3A & 3B, S0B, [0040-0041]).
Sinangil is silent with disclosing a plurality of parasitic offset switches
S
P
O
configured to compensate for weighted parasitic capacitance.
Sutardja and Sinangil in view of Sutardja are silent with disclosing a plurality of parasitic offset switches
S
P
O
configured to compensate for weighted parasitic capacitance.
Li and Sinangil in view of Sutardja in view of Li are silent with disclosing a plurality of parasitic offset switches
S
P
O
configured to compensate for weighted parasitic capacitance.
Hornak teaches a plurality of parasitic offset switches
S
P
O
(Fig. 2, 22, 23; Col. 3, lines 57-68, Col. 4, lines 1-14) configured to compensate for weighted parasitic capacitance ([Abstract]; Col. 2, lines 30-41; Col. 3, lines 57-67; Col. 4, lines 50-67).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Sinangil in view of Sutardja in view of Li with Hornak’s parasitic switches because they are in the claimed invention’s same field of endeavor of bit cell architectures ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the parasitic switches as Li’s switches more advantageously allow for higher switching speeds by controlling the routing of current (Col. 1, lines 45-61; Col. 2, lines 42-58; Col. 3, lines 10-36). A person of ordinary skill in the art would look to Hornak’s parasitic switches in order to utilize an efficient method for routing current in order to more accurately and correctly process data at higher speeds, and thus it would have been obvious to make the modification.
Conclusion
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/M.A.V./Examiner, Art Unit 2151
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182