DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-4 and 6-11 rejected under 35 U.S.C. 103 as being unpatentable over Chen, US-PGPUB 2021/0063471 in view of the Applicant Admitted Prior Art, US, US-PGPUB 2022/0390509 (hereinafter AAPA)
Regarding Claim 1. Chen discloses a testing equipment, comprising: a machine, and a plurality of testing modules disposed on the machine (Fig. 1; Fig. 12; Paragraph [0111]), multiple testing modules), wherein each of the testing module includes a circuit board, a testing carrier disposed on the circuit board and carrying a target object (Paragraphs [0027], [0068], Figs. 1-2, testing a semiconductor wafer-form package that include dies or target objects, and sockets; Paragraph [0105], testing whether there is sufficient contact between the dies) and a processor disposed on the circuit board and electrically connected to the testing carrier (Paragraph [0031], automatic testing equipment. The controller may include a processor, and “in some alternative embodiment, the controller is a built-in component of the testing module), wherein the testing carrier is used for capturing a target information of the target object and for transmitting the target information to the processor via the circuit board (Paragraph [0068]). Note: Chen discloses that each testing module includes a circuit board with a processor as part of the built-in component. Although, Chen does not explicitly disclose a processor in each testing module, one of ordinary skill in the art would have obviously recognized that each circuit boards would have a built-in processor in one embodiment, involving multiple testing modules. Applicant’s argument in regard to a single controller for testing more than one testing module is merely one particular embodiment, and Chen is certainly not restricted to that particular embodiment. Furthermore, as known in the art, it is conventional to include a processor as part of the circuit board in each of the testing modules, as disclosed in AAPA in Fig. 1 (as indicated by control chip 12). As such, it would have been obvious to have a plurality of testing modules, with each testing modules including a processor, as claimed, based on what is already known.
Regarding Claim 5. Chen discloses the testing carrier is used for capturing a target information of the target object (Paragraph [0031], sending testing signal and receiving the responsive signal and evaluating the test result)
Regarding Claim 3. Chen discloses the machine is electrically connected to the circuit board of each of the plurality of testing modules (Paragraph [0031], ATE; Paragraph [0111], multiple testing modules)
Regarding Claim 4. Chen discloses the circuit board is electrically connected to the testing carrier and/or the processor (Fig. 1; Paragraph [0031], controller 300)
Regarding Claim 6. Chen discloses the processor is used for processing the target information of the target object to calculate a detecting information of the target object (Paragraph [0031], controller 300 evaluating the test results)
Regarding Claim 7. AAPA discloses a plurality of testing modules export the detecting information for compiling operations (Fig. 1; Paragraph [0004])
Regarding Claim 8. Chen discloses each of the plurality of testing modules further includes a controller disposed on the circuit board (Paragraph [0031], Paragraph [0111])
Regarding Claim 9. Chen discloses the controller is electrically connected to the circuit board (Paragraph [0031]; Figs. 1, 12)
Regarding Claim 10. Chen discloses the controller is electrically connected to the testing carrier and/or the processor (Paragraph [0031])
Regarding Claim 11. Chen discloses the circuit board has at least one transmission port electrically connected to the testing carrier (Figs. 2-15)
Response to Arguments
Applicant's arguments filed 11/14/2025 have been fully considered but they are not persuasive.
5. Applicant argues that Chen, in view of AAPA, fails to disclose “each of the plurality of testing modules includes a circuit board….and a processor disposed on the circuit board.” Furthermore, Applicant argues that the control chip of AAPA merely performs low-end control functions, and cannot be equivalent to the processor as recited in independent claims 1.
In Response, the Examiner respectfully disagrees. The Fig. 12A discussed by the Applicant is merely one of several different embodiments disclosed in Chen, and certainly does not represent the entire Chen. Having said that, Chen discloses in Paragraph [0031] that in some alternative embodiment, the controller 300 (which includes processor) is a built-in component of the testing module 100A. This means that for a plurality of testing modules 100As, it would have been obvious to one of ordinary skill in the art to recognize each testing modules having the built-in controller 300 as well in one embodiment, particularly given that it is conventional to include a processor as part of the circuit board in each of the testing modules according to AAPA.
Furthermore, the claim 1 does not recites any processing of the processor (such as receiving and processing the target information); rather, it merely recites a generic processor. The claim 6 recites “the processor is used for processing the target information of the target object to calculate a detecting information of the target object.” However, said limitation is merely an intended use of the processor and don’t have any patentable weight (although it has been rejected in the rejection). Furthermore, even when given patentable weight, the said limitation is generic, and the control chip 12 in AAPA is certainly capable of processing such a generic information. Applicant is also advised that the manner of operating the apparatus claim does not differentiate apparatus claim from the prior art (MPEP 2114, section II).
In summary, particularly given that it is conventional to have a processor in each of the testing modules, it would have been obvious to use the teachings of Chen and AAPA and arrive at the claimed apparatus claim. For these reasons, the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HYUN D PARK whose telephone number is (571)270-7922. The examiner can normally be reached 11-4.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen Vazquez can be reached at 571-272-2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN D PARK/Primary Examiner, Art Unit 2857