Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Election/Restrictions
Newly submitted claims #21-29 [herein referred to as Group II (claims #21-28) and Group III (claim #29)] are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Inventions Group I (claims, #1-10), and Group II are directed to related devices. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed by the device of Group II can be practice for it's intended purpose without requiring wherein next to and spaced from the second group of contact pads, the second group of semiconductor dies, which is required by the claimed device of Group I. Also, the invention as claimed in Group I can be practiced for it's intended purpose without requiring wire bonded to the second group of contact pads within the cavity, as required by the invention of the Group II claim language.
Inventions Group I (claims, #1-10) and Group III are directed to related devices. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed by the device of Group III can be practice for it's intended purpose without requiring wherein next to and spaced from the second group of contact pads, the second group of semiconductor dies, which is required by the claimed device of Group I. Also, the invention as claimed in Group I can be practiced for it's intended purpose without requiring wire bonded to the second group of contact pads within the cavity, as required by the invention of the Group III claim language. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim #21-29 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claims #1-10 will be examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim #1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al., (U.S. Pub. No, 2021/0166991), hereinafter referred to as "Liu" as modified by Pagaila et al., (U.S. Pub. No. 2012/0056312), hereinafter referred to as "Pagaila" and in further view of Hsu et al., (U.S. Pub. No. 2006/0273816), hereinafter referred to as "Hsu".
Liu shows, with respect to claim #1, a semiconductor device, comprising: a signal carrier (fig. #Ex1, item BC1) medium including first (fig. #Ex1, item BS1) and second (fig. #Ex1, item TS1) opposed surfaces; a first group of contact pads (fig. #Ex1, item FP1) on the first surface of the signal carrier medium (paragraph 0011-0012, 0053); a cavity formed in the second surface of the signal carrier medium; a second surface (fig. #Ex1, item TS1) of the signal carrier medium being defined within the cavity the second surface opposing the first surface (fig. #Ex1, item BS1) a second group of contact pads (fig. #Ex1, item TP1) within the cavity (paragraph 0011-0012, 0053); a first group of one or more semiconductor dies (fig. #6, item N, M) mounted on the first surface of the signal carrier medium and electrically coupled to the first group of contact pads on the first surface of the signal carrier medium (paragraph 0039-0040, 0042).
[AltContent: textbox (First Pad; FP1)][AltContent: connector][AltContent: arrow][AltContent: arrow]
[AltContent: textbox (Top Surface; TS1)][AltContent: arrow][AltContent: textbox (Top Pads; TP1)]
[AltContent: arrow][AltContent: textbox (Ex1)][AltContent: textbox (Bottom Surface; BS1)][AltContent: textbox (Bottom Pads; BP1)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: oval][AltContent: textbox (Base Carrier; BC1)][AltContent: oval][AltContent: oval][AltContent: arrow]
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Liu substantially shows the claimed invention as shown in the rejection of claim #1 above.
Liu fails to show, with respect to claim #1, a device comprising a second group of semiconductor dies mounted in the cavity next to and spaced from the second group of contact pads, the second group of semiconductor dies and electrically coupled to the second group of contact pads within the cavity, next to and spaced from the second group of contact pads, the second group of semiconductor dies the second group of semiconductor dies comprising two or more memory dies stacked on each other.
Pagaila teaches, with respect to claim #1, a device comprising a second group of semiconductor dies (fig. #Ex2, item 124a&b) mounted in the cavity (fig. #Ex2, item 124c) and electrically coupled (paragraph 0049-0050) to the second group of contact pads (fig. #Ex2, item 132; also, as shown in fig. #4e, item 132 connect to item 164, 148 and 158), a first group of contact pads (fig. #Ex2, item FP2) within the cavity (fig. #Ex2, item Cy2) (paragraph 0053-0054), next to and spaced from the second group of contact pads (fig. #Ex2, item GP2), the second group of semiconductor dies (fig. #Ex2, item 124c&d) (paragraph 0050) the second group of semiconductor dies comprising two or more memory dies stacked on each other (paragraph 0042).
[AltContent: textbox (First Die Group;FDG2)][AltContent: ][AltContent: textbox (Second Die Group; SDG2)]
[AltContent: arrow][AltContent: ][AltContent: textbox (Cavity; Cy2)][AltContent: arrow][AltContent: ][AltContent: arrow][AltContent: textbox (First Group of Pads; FP2)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Second Group of Pads; GP2)][AltContent: textbox (Ex2)]
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It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #1, to modified the invention of Liu as modified by the invention of Pagaila, which teaches, a device comprising a second group of semiconductor dies mounted in the cavity next to and spaced from the second group of contact pads, the second group of semiconductor dies electrically coupled to the second group of contact pads within the cavity, the second group of semiconductor dies comprising two or more memory dies stacked on each other, to incorporate a structural design that would permit communication through and from any connected dies, as taught by Pagaila.
Liu as modified by Pagaila, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Liu as modified by Pagaila, fails to show, with respect to claim #1, a device wherein a second group of contact pads within the cavity extending partially.
Hsu teaches, with respect to claim #1, a device wherein a second group of contact pads (fig. #2, item 23) within the cavity (fig. #2, item 210) paragraph 0030).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #1, to modified the invention of Liu as modified by Pagaila, with modification of the invention of Hsu, which teaches, a device wherein a second group of contact pads within the cavity extending partially into the signal carrier medium within the cavity, to incorporate wherein a circuit layer can formed on a second surface of the dielectric layer and electrically connected to the electrically contact pads through a plurality of conductive via embedded in the dielectric layer, as taught by Hsu.
Liu as modified by Pagaila and Hsu, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Liu fails to show, with respect to claim #2, a device wherein the first group of one or more semiconductor dies comprise one or more memory dies.
Pagaila teaches, with respect to claim #2, a device wherein the first group of one or more semiconductor dies comprise one or more memory dies (paragraph 0017, 0042).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #2, to modified the invention of Liu as modified by the invention of Pagaila, which teaches, a device wherein the first group of one or more semiconductor dies comprise one or more memory dies, to incorporate a structural design that would permit communication through and from any connected dies, as taught by Pagaila.
//
Claim #3-5, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al., (U.S. Pub. No, 2021/0166991), hereinafter referred to as "Liu" as modified by Pagaila et al., (U.S. Pub. No. 2012/0056312), hereinafter referred to as "Pagaila" and Hsu et al., (U.S. Pub. No. 2006/0273816), hereinafter referred to as "Hsu" as shown in the rejection of claim #1 above, and in further view of Fay et al., (U.S. Pub. No. 2022/0084977), hereinafter referred to as "Fay".
Liu as modified by Pagaila and Hsu, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Liu as modified by Pagaila and Hsu, fails to show, with respect to claim #3, a device wherein the two or more memory dies are stacked on each other with a stepped offset.
Fay teaches, with respect to claim #3, a device wherein the two or more memory dies are stacked on each other with a stepped offset (fig. #2a) (paragraph 0013-0014, 0016).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #3, to modified the invention of Liu as modified by Pagaila and Hsu, with the modifications of Fay, which teaches a device wherein the two or more memory dies are stacked on each other with a stepped offset, to incorporate a structural condition that would allow access to the bond pads of each die in the stack, as taught by Fay.
Liu as modified by Pagaila and Hsu, fails to show, with respect to claim #4, a device further comprising a first set of bond wires configured to electrically couple the first set of one or more semiconductor dies to the first group of contact pads on the first surface of the signal carrier medium.
Fay teaches, with respect to claim #4, a device further comprising a first set of bond wires (fig. #2a, item 226a-d) configured to electrically couple the first set of one or more semiconductor dies (fig. #2a, item 220a-d) to the first group of contact pads (fig. #2a, item 218) on the first surface of the signal carrier medium (paragraph 0013, 0020).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #4, to modified the invention of Liu as modified by Pagaila and Hsu with the modifications of Fay, which teaches a device further comprising a first set of bond wires configured to electrically couple the first set of one or more semiconductor dies to the first group of contact pads on the first surface of the signal carrier medium, to incorporate a structural condition that would allow access to the bond pads of each die in the stack, as taught by Fay.
Liu as modified by Pagaila and Hsu, fails to show, with respect to claim #5, a device further comprising a second set of bond wires configured to electrically couple the second group of semiconductor dies to the second group of contact pads within the cavity.
Fay teaches, with respect to claim #5, a device further comprising a second set of bond wires (fig. #2a, item 326a-d) configured to electrically couple the second group of semiconductor dies (fig. #2a, item 320a-d) to the second group of contact pads (fig. #2a, item 318) within the cavity (paragraph 0013, 0021).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #5, to modified the invention of Liu as modified by Pagaila and Hsu with the modifications of Fay, which teaches a device further comprising a second set of bond wires configured to electrically couple the second group of semiconductor dies to the second group of contact pads within the cavity, to incorporate a structural condition that would allow access to the bond pads of each die in the stack, as taught by Fay.
Liu as modified by Pagaila and Hsu, fails to show, with respect to claim #8, a device wherein the two or more memory dies comprise a plurality of memory dies stacked in two separate stacks within the cavity.
Fay teaches, with respect to claim #8, a device wherein the two or more memory dies comprise a plurality of memory dies (fig. #2a, item 320a-d) stacked in two separate stacks within the cavity (paragraph 0013, 0021).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #8, to modified the invention of Liu as modified by Pagaila and Hsu with the modifications of Fay, which teaches a device a device wherein the two or more memory dies comprise a plurality of memory dies stacked in two separate stacks within the cavity, to incorporate a structural condition that would allow access to the bond pads of each die in the stack, as taught by Fay.
Liu as modified by Pagaila and Hsu, fails to show, with respect to claim #9, a device further comprising a compound encapsulating the first group of one or more semiconductor dies on the first surface of the signal carrier medium.
Fay teaches, with respect to claim #9, a device further comprising a compound encapsulating (fig. #2b, item 260) the first group of one or more semiconductor dies on the first surface of the signal carrier medium (paragraph 0022).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #9, to modified the invention of Liu as modified by Pagaila and Hsu, with the modifications of Fay, which teaches a device further comprising a compound encapsulating the first group of one or more semiconductor dies on the first surface of the signal carrier medium, to incorporate a structural condition that would protect the wire bonds and dies, as taught by Fay.
Liu as modified by Pagaila and Hsu, fails to show, with respect to claim #10, a device wherein the compound comprises a first compound, the semiconductor device further comprising a second compound filling the cavity and encapsulating the second group of semiconductor dies in the cavity.
Fay teaches, with respect to claim #10, a device wherein the compound comprises a first compound, the semiconductor device further comprising a second compound (fig. #2b, item 260) filling the cavity and encapsulating the second group of semiconductor dies in the cavity (paragraph 0022).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #10, to modified the invention of Liu as modified by Pagaila and Hsu with the modifications of Fay, which teaches a device wherein the compound comprises a first compound, the semiconductor device further comprising a second compound filling the cavity and encapsulating the second group of semiconductor dies in the cavity, to incorporate a structural condition that would protect the wire bonds and dies, as taught by Fay.
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Claim #6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al., (U.S. Pub. No, 2021/0166991), hereinafter referred to as "Liu" as modified by Pagaila et al., (U.S. Pub. No. 2012/0056312), hereinafter referred to as "Pagaila" and Hsu et al., (U.S. Pub. No. 2006/0273816), hereinafter referred to as "Hsu" as shown in the rejection of claim #1 above, and in further view of Punzalan et al., (U.S. Pat. No. 12,100,719), hereinafter referred to as "Punzalan".
Liu as modified by Pagaila and Hsu, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Liu as modified by Pagaila and Hsu, fails to show, with respect to claim #6, a device wherein the signal carrier medium has an overall thickness, and the cavity has a depth that is 30% to 90% of the overall thickness of the signal carrier medium.
Punzalan teaches, with respect to claim #6, a device wherein the signal carrier medium has an overall thickness, and the cavity has a depth that is 30% to 90% of the overall thickness of the signal carrier medium (fig. #2a) (column #6, line 25-35).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #6, to modified the invention of Liu as modified by Pagaila and Hsu with the modifications of Punzalan, which teaches a device wherein the signal carrier medium has an overall thickness, and the cavity has a depth that is 30% to 90% of the overall thickness of the signal carrier medium, to incorporate a structural condition wherein the height should be sufficient to protect the wire bonds from being damaged, as taught by Punzalan.
Liu as modified by Pagaila and Hsu, fails to show, with respect to claim #7, a device wherein the signal carrier medium has an overall thickness, and the cavity has a depth that is 50% to 75% of the overall thickness of the signal carrier medium.
Punzalan teaches, with respect to claim #7, a device wherein the signal carrier medium has an overall thickness, and the cavity has a depth that is 50% to 75% of the overall thickness of the signal carrier medium (fig. #2a) (column #6, line 25-35).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #7, to modified the invention of Liu as modified by Pagaila and Hsu with the modifications of Punzalan, which teaches a device wherein the signal carrier medium has an overall thickness, and the cavity has a depth that is 50% to 75% of the overall thickness of the signal carrier medium, to incorporate a structural condition wherein the height should be sufficient to protect the wire bonds from being damaged, as taught by Punzalan.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
01/26/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899