DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 4/15/2026. Claims 1, 6-7, 10, 12-15, 21-21, 24-25, 28-29, 31-32, 34-42, 44, 47, 52-53 and 58-68 have been amended. Claims 69-71 have been added. Claims 8-9 have been canceled. Claims 59-68 were withdrawn. Currently, claims 1-4, 6-7, 10-21, 23-42, 44-58, and 69-71 are pending.
Applicant’s amendment to claim 12 successfully overcomes the objection of claim 12 set forth in the previous Office Action.
Applicant’s amendment to claims 24 and 44 successfully overcomes the 112(d) rejection of claims 24 and 44 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments filed 4/15/2026 have been fully considered and are persuasive. The rejection of independent claims 1 and 42 under 35 USC § 103 has been withdrawn. Upon further consideration, a new rejection in view of Yoneyama and Nakajima et al. is presented below.
Claim Objections
Claim 31 is objected to because of the following informalities: In lines 3-4 of the claim, “upper surface” is repeated twice. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6, which depends directly from claim 1, recites the limitation “the rough surface region” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination with regard to the prior art, “the rough surface region” will be treated as “a rough surface region of a surface in which the plurality of concave portions is formed” (see 9/24/25 claim 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 10, 20-21, and 24 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) embodiment of Fig. 12 in view of Yoneyama et al. (US 10714447) embodiment of Fig. 8, and Nakajima et al. (US 6849930).
Regarding claim 1, Yoneyama teaches, in Fig. 12 separately, a semiconductor module (col. 7, lines 20-25) comprising:
an insulating circuit board (see Fig. 2; base 11, solder 12, insulating substrate 14, and circuit patterns 13a1, 13a2, and 13b; col. 3, lines 35-45; col. 7, lines 40-45) having a circuit pattern (13a2; col. 7, lines 40-45) formed in one (top) surface;
a semiconductor chip (16; col. 7, lines 40-45) placed in the insulating substrate (14) (see Fig. 12); and
a wiring portion (33; col. 7, lines 50-60) that electrically connects the semiconductor chip (16) and the circuit pattern (13a2) (see Fig. 12; col. 7, lines 50-60); and
wherein the wiring portion (33) includes a chip connecting portion (left portion; see, for example, Fig. 8) connected to the semiconductor chip (16) (see Fig. 12).
Yoneyama, in Fig. 12 separately, does not teach that a surface of the chip connecting portion includes a plurality of concave portions, that the surface of the chip connecting portion includes a flat portion disposed between two concave portions of the plurality of concave portions, that the plurality of concave portions and the flat portion are formed at least in an edge surface of the chip connecting portion, and that the plurality of concave portions is periodically disposed in at least two directions of the edge surface.
Yoneyama, in Fig. 8 (see annotated figure below), teaches that a (left, see annotated Fig. 8 below) surface of the chip connecting portion (of 33) includes a plurality of concave portions (31b; col. 6, lines 25-35), that the (left) surface of the chip connecting portion includes a flat portion (see annotated Fig. 8 below) disposed between two concave portions of the plurality of concave portions (31b), and that the plurality of concave portions and the flat portion are formed at least in an edge (left) surface of the chip connecting portion (see annotated Fig. 8 below), in order to “reduce impedance in a high-frequency switching operation” (col. 6, lines 40-45).
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Yoneyama Fig. 8 (annotated version 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module embodiment of Yoneyama Fig. 12 with the chip connecting portion embodiment of Yoneyama Fig. 8, in order to “reduce impedance in a high-frequency switching operation” (col. 6, lines 40-45).
Yoneyama does not explicitly teach that the plurality of concave portions is periodically disposed in at least two directions of the edge surface.
In a similar field of endeavor, Nakajima teaches, in Fig. 4A, that the plurality of concave portions (53; col. 11, lines 50-55) is periodically disposed in at least two directions (horizontal and vertical) of the edge surface, in order to improve the adhesion strength between the metal plate and the molding resin (col. 8, lines 20-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama with the concave portion distribution of Nakajima, in order to improve the adhesion strength between the metal plate and the molding resin (col. 8, lines 20-35).
Regarding claim 10, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama in view of Nakajima further teaches that the plurality of concave portions (31b, Yoneyama Fig. 8) is disposed with a predetermined gap in a lateral (horizontal) direction parallel to a lower surface of the chip connecting portion (because as set forth in claim 1 above, the concave portions 31b in the edge surface of Yoneyama Fig. 8 are modified by Nakajima such that 31b are periodically disposed in at least two directions of the edge surface, thus each 31b has a horizontal gap in between each 31b); and
that the plurality of concave portions includes concave portions disposed side by side with the gap in a height direction perpendicular to the lateral direction (the plurality of 31b in the annotated edge surface of Yoneyama in claim 1 would be side by side with the gap).
Regarding claim 20, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama further teaches, in Fig. 8, that the plurality of concave portions (31b) and the flat portion are formed in the edge surface, a side surface (right surface), and an upper surface of the chip connecting portion (see annotated Fig. 8 below).
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Yoneyama Fig. 8 (annotated version 2)
Regarding claim 21, Yoneyama in view of Nakajima teaches the limitations of claim 1. Nakajima further teaches, in Figs. 4A-4B, that the wiring portion (51; col. 12, lines 40-45) is a lead frame having a plate-shaped portion (left portion);
the flat portion includes a raised portion (surface area to the right and left of the middle section of the flat portion, and the area is raised with respect to the concave portions 53) of which a height in a height direction perpendicular to a surface of the chip connecting portion is a same as that of the standard portion or raised in the height direction from the standard portion portion (see Fig. 4B how the heights of the standard portion and the raised portion are the same);
at least some concave portions (53) of the plurality of concave portions are disposed to be recessed from the standard portion in the height direction (see Fig. 5 how concave portions 53 are recessed in the vertical direction with respect to the standard portion); and
the raised portion is provided adjacent to the at least some concave portions (53) (see Figs. 4A-4B).
Regarding claim 24, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama further teaches, in Fig. 8, that the plurality of concave portions (31b) and the flat portion are formed in an upper surface of the chip connection portion (see annotated Fig. 8 below).
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Yoneyama Fig. 8 (annotated version 2 repeated)
Claims 2-3, 7, and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Hu et al. (US 7859089).
Regarding claim 2, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama in view of Nakajima does not teach that a maximum width of each of the plurality of concave portions is 10 µm or more.
In a similar field of endeavor, Hu teaches, in Figs. 2A and 2B, that a maximum width of each of the plurality of concave portions (202) is 10 µm or more (col. 4, lines 10-15; 0.24 mm), “for better control of the solder joint between the contact and a die electrode(s) and for an improved connection between the contact and the die electrode(s)” (col. 4, lines 10-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the concave portion sizes of Hu, in order to improve the physical connection of the chip connecting portion.
Regarding claim 3, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama in view of Nakajima does not teach that an interval of centers of at least two concave portions which are adjacent among the plurality of concave portions is 10 µm or more.
In a similar field of endeavor, Hu teaches, in Figs. 3A and 3B, that an interval of centers of at least two concave portions (202) which are adjacent among the plurality of concave portions is 10 µm or more (col. 4, lines 10-20; the minimum distance between the centers of two concave portions 202 is 0.24 mm), “for better control of the solder joint between the contact and a die electrode(s) and for an improved connection between the contact and the die electrode(s)” (col. 4, lines 10-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the concave portions of Hu, in order to improve the physical connection of the chip connecting portion.
Regarding claim 7, Yoneyama in view of Nakajima teaches the limitations of claim 1. Nakajima further teaches, in Fig. 4A, that the plurality of concave portions (53; col. 11, lines 50-55) is periodically disposed in at least two directions (horizontal and vertical) of at least any one surface of the chip connection portion.
Yoneyama in view of Nakajima does not teach that any one surface of the chip connecting portion includes an unprocessed portion in which the periodic arrangement of the plurality of concave portions is interrupted.
In a similar field of endeavor, Hu teaches that any one surface of the chip connecting portion includes an unprocessed portion in which the periodic arrangement of the plurality of concave portions is interrupted (see Fig. 3A how in the middle portion of 300a, the periodic arrangement of concave portions 202 is interrupted; col. 4, lines 10-15), “for better control of the solder joint between the contact and a die electrode(s) and for an improved connection between the contact and the die electrode(s)” (col. 4, lines 10-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the concave portion distribution of Hu, in order to improve the physical connection of the chip connecting portion.
Regarding claim 11, Yoneyama in view of Nakajima teaches the limitations of claim 10. However, Yoneyama in view of Nakajima does not explicitly teach that widths of at least one concave portion of the plurality of concave portions in the lateral direction are larger than a width of the gap. Nonetheless, the skilled artisan would know too that widths of concave portions would impact “control of the solder joint between the contact and a die electrode(s)” and “connection between the contact and the die electrode(s)” (Hu; col. 4, lines 10-15).
The specific claimed widths, absent any criticality, is only considered to be the “optimum” widths disclosed by Yoneyama in view of Nakajima and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder joint control, contact connection, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as widths of at least one concave portion of the plurality of concave portions in the lateral direction being larger than a width of the gap is used, as already suggested by Yoneyama in view of Nakajima and Hu.
Since the applicant has not established the criticality (see next paragraph) of the widths stated and since these widths are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed widths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 12, Yoneyama in view of Nakajima teaches the limitations of claim 1. However, Yoneyama in view of Nakajima does not explicitly teach that at least one concave portion of the plurality of concave portions has a width in a lateral direction parallel to a lower surface of the chip connecting portion larger than a width in a height direction perpendicular to the lateral direction. Nonetheless, the skilled artisan would know too that widths of concave portions would impact “control of the solder joint between the contact and a die electrode(s)” and “connection between the contact and the die electrode(s)” (Hu; col. 4, lines 10-15).
The specific claimed widths, absent any criticality, is only considered to be the “optimum” widths disclosed by Yoneyama in view of Nakajima and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder joint control, contact connection, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as at least one concave portion of the plurality of concave portions having a width in a lateral direction parallel to a lower surface of the chip connecting portion larger than a width in a height direction perpendicular to the lateral direction is used, as already suggested by Yoneyama in view of Nakajima and Hu.
Since the applicant has not established the criticality (see next paragraph) of the widths stated and since these widths are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed widths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 13, Yoneyama in view of Nakajima teaches the limitations of claim 1. However, Yoneyama in view of Nakajima does not explicitly teach that a density of concave portions in a lateral direction parallel to a lower surface of the chip connecting portion of the plurality of concave portions is higher than a density of concave portions in a height direction perpendicular to the lateral direction. Nonetheless, the skilled artisan would know too that distances between concave portions would impact “control of the solder joint between the contact and a die electrode(s)” and “connection between the contact and the die electrode(s)” (Hu; col. 4, lines 10-15).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder joint control, contact connection, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a density of concave portions in a lateral direction parallel to a lower surface of the chip connecting portion of the plurality of concave portions being higher than a density of concave portions in a height direction perpendicular to the lateral direction is used, as already suggested by Yoneyama in view of Nakajima and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 14, Yoneyama in view of Nakajima teaches the limitations of claim 1. However, Yoneyama in view of Nakajima does not explicitly teach that a density of concave portions in a height direction perpendicular to a lower surface of the chip connecting portion of the plurality of concave portions is higher with increasing distance from the lower surface. Nonetheless, the skilled artisan would know too that distances between concave portions would impact “control of the solder joint between the contact and a die electrode(s)” and “connection between the contact and the die electrode(s)” (Hu; col. 4, lines 10-15).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder joint control, contact connection, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a density of concave portions in a height direction perpendicular to a lower surface of the chip connecting portion of the plurality of concave portions being higher with increasing distance from the lower surface is used, as already suggested by Yoneyama in view of Nakajima and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Kohl et al. (US 9406592).
Regarding claim 4, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama further teaches, in Fig. 8, a bonding layer (16b and 32; col. 5, lines 15-30) for bonding the semiconductor chip (16) and the chip connecting portion (of 33).
Yoneyama in view of Nakajima does not teach that the bonding layer is provided in inner portions of at least one concave portion of the plurality of concave portions.
In a similar field of endeavor, Kohl teaches that the bonding layer is provided in inner portions of at least one concave portion of the plurality of concave portions (A) (col. 4, lines 10-20; see Fig. 5, solder layers enter the concave portions A), in order to reduce the stress (col. 4, lines 14-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the bonding layer and concave portion configuration of Kohl, in order to reduce the stress (col. 4, lines 14-30).
Claims 6 and 69-70 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Nakatsugawa et al. (JP 2019207905 A, citations made hereinafter to the English Machine Translation attached to the Office Action mailed on 1/16/2026).
Regarding claim 6, Yoneyama in view of Nakajima teaches the limitations of claim 1. Nakajima further teaches that a surface in which the plurality of concave portions (53; see Fig. 4B; col. 11, lines 50-55) is formed includes a rough surface region (54; Fig. 5A; col. 12, lines 40-45).
Yoneyama in view of Nakajima does not explicitly teach that the rough surface region has a developed interfacial area ratio of 0.7 or less.
In a similar field of endeavor, Nakatsugawa teaches that the rough surface region has a developed interfacial area ratio of 0.3 or more and 0.8 or less ([0020]), “in order to obtain sufficient resin adhesion to the roughened surface portion” ([0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the developed interfacial area ratio of the rough surface region of Nakatsugawa, in order to obtain sufficient resin adhesion to the rough surface region ([0021]).
However, Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that the rough surface region has a developed interfacial area ratio of 0.7 or less. Nonetheless, the skilled artisan would know too that the surface roughness would impact resin adhesion to the rough surface region (Nakatsugawa, [0021]).
The specific claimed surface roughness, absent any criticality, is only considered to be the “optimum” surface roughness disclosed by Yoneyama in view of Nakajima and Nakatsugawa that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired resin adhesion, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the rough surface region having a developed interfacial area ratio of 0.7 or less is used, as already suggested by Yoneyama in view of Nakajima and Nakatsugawa.
Since the applicant has not established the criticality (see next paragraph) of the surface roughness stated and since these levels of surface roughness are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Nakatsugawa.
Please note that the specification contains no disclosure of either the critical nature of the claimed surface roughness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 69, Yoneyama in view of Nakajima teaches the limitations of claim 1. Nakajima further teaches that a surface in which the plurality of concave portions (53; see Fig. 4B; col. 11, lines 50-55) is formed includes has a rough surface region (54) (col. 12, lines 40-45; see Fig. 5B).
Yoneyama in view of Nakajima does not explicitly teach that a developed interfacial area ratio of the rough surface region of the wiring portion is 0.2 or more, wherein the developed interfacial area ratio of the rough surface region and the developed interfacial ratio of the circuit pattern is an increase ratio of area compared to a completely flat area.
In a similar field of endeavor, Nakatsugawa teaches that the rough surface region has a developed interfacial area ratio of 0.2 or more ([0020], “0.3 or more and 0.8 or less,” which falls within the range of 0.2 or more), wherein the developed interfacial area ratio is an increase ratio of area compared to a completely flat area ([0020]), “in order to obtain sufficient resin adhesion to the roughened surface portion” ([0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the developed interfacial area ratio of the rough surface region of Nakatsugawa, in order to obtain sufficient resin adhesion to the rough surface region ([0021]).
Regarding claim 70, Yoneyama in view of Nakajima teaches the limitations of claim 21. Nakajima further teaches that the surface of the chip connecting portion (51; col. 12, lines 40-45) that includes the plurality of concave portions (53; see Fig. 4B; col. 11, lines 50-55) includes has a rough surface region (54) (col. 12, lines 40-45; see Fig. 5B).
Yoneyama in view of Nakajima does not explicitly teach that a developed interfacial area ratio of the rough surface region of the wiring portion is 0.1 or more, wherein the developed interfacial area ratio of the rough surface region and the developed interfacial ratio of the circuit pattern is an increase ratio of area compared to a completely flat area.
In a similar field of endeavor, Nakatsugawa teaches that the rough surface region has a developed interfacial area ratio of 0.1 or more ([0020], “0.3 or more and 0.8 or less,” which falls within the range of 0.1 or more), wherein the developed interfacial area ratio is an increase ratio of area compared to a completely flat area ([0020]), “in order to obtain sufficient resin adhesion to the roughened surface portion” ([0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the developed interfacial area ratio of the rough surface region of Nakatsugawa, in order to obtain sufficient resin adhesion to the rough surface region ([0021]).
Claims 15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Miura (JP 2009004435 A, citations made hereinafter to the English machine translation filed by Applicant on April 6, 2025), cited by Applicant in the Information Disclosure Statement filed on April 6, 2025, and Kuroda (JP 2013118322 A, citations made hereinafter to the English machine translation filed by Applicant on 5/19/2022), cited by Applicant in the Information Disclosure Statement filed on 5/19/2022.
Regarding claim 15, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama in view of Nakajima does not explicitly teach that the chip connecting portion includes a main material portion; and the chip connecting portion includes an inhibition portion formed of a material having solder wettability lower than the main material portion and disposed to be exposed at the edge surface.
In a similar field of endeavor, Miura teaches, in Fig. 11, that the chip connecting portion ([0066], left portion of 130 connected to 1) includes a main material portion (131a and 131b, [0066]); and the chip connecting portion includes an inhibition portion (132, [0066]-[0067]) disposed to be exposed at the edge surface (left surface of 130), in order to “provide a semiconductor device capable of reducing resistance to a high frequency current in a strap connecting a semiconductor chip and a lead” ([0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the chip connecting portion of Miura, in order to provide a semiconductor device capable of reducing resistance to a high frequency current in a strap connecting a semiconductor chip and a lead.
Yoneyama in view of Nakajima and Miura does not explicitly teach that the inhibition portion is formed of a material having solder wettability lower than the main material portion.
In a similar field of endeavor, Kuroda teaches that the inhibition portion (6, Fig. 2, [0030]) is formed of a material having solder wettability lower ([0032]) than the main material portion (3, 5c and 4; Fig. 1, [0030]), so that “the solder is suppressed from outflowing, for example horizontally, over this top surface 4a” ([0030], see Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima and Miura with the inhibition portion of Kuroda, so that the solder is suppressed from outflowing.
Regarding claim 17, Yoneyama in view of Nakajima, Miura, and Kuroda teaches the limitations of claim 15. Miura further teaches that the inhibition portion (131b) is stacked with the main material portion (131a and 131b) in a height direction perpendicular to a lower surface (bottom surface) of the chip connecting portion (130) (see Fig. 11 how 131a, 131b, and 132b are stacked vertically).
Regarding claim 18, Yoneyama in view of Nakajima, Miura, and Kuroda teaches the limitations of claim 15. Kuroda further teaches that the inhibition portion (6) is stacked with the main material portion (3a, 5c, and 4) in a direction perpendicular to the edge surface of the chip connecting portion (see Fig. 2 how 6 is horizontally stacked with 3a).
Regarding claim 19, Yoneyama in view of Nakajima, Miura, and Kuroda teaches the limitations of claim 15. Kuroda further teaches that the inhibition portion (6) protrudes or is recessed from the main material portion (3a, 5c, and 4) in a direction perpendicular to the edge surface of the chip connecting portion (see Fig. 2 how 6 is recessed horizontally from 4).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), Miura (JP 2009004435 A, citations made hereinafter to the English machine translation filed by Applicant on April 6, 2025), cited by Applicant in the Information Disclosure Statement filed on April 6, 2025, and Kuroda (JP 2013118322 A, citations made hereinafter to the English machine translation filed by Applicant on 5/19/2022), cited by Applicant in the Information Disclosure Statement filed on 5/19/2022, and further in view of Kaizu et al. (US 11710709).
Regarding claim 16, Yoneyama in view of Nakajima, Miura, and Kuroda teaches the limitations of claim 15. Yoneyama in view of Nakajima, Miura, and Kuroda does not explicitly teach that in the edge surface, a width of the inhibition portion in a height direction perpendicular to a lower surface of the chip connecting portion is larger than a width of the main material portion in the height direction.
In a similar field of endeavor, Kaizu teaches, in Fig. 10, that in the edge surface (left surface), a width of the inhibition portion (20a) in a height direction (vertical) perpendicular to a lower surface of the chip connecting portion (20) is larger than a width of the main material portion (20b) in the height direction (col. 13, lines 30-40), so that “the thermal stress acting on each of the bonding members or the semiconductor chip can be reduced,” “warpage of the terminal member can be suppressed, and a local stress acting on each of the bonding members or the semiconductor chip can be suppressed” (col. 3, lines 25-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima, Miura, and Kuroda with the inhibition portion and main material portion of Kaizu, so that the thermal stress acting on each of the bonding members or the semiconductor chip can be reduced, warpage of the terminal member can be suppressed, and a local stress acting on each of the bonding members or the semiconductor chip can be suppressed.
Claims 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Matsunaga et al. (JP 2008211168 A, citations made hereinafter to the English machine translation filed by Applicant on 5/19/2022), cited by Applicant in the Information Disclosure Statement filed on 5/19/2022.
Regarding claim 23, Yoneyama in view of Nakajima teaches the limitations of claim 21. Yoneyama in view of Nakajima does not explicitly teach that a depth of each of the plurality of concave portions is 20 µm or more and 200 µm or less.
In a similar field of endeavor, Matsunaga teaches, in Fig. 11, that a depth of each of the plurality of concave portions (9) is 20 µm or more and 200 µm or less ([0028], 20 to 50 µm), so that “the connection strength between the ribbon wire 1 and the ceramic layer 2 is improved, and peeling of the ribbon wire 1 can be more effectively suppressed” and “[a]s result, a highly reliable power semiconductor device 130 can be provided” ([0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the concave portions of Matsunaga, in order to improve the physical connection of the wiring portion ([0030]).
Regarding claim 25, Yoneyama in view of Nakajima teaches the limitations of claim 24. Yoneyama further teaches, in Fig. 8, that the plurality of concave portions (31b) and the flat portion are formed in the edge surface of the chip connecting portion (see claim 1 above).
However, Yoneyama in view of Nakajima does not explicitly teach that a depth of at least one concave portion formed in the upper surface among the plurality of concave portions is deeper than a depth of at least one concave portion formed in the edge surface. Nonetheless, the skilled artisan would know too that depths of concave portions would impact connection strength between the wiring portion and a ceramic layer (Matsunaga; [0030]).
The specific claimed depths, absent any criticality, is only considered to be the “optimum” depths disclosed by Yoneyama in view of Nakajima and Matsunaga that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired connection strength between the wiring portion and a ceramic layer, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a depth of at least one concave portion formed in the upper surface among the plurality of concave portions being deeper than a depth of at least one concave portion formed in the edge surface is used, as already suggested by Yoneyama in view of Nakajima and Matsunaga.
Since the applicant has not established the criticality (see next paragraph) of the depths stated and since these depths are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Matsunaga.
Please note that the specification contains no disclosure of either the critical nature of the claimed depths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 26-27 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Kamiyama et al. (US 9966327).
Regarding claim 26, Yoneyama in view of Nakajima teaches the limitations of claim 21. Yoneyama in view of Nakajima does not explicitly teach that the plurality of concave portions includes a die hole.
In a similar field of endeavor, Kamiyama teaches that the plurality of concave portions includes a die hole (col. 6, lines 15-30), “in order to reduce the degree of package warping due to a temperature change” (col. 1, lines 50-60).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the concave portions of Kamiyama, in order to reduce the degree of package warping due to a temperature change.
Regarding claim 27, Yoneyama in view of Nakajima teaches the limitations of claim 26. Yoneyama further teaches that the plurality of concave portions (31b) includes a laser hole (col. 6, lines 30-40).
Regarding claim 30, Yoneyama in view of Nakajima teaches the limitations of claim 21. Yoneyama in view of Nakajima does not explicitly teach that at least some concave portions of the plurality of concave portions are compressed more than the flat portion.
In a similar field of endeavor, Kamiyama teaches that at least some concave portions of the plurality of concave portions are compressed more than the flat portion (col. 6, lines 15-30), “in order to reduce the degree of package warping due to a temperature change” (col. 1, lines 50-60).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the concave portions of Kamiyama, in order to reduce the degree of package warping due to a temperature change.
Claims 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Hasegawa et al. (US 8866279).
Regarding claim 28, Yoneyama in view of Nakajima teaches the limitations of claim 21. Yoneyama further teaches, in Fig. 8, that the plurality of concave portions (31b) and the flat portion are formed in an upper surface of the chip connection portion (see annotated Fig. 8 below).
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Yoneyama Fig. 8 (annotated version 2 repeated)
Yoneyama in view of Nakajima does not teach that a shape of each of the plurality of concave portions in the upper surface is a polygonal shape.
In a similar field of endeavor, Hasegawa teaches that a shape of each of the plurality of concave portions (324, Fig. 5B) in the upper surface (of chip connecting portion 101) is a polygonal shape (see Fig. 4B; col. 7, lines 15-20; triangle), to have “a semiconductor device which has both a reduced size and improved heat dissipation characteristics” (col. 2, lines 5-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the upper surface and concave portions of Hasegawa, in order to have a semiconductor device which has both a reduced size and improved heat dissipation characteristics.
Regarding claim 29, Yoneyama in view of Nakajima and Hasegawa teaches the limitations of claim 28. Yoneyama further teaches that that the plurality of concave portions (31b) and the flat portion are formed at least in an edge (left) surface of the chip connecting portion, and
a shape of each of the plurality of concave portions (31b) in the edge surface has a curved line (see Fig. 8).
Claims 31 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Kobayashi et al. (JP 2018067600 A, citations made hereinafter to the English machine translation filed by Applicant on 5/19/2022), cited by Applicant in the Information Disclosure Statement filed on 5/19/2022.
Regarding claim 31, Yoneyama in view of Nakajima teaches the limitations of claim 21. Yoneyama further teaches, in Fig. 8, that the plurality of concave portions (31b) and the flat portion are formed in an upper surface and the edge surface of the chip connection portion (see annotated Fig. 8 below).
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Yoneyama Fig. 8 (annotated version 2 repeated)
Yoneyama in view of Nakajima does not explicitly teach that a bottom portion of at least one concave portion formed in the upper surface among the plurality of concave portions is disposed on an opposite side to the edge surface of the chip connecting portion with respect to a center of the concave portion.
In a similar field of endeavor, Kobayashi teaches, in Fig. 14, that a bottom portion of at least one concave portion (26) formed in the upper surface (top surface of 2) among the plurality of concave portions (26) is disposed on an opposite side to the edge surface (right surface) of the chip connecting portion (2, [0006]) with respect to a center of the concave portion (see Fig. 14 how the bottom portion of 26 is disposed to the left of the center of 26), in order to “improve adhesion to a resin member ([0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the concave portions of Kobayashi, in order to improve adhesion to a resin member.
Regarding claim 36, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama in view of Nakajima does not explicitly teach that the surface of the chip connecting portion is provided with an overlapping portion where adjacent concave portions among the plurality of concave portions overlap each other; and the surface of the chip connecting portion is provided with a non-overlapping portion where the flat portion is provided between adjacent concave portions among the plurality of concave portions; and the overlapping portion is provided inside the surface as compared with the non-overlapping portion.
In a similar field of endeavor, Kobayashi teaches, in Fig. 18, that the surface (top surface of 2, [0006]) of the chip connecting portion is provided with an overlapping portion where adjacent concave portions among the plurality of concave portions (26) overlap each other (see Fig. 18, 25); and the surface of the chip connecting portion is provided with a non-overlapping portion where the flat portion is provided between adjacent concave portions among the plurality of concave portions (see Fig. 18, flat surfaces between areas 25); and the overlapping portion is provided inside the surface as compared with the non-overlapping portion (see Fig. 14 how overlapping portion 26 is inside the surface of 2), in order to “improve adhesion to a resin member ([0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the concave portions of Kobayashi, in order to improve adhesion to a resin member.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930) and Kobayashi et al. (JP 2018067600 A, citations made hereinafter to the English machine translation filed by Applicant on 5/19/2022), cited by Applicant in the Information Disclosure Statement filed on 5/19/2022, and further in view of Matsunaga et al. (JP 2008211168 A, citations made hereinafter to the English machine translation filed by Applicant on 5/19/2022), cited by Applicant in the Information Disclosure Statement filed on 5/19/2022.
Regarding claim 32, Yoneyama in view of Nakajima and Kobayashi teaches the limitations of claim 31. However, Yoneyama in view of Nakajima and Kobayashi does not explicitly teach that a depth of a concave portion among the plurality of concave portions formed in the upper surface becomes shallower with increasing distance from the edge surface. Nonetheless, the skilled artisan would know too that depths of concave portions would impact connection strength between the wiring portion and a ceramic layer (Matsunaga; [0030]).
The specific claimed depths, absent any criticality, is only considered to be the “optimum” depths disclosed by Yoneyama in view of Nakajima, Kobayashi, and Matsunaga that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired connection strength between the wiring portion and a ceramic layer, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a depth of at least one concave portion among the plurality of concave portions formed in the upper surface being deeper than a depth of at least one concave portion formed in the edge surface is used, as already suggested by Yoneyama in view of Nakajima, Kobayashi, and Matsunaga.
Since the applicant has not established the criticality (see next paragraph) of the depths stated and since these depths are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima, Kobayashi, and Matsunaga.
Please note that the specification contains no disclosure of either the critical nature of the claimed depths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 33-35 and 37-41 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) in view of Nakajima et al. (US 6849930), and further in view of Nakamura (JP 2018046214 A, citations made hereinafter to the English machine translation attached to the Office Action mailed on 5/30/2025) and Hu et al. (US 7859089).
Regarding claim 33, Yoneyama in view of Nakajima teaches the limitations of claim 24. However, Yoneyama in view of Nakajima does not explicitly teach that a shortest distance between the plurality of concave portions and at least one end side of the surface is larger than an interval of concave portions which are adjacent among the plurality of concave portions. Nonetheless, the skilled artisan would know too that a distance between a concave portion and an end side of a surface would impact “spreading of the solder” (Nakamura; see Fig. 3; [0046]), and that a interval of concave portions would impact “control of the solder joint between the contact and a die electrode(s)” and “connection between the contact and the die electrode(s)” (Hu; col. 4, lines 10-15).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima, Nakamura, and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder spreading, solder joint control, contact/die electrode connection, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a shortest distance between the plurality of concave portions and at least one end side of the surface being larger than an interval of concave portions which are adjacent among the plurality of concave portions is used, as already suggested by Yoneyama in view of Nakajima, Nakamura, and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima, Nakamura, and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 34, Yoneyama in view of Nakajima, Nakamura, and Hu teaches the limitations of claim 33. Yoneyama further teaches that the plurality of concave portions (31b) and the flat portion are formed in the edge (left) surface of the chip connection portion (see claim 1 above), and
the upper surface of the chip connecting portion and the edge (left) surface of the chip connecting portion are connected at an end side (left end side of the upper surface).
However, Yoneyama in view of Nakajima, Nakamura, and Hu does not explicitly teach that a shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the end side is larger than a shortest distance between a concave portion among the plurality of concave portions formed in the edge surface of the chip connecting portion and the end side. Nonetheless, the skilled artisan would know too that a distance between a concave portion and an end side of a surface would impact “spreading of the solder” (Nakamura; see Fig. 3; [0046]).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima, Nakamura, and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder spreading, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the end side being larger than a shortest distance between a concave portion among the plurality of concave portions formed in the edge surface of the chip connecting portion and the end side is used, as already suggested by Yoneyama in view of Nakajima, Nakamura, and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima, Nakamura, and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 35, Yoneyama in view of Nakajima, Nakamura, and Hu teaches the limitations of claim 33. Yoneyama further teaches, in Fig. 8, that the plurality of concave portions (31b) and the flat portion are formed in a side surface (col. 6, lines 25-35; surface facing away from the page) of the chip connecting portion; and
the upper surface of the chip connecting portion and the side surface of the chip connecting portion are connected at an end side (end side of upper surface facing away from the page).
However, Yoneyama in view of Nakajima, Nakamura, and Hu does not explicitly teach that a shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the end side is larger than a shortest distance between a concave portion among the plurality of concave portions formed in the side surface of the chip connecting portion and the end side. Nonetheless, the skilled artisan would know too that a distance between a concave portion and an end side of a surface would impact “spreading of the solder” (Nakamura; see Fig. 3; [0046]).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima, Nakamura, and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder spreading, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the end side being larger than a shortest distance between a concave portion among the plurality of concave portions formed in the side surface of the chip connecting portion and the end side is used, as already suggested by Yoneyama in view of Nakajima, Nakamura, and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima, Nakamura, and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 37, Yoneyama in view of Nakajima teaches the limitations of claim 1. Yoneyama further teaches, in Fig. 8, that the plurality of concave portions (31b) and the flat portion are formed in an upper surface of the chip connection portion (of 33) (see annotated Fig. 8 below); and
the upper surface has a first end side (facing away from the page) and a second end side (facing into the page) opposite to the first end side.
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Yoneyama Fig. 8 (annotated version 2 repeated)
However, Yoneyama in view of Nakajima does not explicitly teach that a maximum distance in intervals of concave portions among the plurality of concave portions sandwiched between the first end side and the second end side is larger than a first shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the first end side and a second shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the second end side. Nonetheless, the skilled artisan would know too that a distance between a concave portion and an end side of a surface would impact “spreading of the solder” (Nakamura; see Fig. 3; [0046]), and that an interval of concave portions would impact “control of the solder joint between the contact and a die electrode(s)” and “connection between the contact and the die electrode(s)” (Hu; col. 4, lines 10-15).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima, Nakamura, and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder spreading, solder joint control, contact/die electrode connection, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a maximum distance in intervals of concave portions among the plurality of concave portions sandwiched between the first end side and the second end side being larger than a first shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the first end side and a second shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the second end side is used, as already suggested by Yoneyama in view of Nakajima, Nakamura, and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima, Nakamura, and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 38, Yoneyama in view of Nakajima, Nakamura, and Hu teaches the limitations of claim 37. However, Yoneyama in view of Nakajima, Nakamura, and Hu does not explicitly teach that an interval of concave portions among the plurality of concave portions at a center between the first end side and the second end side of the upper surface of the chip connecting portion is larger than the first shortest distance and the second shortest distance. Nonetheless, the skilled artisan would know too that a distance between a concave portion and an end side of a surface would impact “spreading of the solder” (Nakamura; see Fig. 3; [0046]), and that a interval of concave portions would impact “control of the solder joint between the contact and a die electrode(s)” and “connection between the contact and the die electrode(s)” (Hu; col. 4, lines 10-15).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima, Nakamura, and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder spreading, solder joint control, contact/die electrode connection, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as that an interval of concave portions among the plurality of concave portions at a center between the first end side and the second end side of the upper surface of the chip connecting portion being larger than the first shortest distance and the second shortest distance is used, as already suggested by Yoneyama in view of Nakajima, Nakamura, and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima, Nakamura, and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 39, Yoneyama in view of Nakajima, Nakamura, and Hu teaches the limitations of claim 37. Hu further teaches, in Figs. 3A and 3B, that an interval of concave portions among the plurality of concave portions (202) at a center between the first end side (left side of 300a) and the second end side of the upper surface of the chip connecting portion (right side of 300a) is the maximum distance (col. 4, lines 10-20).
Regarding claim 40, Yoneyama in view of Nakajima, Nakamura, and Hu teaches the limitations of claim 37. Yoneyama further teaches, in Fig. 8, that the upper surface further has a third end side (left side) in contact with the first end side and the second end side.
However, Yoneyama in view of Nakajima, Nakamura, and Hu does not explicitly teach that a shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the third end side is larger than the first shortest distance and the second shortest distance. Nonetheless, the skilled artisan would know too that a distance between a concave portion and an end side of a surface would impact “spreading of the solder” (Nakamura; see Fig. 3; [0046]).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima, Nakamura, and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder spreading, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as that a shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the third end side being larger than the first shortest distance and the second shortest distance is used, as already suggested by Yoneyama in view of Nakajima, Nakamura, and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima, Nakamura, and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 41, Yoneyama in view of Nakajima, Nakamura, and Hu teaches the limitations of claim 40. Yoneyama further teaches that the plurality of concave portions (31b) and the flat portion are formed in the edge (left) surface of the chip connection portion (see claim 1 above), and
the upper surface of the chip connecting portion and the edge (left) surface of the chip connecting portion are connected at the third end side (left end side of the upper surface).
However, Yoneyama in view of Nakajima, Nakamura, and Hu does not explicitly teach that a shortest distance between a concave portion formed in the upper surface of the chip connecting portion among the plurality of concave portions and the third end side is larger than a shortest distance between a concave portion formed in the edge surface of the chip connecting portion and the third end side. Nonetheless, the skilled artisan would know too that a distance between a concave portion and an end side of a surface would impact “spreading of the solder” (Nakamura; see Fig. 3; [0046]).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Yoneyama in view of Nakajima, Nakamura, and Hu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired solder spreading, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a shortest distance between a concave portion among the plurality of concave portions formed in the upper surface of the chip connecting portion and the third end side being larger than a shortest distance between a concave portion among the plurality of concave portions formed in the edge surface of the chip connecting portion and the third end side is used, as already suggested by Yoneyama in view of Nakajima, Nakamura, and Hu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima, Nakamura, and Hu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 42, 44-47, 49, 52-53, 55-57, and 71 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama et al. (US 10714447) embodiment of Fig. 12 in view of Yoneyama et al. (US 10714447) embodiment of Fig. 8, Nakajima et al. (US 6849930), and Nakatsugawa et al. (JP 2019207905 A, citations made hereinafter to the English Machine Translation attached to the Office Action mailed on 1/16/2026).
Regarding claim 42, Yoneyama teaches, in Fig. 12 separately, a semiconductor module (col. 7, lines 20-25) comprising:
an insulating circuit board (see Fig. 2; base 11, solder 12, insulating substrate 14, and circuit patterns 13a1, 13a2, and 13b; col. 3, lines 35-45; col. 7, lines 40-45) having a circuit pattern (13a2; col. 7, lines 40-45) formed in one (top) surface;
a semiconductor chip (16; col. 7, lines 40-45) placed in the insulating substrate (14) (see Fig. 12);
a wiring portion (33; col. 7, lines 50-60) that connects the semiconductor chip (16) and the circuit pattern (13a2) (see Fig. 12; col. 7, lines 50-60); and
a resin package (24 and 25; col. 3, lines 50-60; col. 6, lines 60-65) for protecting the semiconductor chip (16).
Yoneyama, in Fig. 12 separately, does not teach that the wiring portion has a rough surface region, wherein a developed interfacial area ratio of the rough surface region of the wiring portion is 0.2 or more, wherein the developed interfacial area ratio of the rough surface region and the developed interfacial ratio of the circuit pattern is an increase ratio of area compared to a completely flat area, wherein a plurality of concave portions and a flat portion are formed at least in an edge surface of the wiring portion, and wherein the plurality of concave portions is periodically disposed in at least two directions of the edge surface.
Yoneyama, in Fig. 8 (see annotated figure below), teaches that the wiring portion has a rough surface region (see annotated figure below); and
that a plurality of concave portions (31b; col. 6, lines 25-35) and a flat portion (see annotated Fig. 8 below) are formed at least in an edge (left) surface of the wiring portion (see annotated Fig. 8 below), in order to “reduce impedance in a high-frequency switching operation” (col. 6, lines 40-45).
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Yoneyama Fig. 8 (annotated)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module embodiment of Yoneyama Fig. 12 with the chip connecting portion embodiment of Yoneyama Fig. 8, in order to “reduce impedance in a high-frequency switching operation” (col. 6, lines 40-45).
Yoneyama does not explicitly teach that the plurality of concave portions is periodically disposed in at least two directions of the edge surface.
In a similar field of endeavor, Nakajima teaches that the plurality of concave portions (53; see Figs. 4A-4B; col. 11, lines 50-55) is periodically disposed in at least two directions (horizontal and vertical) of the edge surface,
because it “improves the adhesion property between the leads and the sealing resin and sealing property of the molding resin” (col. 3, lines 50-55).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama with the concave portions of Nakajima, because it improves the adhesion property between the leads and the sealing resin and sealing property of the molding resin.
Yoneyama in view of Nakajima does not explicitly teach that a developed interfacial area ratio of the rough surface region of the wiring portion is 0.2 or more, wherein the developed interfacial area ratio of the rough surface region and the developed interfacial ratio of the circuit pattern is an increase ratio of area compared to a completely flat area.
In a similar field of endeavor, Nakatsugawa teaches that the rough surface region has a developed interfacial area ratio of 0.2 or more ([0020], “0.3 or more and 0.8 or less,” which falls within the range of 0.2 or more), wherein the developed interfacial area ratio is an increase ratio of area compared to a completely flat area ([0020]), “in order to obtain sufficient resin adhesion to the roughened surface portion” ([0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima with the developed interfacial area ratio of the rough surface region of Nakatsugawa, in order to obtain sufficient resin adhesion to the rough surface region ([0021]).
Regarding claim 44, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 71, as set forth below. However, Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that the developed interfacial area ratio of the circuit pattern is 0.08 or less. Nonetheless, the skilled artisan would know too that the surface roughness of the circuit pattern would impact resin releasability (Nakatsugawa, [0011]).
The specific claimed surface roughness, absent any criticality, is only considered to be the “optimum” surface roughness disclosed by Yoneyama in view of Nakajima and Nakatsugawa that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired resin releasability, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the developed interfacial area ratio of the circuit pattern being 0.08 or less is used, as already suggested by Yoneyama in view of Nakajima and Nakatsugawa.
Since the applicant has not established the criticality (see next paragraph) of the surface roughness stated and since these levels of surface roughness are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Nakatsugawa.
Please note that the specification contains no disclosure of either the critical nature of the claimed surface roughness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 45, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 42. Nakajima further teaches that an arithmetic average height of the rough surface region is 10 µm or less (col. 16, lines 25-35).
Regarding claim 46, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 42. Nakajima further teaches, in Fig. 4B, that a maximum average height of the rough surface region is 100 µm or less (col. 16, lines 25-35).
However, Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that a maximum height of the rough surface region is 100 µm or less. Nonetheless, the skilled artisan would know too that a height of the rough surface region would impact “adhesion strength to a molding resin” (Nakajima, Abstract).
The specific claimed height, absent any criticality, is only considered to be the “optimum” height disclosed by Yoneyama in view of Nakajima and Nakatsugawa that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired adhesion strength, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a maximum height of the rough surface region is 100 µm or less is used, as already suggested by Yoneyama in view of Nakajima and Nakatsugawa.
Since the applicant has not established the criticality (see next paragraph) of the heights stated and since these heights are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Nakatsugawa.
Please note that the specification contains no disclosure of either the critical nature of the claimed heights or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 47, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 42. Yoneyama further teaches, in Fig. 12, that the wiring portion (33) is a lead frame having a plate-shaped portion (see Fig. 10, left and right portions);
the wiring portion (33) includes a chip connecting portion (shown in Fig. 8) connected to the semiconductor chip (16) (see Fig. 12),
the wiring portion (33) includes a circuit pattern connecting portion (right portion) connected to the circuit pattern (13a2); and
the wiring portion (33) includes a bridge (middle) portion that connects the chip connecting portion and the circuit pattern connecting portion (see Fig. 12).
Nakajima further teaches, in Fig. 5B, that the rough surface region (54) is provided in the chip connecting portion (left portion of wiring portion 51 that is connected to semiconductor chip 30 that is labelled in Fig. 3A; col. 10, lines 10-15).
Regarding claim 49, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 47. However, Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that the developed interfacial area ratio of the circuit pattern connecting portion is smaller than the developed interfacial area ratio of the rough surface region of the chip connecting portion. Nonetheless, the skilled artisan would know too that surface roughness would impact “adhesion strength to a molding resin” (Nakajima, Abstract).
The specific claimed surface roughness, absent any criticality, is only considered to be the “optimum” surface roughness disclosed by Yoneyama in view of Nakajima and Nakatsugawa that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired resin adhesion strength, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the developed interfacial area ratio of the circuit pattern connecting portion being smaller than the developed interfacial area ratio of the rough surface region of the chip connecting portion is used, as already suggested by Yoneyama in view of Nakajima and Nakatsugawa.
Since the applicant has not established the criticality (see next paragraph) of the surface roughness stated and since these surface roughness are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Nakatsugawa.
Please note that the specification contains no disclosure of either the critical nature of the claimed surface roughness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 52, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 47. Nakajima further teaches a coating layer (8, see Fig. 3B) for covering at least a part of a surface of the lead frame (51) and formed of a resin (col. 2, lines 60-65).
Regarding claim 53, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 52. Nakajima further teaches, in Fig. 3B, that the chip connecting portion (left portion of wiring portion 51) has the edge surface (left surface) farthest from the bridge portion (middle portion of wiring portion 51); and the coating layer (8) is provided in the edge surface (left surface of wiring portion 51).
Regarding claim 55, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 52. Nakajima further teaches that a surface of the coating layer (8, Fig. 3B) has irregularities corresponding to irregularities of the rough surface region (54, Fig. 5B, see how the surface of coating layer 8 that is in contact with rough surface region 54 would have irregularities corresponding to irregularities of the rough surface region 54).
Regarding claim 56, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 52. Nakajima further teaches that a surface of the coating layer (8, Fig. 3B, top surface) is flatter than the rough surface region (54, Fig. 5B).
Regarding claim 57, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 42. Yoneyama further teaches, in Fig. 11, that the resin package (24 and 25) includes a resin case (25) surrounding the insulating circuit board (12, 13b, and 14) and a resin (24) filled in the resin case (col. 3, lines 55-60).
Regarding claim 71, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 42. However, Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that the developed interfacial area ratio of the rough surface region is larger than the developed interfacial area ratio of the circuit pattern. Nonetheless, the skilled artisan would know too that the surface roughness of the rough surface region would impact resin adhesion to the rough surface region (Nakatsugawa, [0021]).
The specific claimed surface roughness, absent any criticality, is only considered to be the “optimum” surface roughness disclosed by Yoneyama in view of Nakajima and Nakatsugawa that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired resin adhesion, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the developed interfacial area ratio of the rough surface region being larger than the developed interfacial area ratio of the circuit pattern is used, as already suggested by Yoneyama in view of Nakajima and Nakatsugawa.
Since the applicant has not established the criticality (see next paragraph) of the surface roughness stated and since these levels of surface roughness are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Yoneyama in view of Nakajima and Nakatsugawa.
Please note that the specification contains no disclosure of either the critical nature of the claimed surface roughness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 48 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama in view of Nakajima et al. (US 6849930), and Nakatsugawa et al. (JP 2019207905 A, citations made hereinafter to the English Machine Translation attached to the Office Action mailed on 1/16/2026), and further in view of Ooshima et al. (US 10373889).
Regarding claim 48, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 47. Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that an area of the chip connecting portion is larger than an area of the circuit pattern connecting portion.
In a similar field of endeavor, Ooshima teaches, in Fig. 6, that an area of the chip connecting portion (192; col. 10, lines 20-30) is larger than an area of the circuit pattern connecting portion (194; col. 10, lines 35-45), in order “to restrict the peeling of the sealing resin body” (col. 19, lines 35-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima and Nakatsugawa with the areas of Ooshima, in order to restrict the peeling of the sealing resin body.
Claims 50-51 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama in view of Nakajima et al. (US 6849930), and Nakatsugawa et al. (JP 2019207905 A, citations made hereinafter to the English Machine Translation attached to the Office Action mailed on 1/16/2026), and further in view of Miura (JP 2009004435 A, citations made hereinafter to the English machine translation filed by Applicant on April 6, 2025), cited by Applicant in the Information Disclosure Statement filed on April 6, 2025.
Regarding claim 50, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 47. Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that the bridge portion has an opening.
In a similar field of endeavor, Miura teaches, in Fig. 8, that the bridge portion (102) has an opening (106) ([0050]-[0052]), in order to “provide a semiconductor device capable of reducing resistance to a high frequency current in a strap connecting a semiconductor chip and a lead” ([0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima and Nakatsugawa with the bridge portion of Miura, in order to provide a semiconductor device capable of reducing resistance to a high frequency current in a strap connecting a semiconductor chip and a lead.
Regarding claim 51, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 47. Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that a lower surface of the chip connecting portion or a lower surface of the circuit pattern connecting portion has a protrusion protruding toward the insulating circuit board.
In a similar field of endeavor, Miura teaches, in Fig. 9(a), that a lower surface (bottom surface) of the chip connecting portion or a lower surface of the circuit pattern connecting portion (110, [0061]) has a protrusion protruding toward the insulating circuit board (see in Fig. 9(a) how the recesses 111 on the lower surface form protrusions protruding toward the circuit board below), in order to “provide a semiconductor device capable of reducing resistance to a high frequency current in a strap connecting a semiconductor chip and a lead” ([0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima and Nakatsugawa with the lower surface of Miura, in order to provide a semiconductor device capable of reducing resistance to a high frequency current in a strap connecting a semiconductor chip and a lead.
Claim 54 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama in view of Nakajima et al. (US 6849930), and Nakatsugawa et al. (JP 2019207905 A, citations made hereinafter to the English Machine Translation attached to the Office Action mailed on 1/16/2026), and further in view of Paulus et al. (US 7868430).
Regarding claim 54, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 52. Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that a film thickness of the coating layer is 1 µm or more and 100 µm or less.
In a similar field of endeavor, Paulus teaches that a film thickness (D) of the coating layer (11) is 1 µm or more and 100 µm or less (col. 3, lines 20-30), in order to “improve reliability, reduce size, and to decrease manufacturing costs” (col. 1, lines 10-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima and Nakatsugawa with the coating layer thickness of Paulus, in order to improve reliability, reduce size, and to decrease manufacturing costs.
Claim 58 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneyama in view of Nakajima et al. (US 6849930), and Nakatsugawa et al. (JP 2019207905 A, citations made hereinafter to the English Machine Translation attached to the Office Action mailed on 1/16/2026), and further in view of Kamiyama et al. (US 9966327).
Regarding claim 58, Yoneyama in view of Nakajima and Nakatsugawa teaches the limitations of claim 47. Yoneyama further teaches, in Fig. 12, that the chip connecting portion has a lower surface (bottommost surface) facing the semiconductor chip (16); and that the lower surface of the chip connecting portion has a first (left) side farthest from the bridge portion (middle portion of 33).
Yoneyama in view of Nakajima and Nakatsugawa does not explicitly teach that the lower surface of the chip connecting portion is provided with a step or an inclination along the first side over a length of half or more of the first side.
In a similar field of endeavor, Kamiyama teaches, in Figs. 3D and 4B, that the lower surface of the chip connecting portion (11) is provided with a step or an inclination (6) along the first side over a length of half or more of the first side (see Fig. 3D, entire length of right side) (col. 6, lines 20-30) “in order to reduce the degree of package warping due to a temperature change” (col. 1, lines 50-60).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor module of Yoneyama in view of Nakajima and Nakatsugawa with the lower surface of Kamiyama, in order to reduce the degree of package warping due to a temperature change.
Conclusion
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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