DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed February 202, 2026 has been entered. Claims 1-5, 7-18, and 20 remain pending in the application.
Applicant’s amendments to the Drawings have overcome each and every objection previously set forth for claims 5 and 6 in the Non-Final Office Action mailed February 05, 2025.
Examiner maintains drawing objection previously set forth in the Non-Final Office Action mailed February 05, 2025 for claims 10 and 11.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the area of the boundary region as compared with the area of the transistor region in a top view as claimed in claims 10 and 11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 5 is objected to because of the following informalities:
The amendment in Claim 5, line 5 uses “the at least one.” However, this causes the structure of the limitation to contain itself possibly causing confusion. Examiner suggests changing the amendment to “at least one” to such that the limitation reads “the at least one emitter region comprises at least one first emitter region in the boundary region and at least one second emitter region in the transistor region.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 recites the limitation "according to claim 6" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 depends on claim 6. However, claim 6 was canceled. For purposes of Examination, Examiner will interpret claim 9 to be dependent on claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 16-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tatsuya (WO 2019098270 A1).
Regarding claim 1, Tatsuya teaches a semiconductor device (Fig 1a semiconductor device
100, [0013] of translation) comprising: a semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation) including a transistor portion (Fig 1b transistor section 70, [0013] of translation) and a diode portion (Fig 1b diode portion 81, [0018] of translation), wherein the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation) includes a drift region (Fig 1b drift region 18, [0056] of translation) of a first conductivity type (N-type, [0018] of translation) provided inside, wherein the transistor portion (Fig 1b transistor section 70, [0013] of translation) includes a transistor region (Fig 1b transistor section 70, [0013] of translation) separated from the diode portion (Fig 1b diode portion 81, [0018] of translation) in a top view (Fig 1a is a top view, [0018] of translation) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation), wherein the semiconductor device (Fig 1 semiconductor device 100, [0013] of translation) includes a boundary region (Fig 1a boundary portion 90, [0018] of translation) located between the transistor region (Fig 1b transistor section 70, [0013] of translation) and the diode portion (Fig 1b diode portion 81, [0018] of translation) in a top view of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation), wherein the semiconductor device (Fig 1 semiconductor device 100, [0013] of translation) includes a lifetime control region (Fig 1b lifetime control region 72, [0046] of translation) on a front surface side (Fig 1b top side of semiconductor substrate 10) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation) in the drift region (Fig 1b drift region 18, [0056] of translation), and wherein the boundary region (Fig 1a boundary portion 90, [0018] of translation) has a current suppression structure (the boundary section 90 comprising trenches 30/40 and an upper lifetime control region 72 suppresses leakage current, [0078] of translation), wherein the boundary region (Fig 1a boundary portion 90, [0018] of translation) includes a plurality of mesa portions (Fig 1a mesa is a portion of the semiconductor substrate sandwiched between two adjacent trenches, [0030] of translation; mesa portions in boundary portion 90), wherein the boundary region (Fig 1a boundary portion 90, [0018] of translation) includes a plurality of dummy trench portions (Fig 1b dummy trench portion 30, [0020] of translation) provided from the front surface side (Fig 1b top side of semiconductor substrate 10) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation) to the drift region (Fig 1b drift region 18, [0056] of translation), wherein at least one of the plurality of dummy trench portions (Fig 1b dummy trench portion 30, [0020] of translation) is sandwiched between (Fig 1b) two of the plurality of mesa portions (Fig 1b mesa portions in boundary portion 90) that are adjacent to each other (Fig 1b), where each of the plurality of the mesa portions (Fig 1b mesa portions in boundary portion 90) include at least one first emitter region (Fig 1a emitter region 12, [0034] of translation) of a first conductivity type (n-type, [0034] of translation), a base region (Fig 1a base region 14, [0032] of translation) of a second conductivity type (p-type, [0032] of translation), and at least one first extraction region (Fig 1a contact region 15, [0035] of translation) of the second conductivity type (p-type, [0035] of translation) in a top view (Fig 1a) that are each formed along an extending direction (Fig 1a x-direction) of at least one of the plurality of dummy trench portions (Fig 1b dummy trench portion 30, [0020] of translation).
Regarding claim 2, Tatsuya teaches the transistor portion (Fig 1b transistor section 70, [0013] of translation) further includes at least one gate trench portion (Fig 1a gate trench section 40, [0044] of translation) provided from the front surface side (Fig 1b top side of semiconductor substrate 10) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation) to the drift region (Fig 1b drift region 18, [0056] of translation), and in the boundary region (Fig 1a boundary portion 90, [0018] of translation), the current suppression structure (the boundary section 90 comprising trenches 30/40 and an upper lifetime control region 72 suppresses leakage current, [0078] of translation) comprises a dummy ratio that is a ratio of a number of the dummy trench portions (Fig 1b dummy trench portion 30, [0020] of translation) to a number of the gate trench portions (Fig 1a gate trench section 40, [0044] of translation) is greater than 1 (ratio of dummy trench portions to gate trench portions in boundary region is 3:1; Examiner considers the gate trench 40 at the left side of the boundary region to be a part of the boundary portion and transistor section; Further, Examiner considers the dummy trench 30 at the right side of the boundary region to be a part of the boundary portion and diode section).
Regarding claim 3, Tatsuya teaches the dummy ratio (3:1 from claim 2) in the boundary region (Fig 1a boundary portion 90, [0018] of translation) is higher (3:1 is higher than 3:2) than the dummy ratio (ratio of dummy trench portions to gate trench portions in transistor region is 6:4, reduced to 3:2; Examiner considers the gate trench 40 at the right side of the transistor region to be a part of the boundary portion and transistor section; Further, Examiner obtained ratio for visible portions only) in the transistor region (Fig 1b transistor section 70, [0013] of translation).
Examiner notes that Tatsuya teaches the numbers and arrangement of gate trenches and dummy trenches can be set at a predetermined number ([0026]), thus allowing the ratio to be further altered if needed.
Regarding claim 4, Tatsuya teaches the dummy ratio (3:1 from claim 2; 3:1 is two times more than 3:2) in the boundary region (Fig 1a boundary portion 90, [0018] of translation) is one time or more and nine times or less the dummy ratio in the transistor region (Fig 1b transistor section 70, [0013] of translation).
Regarding claim 5, Tatsuya teaches the transistor portion (Fig 1b transistor section 70, [0013] of translation) further includes at least one emitter region (Fig 1a emitter region 12, [0034] of translation) of a first conductivity type (n-type, [0034] of translation) on the front surface side (Fig 1b top side of semiconductor substrate 10) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation), the at least one emitter region (Fig 1a emitter region 12, [0034] of translation) comprises the at least one first emitter region (Fig 1a emitter region 12, [0034] of translation) in the boundary region (Fig 1a boundary portion 90, [0018] of translation) and at least one second emitter region (Fig 1a emitter region 12, [0034] of translation) in the transistor region (Fig 1b transistor section 70, [0013] of translation), the transistor portion (Fig 1b transistor section 70, [0013] of translation) further includes at least one extraction region (Fig 1a contact region 15, [0035] of translation) of the second conductivity type (p-type, [0035] of translation) on the front surface side (Fig 1b top side of semiconductor substrate 10) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation), the at least one extraction region (Fig 1a contact region 15, [0035] of translation) comprises the at least one first extraction region (Fig 1a contact region 15, [0035] of translation) in the boundary region (Fig 1a boundary portion 90, [0018] of translation) and at least one second extraction region (Fig 1a contact region 15, [0035] of translation) in the transistor region (Fig 1b transistor section 70, [0013] of translation).
Regarding claim 7, Tatsuya teaches a width (Fig 3a width of {Wa-(Wt+Wc)} is the same as the
width of the boundary portion 90; using dimensions in [0104] of translation for Wa, Wt, and Wc; width is 150 µm-20 µm-20 µm=110 µm) of the boundary region (Fig 1 boundary portion 90, [0018] of translation) in an arrangement direction (Fig 3a y-direction) of the transistor portion (Fig 1b transistor section 70, [0013] of translation) and the diode portion (Fig 1b diode portion 81, [0018] of translation) is 50 µm or more and 150 µm or less in a top view (Fig 1a) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation).
Examiner notes Tatsuya teaches the widths of Wc may be between 0.1 and 0.3 and times the
width Wa and the width Wt may be between 0.1 and 0.3 times the width Wa. This would make the width of the boundary region 0.8 times Wa. If Wa were 150 µm then the width of the boundary region would be calculated to be 120 µm.
Regarding claim 8, Tatsuya teaches a width (Fig 3a width of {Wa-(Wt+Wc)} is the same as the
width of the boundary portion 90; using dimensions in [0104] of translation for Wa, Wt, and Wc; width is 150 µm-20 µm-20 µm=110 µm)) of the boundary region (Fig 1 boundary portion 90, [0018] of translation) in an arrangement direction (Fig 3a y-direction) of the transistor portion (Fig 1b transistor section 70, [0013] of translation) and the diode portion (Fig 1b diode portion 81, [0018] of translation) is 50 µm or more and 150 µm or less in a top view (Fig 1a) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation).
Examiner notes Tatsuya teaches the widths of Wc may be between 0.1 and 0.3 and times the
width Wa and the width Wt may be between 0.1 and 0.3 times the width Wa. This would make the width of the boundary region 0.8 times Wa. If Wa were 150 µm then the width of the boundary region would be calculated to be 120 µm.
Regarding claim 9, Tatsuya as modified in claim 6 teaches a width (Fig 1 space taken by
boundary region 75) of the boundary region (Fig 1 boundary portion 90, [0018] of translation) is 100 µm or more (from claim 7; 110 µm).
Regarding claim 16, Tatsuya teaches the first extraction region (Fig 1a contact region 15, [0035] of translation) in the boundary region (Fig 1a boundary portion 90, [0018] of translation) of one of the plurality of mesa portions (Fig 1b mesa portions in boundary portion 90) is adjacent to (Fig 1a) the diode portion (Fig 1b diode portion 81, [0018] of translation) in a top view (Fig 1a).
Regarding claim 17, Tatsuya teaches the first extraction region (Fig 1a contact region 15, [0035] of translation) in the boundary region (Fig 1a boundary portion 90, [0018] of translation) of one of the plurality of mesa portions (Fig 1b mesa portions in boundary portion 90) is adjacent to (Fig 1a) the diode portion (Fig 1b diode portion 81, [0018] of translation) in a top view (Fig 1a).
Regarding claim 18, Tatsuya teaches in one of the plurality of mesa portions (Fig 1b mesa portions in boundary portion 90) the at least one first emitter region (Fig 1a emitter region 12, [0034] of translation) and the at least one first extraction region (Fig 1a contact region 15, [0035] of translation) are alternately disposed (Fig 1a) along the extending direction (Fig 1a x-direction) of the at least one of the plurality of dummy trench portion (Fig 1a dummy trench portion 30, [0020] of translation) in a top view (Fig 1a).
Regarding claim 20, Tatsuya teaches a gate trench portion (Fig 1a gate trench section 40, [0044] of translation) of the boundary region (Fig 1 boundary portion 90, [0018] of translation) includes: a first gate trench portion (Fig 1a gate trench section 40, [0044] of translation in storage region 16, [0045] of translation) in contact (Fig 1a) with the at least one first emitter region (Fig 1 emitter region 12, [0057]), and a second gate trench portion (Fig 1a gate trench section 40, [0044] of translation in well region 11, [0028] of translation) not in contact (Fig 1a) with the at least one emitter region (Fig 1 emitter region 12, [0057]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tatsuya (WO 2019098270 A1), in view of Tanabe et. al. (US 20180151557 A1), hereinafter Tanabe.
Regarding claim 10, Tatsuya and Tanabe fail to teach an area of the boundary region is three
times or more an area of the transistor region in a top view of the semiconductor substrate.
Regarding an area of the boundary region is three times or more an area of the transistor region
in a top view of the semiconductor substrate. Tanabe teaches an area occupied by the boundary region is dependent on the shape of the diode region and the thickness of the drift region ([0047]-[0050]). The area occupied by the boundary region width is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the shape of the diode region and the thickness of the drift region as Tanabe have identified the boundary region width as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at an area of the boundary region is three times or more an area of the transistor region
in a top view of the semiconductor substrate, in order to achieve the desired balance between the shape of the diode region and the thickness of the drift region, as taught by Tanabe. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the area of the boundary region ratio is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific area).
Regarding claim 11, Tatsuya and Tanabe fail to teach an area of the boundary region is three
times or more an area of the transistor region in a top view of the semiconductor substrate.
Regarding an area of the boundary region is three times or more an area of the transistor region
in a top view of the semiconductor substrate. Tanabe teaches an area occupied by the boundary region is dependent on the shape of the diode region and the thickness of the drift region ([0047]-[0050]). The area occupied by the boundary region width is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the shape of the diode region and the thickness of the drift region as Tanabe have identified the boundary region width as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at an area of the boundary region is three times or more an area of the transistor region
in a top view of the semiconductor substrate, in order to achieve the desired balance between the shape of the diode region and the thickness of the drift region, as taught by Tanabe. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the area of the boundary region ratio is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific area).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tatsuya (WO 2019098270 A1), in view of Tawara et. al. (US 20190393312 A1), hereinafter Tawara.
Regarding claim 12, Tatsuya fails to teach the lifetime control region includes a lifetime killer having a doping concentration of 1x1010 cm-3 or more and 1x1013 cm-3 or less.
Regarding the lifetime control region includes a lifetime killer having a doping concentration of
1x1010 cm-3 or more and 1x1013 cm-3 or less. Tawara teaches a lifetime reduced layer ([0046]) with a carrier lifetime killer (Vanadium, [0046]). Tawara further teaches when the carrier lifetime killer concentration is too low then effect of the carrier lifetime killer is reduced and when the concentration is too high then the lifetime reduced layer may invert to become a p-type layer ([0048]). The lifetime killer concentration is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the lifetime killer concentration as Tawara has identified the concentration as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a doping concentration of 1x1010 cm-3 or more and 1x1013 cm-3 or less, in order to achieve the desired balance between effectively reducing the carrier lifetime and the doping the layer to near carrier inversion, as taught by Tawara. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed concentration is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed range).
Regarding claim 13, Tatsuya fails to teach the lifetime control region includes a lifetime killer having a doping concentration of 1x1010 cm-3 or more and 1x1013 cm-3 or less.
Regarding the lifetime control region includes a lifetime killer having a doping concentration of
1x1010 cm-3 or more and 1x1013 cm-3 or less. Tawara teaches a lifetime reduced layer ([0046]) with a carrier lifetime killer (Vanadium, [0046]). Tawara further teaches when the carrier lifetime killer concentration is too low then effect of the carrier lifetime killer is reduced and when the concentration is too high then the lifetime reduced layer may invert to become a p-type layer ([0048]). The lifetime killer concentration is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the lifetime killer concentration as Tawara has identified the concentration as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a doping concentration of 1x1010 cm-3 or more and 1x1013 cm-3 or less, in order to achieve the desired balance between effectively reducing the carrier lifetime and the doping the layer to near carrier inversion, as taught by Tawara. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed concentration is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed range).
Regarding claim 14, Tatsuya teaches a back surface lifetime control region (embodiment of Fig 10 lifetime control region 74, [0189] of translation; Fig 1b for side view example) is further provided over the entire transistor portion (Fig 8 transistor section 70, [0184] of translation) and the entire diode portion (Fig 8 diode portion 81, [0184] of translation) on a back surface side (Fig 1b lower side of semiconductor substrate 10) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation) to the drift region (Fig 1b drift region 18, [0056] of translation).
Regarding claim 15, Tatsuya teaches a back surface lifetime control region (embodiment of Fig 10 lifetime control region 74, [0189] of translation; Fig 1b for side view example) is further provided over the entire transistor portion (Fig 8 transistor section 70, [0184] of translation) and the entire diode portion (Fig 8 diode portion 81, [0184] of translation) on a back surface side (Fig 1b lower side of semiconductor substrate 10) of the semiconductor substrate (Fig 1b semiconductor substrate 10, [0013] of translation) to the drift region (Fig 1b drift region 18, [0056] of translation).
Response to Arguments
Applicant’s arguments, see 35 USC §112 section on page 8, filed February 20, 2026, with respect to amending claim 5 and cancelling claim 6 have been fully considered and are persuasive. The 35 USC §112 rejection of claims 5-6 has been withdrawn.
Applicant’s arguments with respect to claims 1-4, 7-18, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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