Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 30, 2025 has been entered.
This action is non-final, and is in response to the amendments filed on December 30, 2025.
Claims 1-8 are pending and have been considered. Claims 1 is independent claim. Claims 1 has been amended. No claims have been canceled.
Claims 1-8 are rejected under 35 U.S.C. 112(a), for failing to comply with the written description requirement.
Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea, a mental process, without significantly more.
Claim(s) 1, 3 are rejected under 35 U.S.C. 103 as being unpatentable over Brill Boaz WO 2011158239 A1 hereinafter BOA in view of ADIGA, TW 202026631 A, hereinafter ADI in further view of Chun US 20090023293 A1, hereinafter CHU in further view of Grinchuk et al US 20040120578 A1, hereinafter GRI.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brill Boaz WO 2011158239 A1 hereinafter BOA in view of ADIGA, TW 202026631, hereinafter ADI in further view of Chun US 20090023293 A1, hereinafter CHU in further view of Grinchuk et al US 20040120578 A1, hereinafter GRI in further view of Jakatdar et al US 20030163295 A1 hereinafter JAK
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brill Boaz WO 2011158239 A1 hereinafter BOA in view of ADIGA, TW 202026631, hereinafter ADI in further view of Chun US 20090023293 A1, hereinafter CHU in further view of Grinchuk et al US 20040120578 A1, hereinafter GRI in further view of Meng et al CN 111929980 A hereinafter MEN
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brill Boaz WO 2011158239 A1 hereinafter BOA in view of ADIGA, TW 202026631, hereinafter ADI in further view of Chun US 20090023293 A1, hereinafter CHU in further view of Grinchuk et al US 20040120578 A1, hereinafter GRI in further view of Gao et al A High Speed Surface Illuminated Si Photodiode using Microstructured Holes for Absorption Enhancements at 900-1000 nm Wavelength, ACS Photonics 2017, referred as GAO
Response to Amendments and Arguments
In the amendment filed on December 30, 2025, applicant amended independent claim 1 to include new limitations. The amendments have been fully considered.
The arguments filed on December 30, 2025 have been considered but have not been found persuasive.
Regarding the 101 rejection, Applicant makes the argument that Paragraph [0013] of the instant application teaches that "Based on different types of the SEM image, different parameters can be used to generate the side edge model. ... etching parameters can be inputted into
the polynomial data base to generate the side edge model. The etching parameters include etching machine type, a material of the material layer, etchant type, operational power of an etching process, operational pressure of an etching process or temperature of a wafer chuck".
Further, Applicant submits that “It can be inferred from paragraph [0013] that parameters such as
etching machine type, operational power, pressure, and temperature are direct control signals used by an etching machine for "forming a pattern". A similar argument regarding Paragraph [0009] Applicant concludes that based on "The SEM image10 10ay be ... an after etching inspection (AEI) image... The SEM image 10 may be a top view of a contact hole, a top view of a rectangular trench...”
It can be inferred from paragraph [0009] that an AEI image is a result of the "forming a pattern" action performed by an etching machine.
The Examiner notes that the Application does not recite the limitation. Applicant assumes inherency driven by probable use or logical consequence. Unfortunately, as per MPEP 2163(b) In re Robertson, 169 F.D 743, 745, 49 USPQ2d 1949, 1950-51 (Fed. Cir. 1999) ("To establish inherency, the extrinsic evidence ‘must make clear that the missing descriptive matter is necessarily present in the thing described in the reference, and that it would be so recognized by persons of ordinary skill. Inherency, however, may not be established by probabilities or possibilities. The mere fact that a certain thing may result from a given set of circumstances is not sufficient.’" While MPEP 2163 permits inherent support for written description, such inherency requires that the claimed feature be necessarily present in the originally disclosed invention, not merely a logical or intended use of the disclosed output. The specification of the instant application does not establish that forming a pattern on anther substrate by an etching machine based on the process judgment derived from the 3D feature profile is inevitable.
Moreover, even if considered, the etching step merely applies the result of the model/simulation in a generic manufacturing context and does not recite any particular machine, fabrication parameters, or technological improvement. The step therefore constitutes an extra solution activity and does not integrate the abstract idea into a practical application. The limitation is also WURC as shown further below.
Accordingly, the rejections of the independent claim, and of the dependent claims are maintained.
The analysis in 101 and 103 context is provided only for the purpose of compact prosecution.
The arguments filed on December 30, 2025 have been considered. In view of the amendments a new ground of rejection has been established.
The Examiner confirms that the § 112(b) issues have been resolved with the previous Amendment dated 10/15/2025, and the rejection has been withdrawn.
Claim Rejections - 35 USC § 112(a)
Written Description (New Matter)
The following is a quotation of 35 U.S.C. 112(a):
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of the relevant portion of 35 U.S.C. §132(a):
No amendment shall introduce new matter into the disclosure of the invention.
Claims 1-8 are rejected under 35 U.S.C. 112(a), for failing to comply with the written description requirement. MPEP 2163.06 stipulates – If new matter is added to the claims, the examiner should reject the claims under 35 U.S.C. 112(a) – written description requirement. In re Rasmussen, 650 F.2d 1212, 211 USPQ 323 (CCPA 1981).
Claim 1 have been amended by Applicant to include the limitation “forming a pattern on anther substrate by an etching machine based on the process judgment derived from the 3D feature profile “ The limitation has no support in the specification, drawings or initial set of claims.
As per claim 1 Applicant has not pointed out where the amended claim is supported, nor does there appear to be a written description of the claim limitation “forming a pattern on anther substrate by an etching machine based on the process judgment derived from the 3D feature profile” in the application as filed, the drawings or the initial set of claims.
The Examiner notes that the claim elements are not in the Specification. The specification does not explicitly or inherently (in the legal sense) disclose the limitation and its use as implied by the Applicant is not inevitable. Accordingly the limitation lacks adequate written description support under 35 USC 112(a).
The dependent claims inherit the deficiency and are thus also properly rejected.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea, a mental process, without significantly more.
Step 1
Claims 1-8 is directed towards the statutory category of a process.
Step 2A – Prong 1
The claims recite an abstract idea, a mental process. Claim 1 recites the following:
identifying a position of the inner edge and a position of the outer edge of the feature pattern; defining a side edge region based on the position of the inner edge and the position of the outer edge; automatically generating a side edge model to simulate a side edge profile of the feature pattern in the side edge region; automatically outputting a 3D feature profile based on the position of the inner edge, the position of the outer edge, the thickness of the material layer and the side edge profile; and using the 3D feature profile for a process judgment of the semiconductor device.
A human can visually/mentally identify position of edges, define a region between edges and with pen and paper calculate a side edge model; outputting is here interpreted as the process of obtaining the 3D profile, as a necessary step.
Under the broadest reasonable interpretation, these limitations are process steps that cover mental processes including an observation, evaluation, judgment or opinion that could be performed in the human mind or with the aid of physical aids but for the recitation of a generic computer component. If a claim, under its broadest reasonable interpretation, covers a mental process but for the recitation of generic computer components, then it falls within the "Mental Process" grouping of abstract ideas. A person would readily be able to perform this process either mentally or with the assistance of physical aids. See MPEP § 2106.04(a)(2).
To clarify, see the USPTO 101 training examples, available at https://www.uspto.gov/patents/laws/examination-policy/subject-matter-eligibility. In particular, with respect to the physical aids, see example # 45, analysis of claim 1 under step 2A prong 1, including: “Note that even if most humans would use a physical aid (e.g., pen and paper, a slide rule, or a calculator) to help them complete the recited calculation, the use of such physical aid does not negate the mental nature of this limitation.”; also see example # 49, analysis of claim 1, under step 2A prong 1: “Moreover, the recited mathematical calculation is simple enough that it can be practically performed in the human mind. Even if most humans would use a physical aid, like a pen and paper or a calculator, to make such calculations, the use of a physical aid would not negate the mental nature of this limitation.”
Regarding the claim element “automatically”, it refers on using a computer. The courts do not distinguish between claims that recite mental processes performed by humans and claims that recite mental processes performed on a computer. As the Federal Circuit has explained, "[c]ourts have examined claims that required the use of a computer and still found that the underlying, patent-ineligible invention could be performed via pen and paper or in a person’s mind." Versata Dev. Group v. SAP Am., Inc., 793 F.3d 1306, 1335, 115 USPQ2d 1681, 1702 (Fed. Cir. 2015). See also Intellectual Ventures I LLC v. Symantec Corp., 838 F.3d 1307, 1318, 120 USPQ2d 1353, 1360 (Fed. Cir. 2016) (MPEP § 2106.04(a)(2), subsection III).
As such, the claims recite a mental process, which is an abstract idea.
Step 2A, prong 2
The claimed invention does not recite any additional elements that integrate the judicial exception into a practical application. Refer to MPEP §2106.04(d).
The following limitations are mere data gathering, MPEP §2106.05(d): providing a semiconductor device disposed in a substrate; providing a scanning electron microscope (SEMI image, wherein the SEM image is a feature pattern within a material layer, the feature pattern comprises an inner edge and an outer edge, and the outer edge surrounds the inner edge, and wherein the feature pattern is an SEM image of the semiconductor device and the material layer is an SEM image of the substrate; wherein the thickness of the material layer is obtained by measuring
The following limitation forming a pattern on anther substrate by an etching machine based on the process judgment derived from the 3D feature profile
Is analyzed solely from the perspective of a compact prosecution, since the specification does not, explicitly or inherently recite the limitation. As per MPEP 2163(b) In re Robertson, 169 F.D 743, 745, 49 USPQ2d 1949, 1950-51 (Fed. Cir. 1999) ("To establish inherency, the extrinsic evidence ‘must make clear that the missing descriptive matter is necessarily present in the thing described in the reference, and that it would be so recognized by persons of ordinary skill. Inherency, however, may not be established by probabilities or possibilities. The mere fact that a certain thing may result from a given set of circumstances is not sufficient.’" While MPEP 2163 permits inherent support for written description, such inherency requires that the claimed feature be necessarily present in the originally disclosed invention, not merely a logical or intended use of the disclosed output. The specification of the instant application does not establish that forming a pattern on anther substrate by an etching machine based on the process judgment derived from the 3D feature profile is inevitable.
Even if considered, the etching step merely applies the result of the model/simulation in a generic manufacturing context and does not recite any particular machine, fabrication parameters, or technological improvement. The step therefore constitutes an insignificant extra (post) solution activity and does not integrate the abstract idea into a practical application. It does not provide more than a link to a field of use.
Re “automatically” – mere instructions to do it on a computer. See 2106.05(f): ““Similarly, "claiming the improved speed or efficiency inherent with applying the abstract idea on a computer" does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015)… iii. A process for monitoring audit log data that is executed on a general-purpose computer where the increased speed in the process comes solely from the capabilities of the general-purpose computer, FairWarning IP, LLC v. Iatric Sys., 839 F.3d 1089, 1095, 120 USPQ2d 1293, 1296 (Fed. Cir. 2016);”
A claim that integrates a judicial exception into a practical application will apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the judicial exception. See MPEP § 2106.04(d).
E.g. MPEP § 2106(I): “Mayo, 566 U.S. at 80, 84, 101 USPQ2dat 1969, 1971 (noting that the Court in Diamond v. Diehr found “the overall process patent eligible because of the way the additional steps of the process integrated the equation into the process as a whole,”” – and see MPEP § 2106.05(e).
The claimed invention does not recite any additional elements that integrate the judicial exception into a practical application. Refer to MPEP §2106.04(d).
Step 2B
The claimed invention does not recite any additional elements/limitations that amount to significantly more.
The following limitations are mere data gathering, MPEP §2106.05(d): providing a semiconductor device disposed in a substrate; providing a scanning electron microscope (SEMI image, wherein the SEM image is a feature pattern within a material layer, the feature pattern comprises an inner edge and an outer edge, and the outer edge surrounds the inner edge, and wherein the feature pattern is an SEM image of the semiconductor device and the material layer is an SEM image of the substrate;
Obtaining SEM images is WURC. See Wikipedia https://en.wikipedia.org/wiki/Scanning_electron_microscope
The limitation “forming a pattern …by etching machine” is WURC. See Wikipedia https://en.wikipedia.org/wiki/Etching forming a patterns is the very definition and purpose of these machines in semiconductors.
The claimed invention is directed towards a judicial exception (abstract idea, mental process) without significantly more.
Regarding the dependent claims
Claim 2 is merely further limiting the mental process specifying what data is used.
Claim 3 is merely further limiting the mental process specifying what data is used.
Claim 4 is mere data gathering: SEM ADI and SEM AEI are WURC.
For both ADI and AEI see SEM ADI on device overlay: the advantages and outcome https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12496/124960K/SEM-ADI-on-device-overlay-the-advantages-and-outcome/10.1117/12.2657672.full?SSO=1
Also see SEM Image Transformation Between Litho Domain and Etch Domain,
https://ieeexplore.ieee.org/document/9461458
Claim 5 – rejected under a similar rationale as claim 1, adding an additional step to the abstract idea of claim 1.
Claim 6 is merely further limiting the mental process itself of the mental visualization.
Claim 7 is merely further limiting the mental process itself of the mental visualization.
Claim 8 is merely further limiting the mental process itself of the mental visualization.
The claimed invention is directed towards an abstract idea without significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 are rejected under 35 U.S.C. 103 as being unpatentable over Brill Boaz WO 2011158239 A1 hereinafter BOA in view of ADIGA, TW 202026631, hereinafter ADI in further view of Chun US 20090023293 A1, hereinafter CHU in further view of Grinchuk et al US 20040120578 A1, hereinafter GRI.
Regarding claim 1:
BOA teaches a method of simulating a three dimensional (3D) feature profile of a semiconductor device disposed in a substrate , comprising {[p.1 line 6 Semiconductor structures, such as integrated circuits, become more complicated in the dimensions and shapes of pattern features. [p7 ln11] Fig. 2A exemplifies a system of the present invention for creation of an optical model for interpretation of optical measurements, e.g. OCD, on patterned structures based on image data provided by an imaging tool (metrology tool), for example SEM; Fig. 2B exemplifies a method of the present invention for optical model creation based on identification of the unit cell from an image data obtained by a scanning tool, such as SEM; [p. 17 top] For example, it allows for increasing the overall sampling across a given wafer, as well as allows for sampling different wafers in a lot, and for measuring both inside the die, on a device,}. In BRI the simulation of the feature profile is interpreted as optical model creator – the focus being the geometry of the 3D profile, regardless the intended use.
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BOA further teaches
automatically outputting a 3D feature profile based on the position of the inner edge, the position of the outer edge, a thickness of the material layer and the side edge profile. { [p8 ln 22] the unit cell shown in the figure would practically be characterized by additional parameters, such as side wall angle (SWA), the line width profile, height, etc. ; ;[p9 ln 17] The final model creator receives the contour-data and analyzes it to determine and apply a suitable morphological function and thereby create an appropriate physical model. [p9 ln30] Then, the system operates for processing image data of the unit cell for automatically identifying the contours of all or at least one of the features within the unit cell, a single such contour C being shown in the figure (step 22), and then operates to extract the contour related data/image (step 24). The system utilizes the contour related data C for determining a 3- dimensional shape 26 of the respective feature (step 28).; and the unit cell shown in the figure would practically be characterized by additional parameters, such as side wall angle (SWA), the line width profile, height, etc.; Fig. 2B} The 3D feature profile is the sidewall of between two contours on the
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image 2, one interior to the other, thickness of the layer is parameter H, side edge profile is the side wall angle (SWA).
BOA does not teach, however ADI teaches
wherein the thickness of the material layer is obtained by measuring;{ [paragraph starting with Fig 1] FIG. 1 is an example image sequence 100 showing image processing and the resulting measurement... For process control and defect detection, manufacturers of VNAND devices need to measure the thickness of the material layer forming the operating device.}
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA on generating a 3D model using edge positions extracted from SEM images with the ADI’s thickness measurement. One would have been motivated in order to obtain accurate process characterization. In the instant case, BOA teaches methods to provide a 3D model from 2D SEM image and does disclose processing the 2D image and uses an a derived/calculated value of the thickness. ADI is relied upon to provide a directly measured and more accurate value of the 3rd dimension, the thickness of the material. As both BOA and GRI methods are implemented through well-known computer technologies in the same or similar context, combining their features as outlined above using such well-known computer technologies (i.e., conventional software/hardware configurations), would be reasonable, according to one of ordinary skill in the art. Since their elements would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable.
Accordingly, the claimed subject matter would have been obvious over BOA in view of ADI.
BOA/ADI does not explicitly teach, however CHU teaches:
automatically generating a side edge model to simulate a side edge profile of the feature pattern in the side edge region; and using the 3D feature profile for a process judgment of the semiconductor device. {[0007] … The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate and developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher. The method can also include predicting a sidewall angle using the statistical model. [0033] FIG. 5 shows an exemplary predicted sidewall angle distribution from batch to batch for a period of one year using the statistical model as given in equation 3 and the optimized process parameters according to various embodiments of the present teachings. } using the profile for process improvement interpreted as optimized process parameters.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA/ADI on understanding the a feature’s surface appearance (contour lines) and depth with the teachings from CHU on determining a feature’s depth appearance/profile. The motivation to combine would have been that it would provide the advantage of not only precisely being able to observe (and then more precisely control) the controlled dimensions (CD) on the surface but on the depth as well. “ With the shrinking of the design rules and decreasing process windows (i.e. margins of error in processing), the variation in critical dimension is becoming increasingly important. The critical dimension (CD) refers to dimensions of the smallest geometrical features such as, width of interconnect line, contacts, trenches, etc. which can be formed during semiconductor device/circuit manufacturing using given technology. Currently, gate bottom CD is controlled while sidewall angle is only monitored. As a result of the sidewall angle not being controlled, there is a significant variation in the sidewall angle from run-to-run. Sidewall angle variation in turn impacts parametric I.sub.drives and yield. Thus, there is a need to overcome these and other problems of the prior art and to provide methods of fabricating gates having reduced sidewall angle variation from batch to batch while maintaining current bottom CD control performance.”
Accordingly, the claimed subject matter would have been obvious over BOA in view of ADI in further view of CHU.
BOA/ADI/CHU does not explicitly teach, however GRI teaches
providing a semiconductor device disposed in a substrate; providing a scanning electron microscope (SEM) image, wherein the SEM image is a feature pattern within a material layer, the feature pattern comprises an inner edge and an outer edge, and the outer edge surrounds the inner edge, and wherein the feature pattern is a SEM image of the semiconductor device and the material layer is an SEM image of the substrate; identifying a position of the inner edge and a position of the outer edge of the feature pattern; defining a side edge region based on the position of the inner edge and the position of the outer edge;
{[Abs] . The method includes recognizing edges of the features…[0002] leaving the desired pattern in the substrate.; Fig2, Fig3}; SEM Image Fig. 2 (156); Inner and outer edge surrounding inner edge as the edges in Fig 3 outside zone C and outside zone B respectively (174); side edge region defined based on the position of inner edge and outer edge as the Feature 172 (zone B) in Fig 3.
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forming a pattern on anther substrate by an etching machine based on the process judgment derived from the 3D feature profile {{[0002] … The photolithography process is typically followed by an etch process during which the underlying substrate not covered or masked by the photoresist pattern is etched away, leaving the desired pattern in the substrate.}
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA/ADI/CHU on creating the 3D features with the GRI’s details on collecting the SEM input information. One would have been motivated in order to fully isolate the feature to have the advantage of a fast and simple automatic procedure. In the instant case, BOA teaches methods to provide a 3D model from 2D SEM image and does disclose processing the 2D image but with a technique that benefits from human intervention. GRI is relied upon to illustrate the process of processing 2D image with a simpler autonomous method. GRI also teaches the etching as something typical to do at that step. It would have been obvious to follow, as it is typical, with an etch process (implicitly by an etching machine).
Accordingly, the claimed subject matter of claim 1 would have been obvious over BOA/ADI/CHU/GRI.
Regarding claim 3:
BOA/ADI/CHU/GRI disclose the limitations of claim 1. CHU further discloses
wherein etching parameters are used in generating the side edge model, the etching parameters comprise etching machine type, a material of the material layer, etchant type, operational power of an etching process, operational pressure of an etching process or temperature of a wafer chuck. {[0007] … The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate and developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher. The method can also include predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. }
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from B BOA/ADI/CHU/GRI on determining the feature appearance in 2D (surface) and side profile with further teaching from CHU on determining profile controlling etching parameters, as etching is a key process step in semiconductor fabrication that allows control of features on the vertical/depth. In the instant case, BOA/ADI/CHU/GRI teaches methods to provide a 3D model from 2D SEM image. CHU is relied upon to illustrate the process of processing 2D image with a simpler autonomous method. As both BOA/ADI/CHU/GRI and other embodiment of CHU methods are implemented through well-known computer technologies in the same or similar context, combining their features as outlined above using such well-known computer technologies (i.e., conventional software/hardware configurations), would be reasonable, according to one of ordinary skill in the art. Since their elements would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable.
Accordingly, the claimed subject matter would have been obvious over BOA/ADI/CHU/GRI.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brill Boaz WO 2011158239 A1 hereinafter BOA in view of ADIGA, TW 202026631, hereinafter ADI in further view of Chun US 20090023293 A1, hereinafter CHU in further view of Grinchuk et al US 20040120578 A1, hereinafter GRI in further view of Jakatdar et al US 20030163295 A1 hereinafter JAK
Regarding claim 2:
BOA/ADI/CHU/GRI teach the limitations of the parent claim. BOA/ADI/CHU/GRI do not explicitly teach, however JAK teaches
wherein lithographic parameters are used in generating the side edge model, {[0058] full-profile control 835 of the sidewall angle in a lithographic simulation provided the least variations of sidewall angle; [claim 2] and simulating lithography process using a selected second set of process control parameters.} the lithographic parameters comprise focus offset, exposure energy, photoresist type, development time or baking temperature of photoresist. {[0049] For example, if the type of fabrication process simulation is lithography, the set of process control parameters may include values of the bake time, bake temperature, focus, PEB time, and/or rinse temperature.}
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA/ADI/CHU/GRI on determining the feature appearance in 2D (surface), profile and 3D with the teachings from JAK on determining profile appearance using a model influenced by lithographic parameters as these are in effect the parameters that lead to the creation of the profile and a model with have the advantage of understanding from metrology and control perspective. The reference also teaches “ IC design objectives drive the design activity where masks and IC fabrication plans are produced and transmitted to IC fabrication. IC fabrication produces the wafers that are tested and that undergo finishing operations in IC testing and finishing where flaws or shortcomings of the wafer are noted. Typically, some of the impact of design or process decisions is fed back to the design and fabrication groups at this point. For example, the structure shape is greatly influenced by the process control parameters such as lithography numerical aperture, wavelength, focus exposure, post exposure bake (PEB) temperature, resist thickness, anti-reflective coating thickness, dielectric materials, and fabrication processes used.”
Accordingly, the claimed subject matter would have been obvious over BOA/ADI/CHU/GRI/JAK.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brill Boaz WO 2011158239 A1 hereinafter BOA in view of ADIGA, TW 202026631, hereinafter ADI in further view of Chun US 20090023293 A1, hereinafter CHU in further view of Grinchuk et al US 20040120578 A1, hereinafter GRI in further view of Meng et al CN 111929980 A hereinafter MEN
Regarding claim 4:
BOA/ADI/CHU/GRI do not explicitly teach, however MEN teaches
wherein the SEM image comprises an after develop inspection image or an after etching inspection image. [Description] An ADI (developed photoresist pattern) and an AEI (after etch post etch post etch profile) pattern are stored using a memory device. can store integrated circuit layout data, and the wafer 110 corresponding to the ADI and AEI of the SEM (electronic scanning) pattern; Specifically, using SEM image extraction device to extract the top contour line and the bottom contour line of the SEM image, generating SEM image shape data, taking the SEM image contour line as the reference, calculating the intersection point of the vertical parallel line of the layout edge data, calculating the Eular distance between two points, obtaining the SEM contour line; using pattern and surrounding environment identification device…}
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA/ADI/CHU/GRI on determining the feature appearance in 2D (surface), profile and 3D from SEM image with the teachings from MEN on SEM image being an ADI or AEI Image. This would provide the advantage of checking critical dimensions (CD) and verifying lithography before committing to etching (ADI), and measuring CD, etch profile, sidewall angle and check for etch-defects (AEI). In the instant case, BOA/ADI/CHU/GRI teaches methods to provide a 3D model from 2D SEM image and does disclose processing the 2D image. MEN is relied upon to illustrate how/when the 2D SEM images are obtained. As BOA, GRi, CHU and MEN methods are implemented through well-known computer technologies in the same or similar context, combining their features as outlined above using such well-known computer technologies (i.e., conventional software/hardware configurations), would be reasonable, according to one of ordinary skill in the art. Since their elements would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable.
Accordingly, the claimed subject matter would have been obvious over BOA/ADI/CHU/GRI in further view of MEN.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brill Boaz WO 2011158239 A1 hereinafter BOA in view of ADIGA, TW 202026631, hereinafter ADI in further view of Chun US 20090023293 A1, hereinafter CHU in further view of Grinchuk et al US 20040120578 A1, hereinafter GRI in further view of Gao et al A High Speed Surface Illuminated Si Photodiode using Microstructured Holes for Absorption Enhancements at 900-1000 nm Wavelength, ACS Photonics 2017, referred as GAO
Fig 5 from GAO is reproduced below for convenience, with partial caption that is relevant.
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Regarding claim 5
BOA/ADI/CHU/GRI teach the limitation of the patent claim. They do not explicitly teach, however GAO teaches
wherein in 3D feature profile the inner edge is located away from a top surface of the material layer, and the position of the outer edge is located at the top surface of the material layer.
Gao Fig 5, reproduced as a fragment in the annotated figure below, shows the inner edge away from the top (at bottom), outer edge at the top
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA/ADI/CHU/GRI on determining the feature appearance in 2D (surface), profile and 3D from SEM image with the teachings from GAO. This would provide the advantage of doing 3D for features that are with a lower bottom (trenches, holes). BOA/ADI/CHU/GRI as well as GAO methods are in implemented through well-known computer technologies in the same or similar context, combining their features as outlined above would be reasonable, according to one of ordinary skill in the art. Since their elements would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable.
Accordingly, the claimed subject matter would have been obvious over BOA/ADI/CHU/GRI in further view of GAO.
Regarding claim 6:
BOA/ADI/CHU/GRI teach the limitations of the parent claim. BOA/GRI/CHU do not explicitly teach, however GAO teaches
wherein the 3D feature profile comprises a sidewall and the sidewall connects the inner edge and the outer edge. Gao Fig 5, reproduced as a fragment in the annotated figure below, shows
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA/ADI/CHU/GRI on determining the feature appearance in 2D (surface), profile and 3D from SEM image with the teachings from GAO. This would provide the advantage of doing 3D for features such as a sidewall, a very important parameter in device performance. BOA/ADI/CHU/GRI as well as GAO methods are in implemented through well-known computer technologies in the same or similar context, combining their features as outlined above would be reasonable, according to one of ordinary skill in the art. Since their elements would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable.
Accordingly, the claimed subject matter would have been obvious over BOA/ADI/CHU/GRI in further view of GAO.
Regarding claim 7 (dependent on claim 6):
BOA/GRI/CHU/ADI/GAO teach the limitations of claim 6. GAO further teaches
wherein the sidewall comprises an inclined surface with no curvature, a convex surface curved toward a top surface of the material layer, or a convex surface curved toward a bottom surface of the material layer. Gao Fig 5, reproduced as a fragment in the annotated figure below, shows sidewall as a covex surface curved towards the bottom
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA/GRI/CHU/GAO on determining the feature appearance in 2D (surface), profile and 3D from SEM image with the further teachings from GAO. This would provide the advantage of doing 3D sidewall simulations for the common modalities – conical or convex (holes, trenches) or concave. BOA/ADI/CHU/GRI as well as GAO methods are in implemented through well-known computer technologies in the same or similar context, combining their features as outlined above would be reasonable, according to one of ordinary skill in the art. Since their elements would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable.
Accordingly, the claimed subject matter would have been obvious over BOA/ADI/CHU/GRI in further view of GAO.
Regarding claim 8,
BOA/GRI/CHU/ADI do not explicitly teach, however GAO teaches
wherein the 3D feature profile is embedded within the material layer.
Gao Fig 5, reproduced as a fragment in the annotated figure below, shows feature (sidewall) embedded within the material layer.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings from BOA/GRI/CHU/ADI on determining the feature appearance in 2D (surface), profile and 3D from SEM image with the teachings from GAO. This would provide the advantage of doing 3D for features which are embedded in the material and show the true advantage of 3D from 2D without expensive imaging techniques (TEM or by destructive means. BOA, GRI, CHU as well as GAO methods are in implemented through well-known computer technologies in the same or similar context, combining their features as outlined above would be reasonable, according to one of ordinary skill in the art. Since their elements would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable.
Accordingly, the claimed subject matter would have been obvious over BOA/GRI/CHU/ADI in further view of GAO.
Prior art made of record
The prior art made of record and not relied upon which, however, is considered pertinent to applicant's disclosure:
US 8401273 B2 Apparatus For Evaluating Degradation Of Pattern Features
CN 117452779 A Modelling And Calibrating Method And Device Of Computing Photoetching Non-linear System
CN 110501871 A For Defining Lithography Pattern Side Wall Appearance Of Photoetching Technology Method
Conclusion
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/A.S./Examiner, Art Unit 2188
/RYAN F PITARO/Supervisory Patent Examiner, Art Unit 2188