DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 3, 11 are objected to because of the following informalities:
Claim 3 recites “an XOR gate”, “the XOR gate” and “the first XOR gate”. The claim should be amended such that only “an/the XOR gate” or “a/the first XOR gate” is recited for consistency.
Claim 11, change “multiplexers and;” to “multiplexers; and”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katayama (US 20090228540 A1, hereinafter “Katayama”, included in IDS filed 5/15/2024). The Examiner notes the preamble of claims 1-11, the compute-in-memory-device, are not given patentable weight.
As per claim 1, Katayama teaches a Booth encoder configured to receive at least one input of first bits (Katayama: Fig. 5 elements 410, 420, 430, 440; [0051]);
and a Booth decoder configured to receive at least one weight of second bits and to output a plurality of partial products of the at least one input and the at least one weight (Katayama: Fig. 6 elements 450, 460, 470, 480; [0053]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Katayama in view of Abdallah et al. (US 6035318 A, hereinafter “Abdallah”, included in IDS filed 10/13/2023)
As per claim 2, Katayama further teaches The compute-in-memory device of claim 1, further comprising: an adder configured to add a first partial product of the plurality of partial products and a second partial product of the plurality of partial products before the Booth decoder generates a third partial product of the plurality of the partial products and to generate a plurality of sums of partial products (Katayama: Fig. 5 element 490; [0050]);
However, while Katayama discloses an adder to sum partial products, Katayama does not explicitly disclose the tree comprising at least one carry-lookahead adders. Thus, Katayama does not teach and a carry-lookahead adder configured to add the plurality of sums of partial products and to generate a final sum.
Abdallah teaches and a carry-lookahead adder configured to add the plurality of sums of partial products and to generate a final sum (Abdallah: Fig. 10 element 98; col 10 lines 19-26).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the adder of Katayama with the adder tree of Abdallah. One would have been motivated to combine these references because both references disclose Booth multipliers, and combining prior art elements according to known methods to yield predictable results (adding partial products for Booth multiplication).
Claims 3-8, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Katayama in view of Argade (US 5138570 A, hereinafter “Argade”).
As per claim 3, Katayama further teaches The compute-in-memory device of claim 1.
However, while Katayama discloses numerical outputs of the booth encoders (Table 2), Katayama does not explicitly disclose the equations to formulate the output. Thus, Katayama does not teach wherein the Booth encoder includes: an XOR gate configured to receive a first bit and a second bit of the at least one input; an XNOR gate configured to receive the second bit and a third bit of the at least one input; a first NOR gate configured to receive an output of the XOR gate and an output of the XNOR gate and to output a Booth encoded bit; a second NOR gate configured to receive the output of the first XOR gate and the Booth encoded bit and to output an enable signal configured to control logic gating of the Booth decoder; a third NOR gate configured to receive the enable signal and an inverse of the third bit of the at least one input and to output a select signal.
Argade teaches wherein the Booth encoder includes: an XOR gate configured to receive a first bit and a second bit of the at least one input; an XNOR gate configured to receive the second bit and a third bit of the at least one input; a first NOR gate configured to receive an output of the XOR gate and an output of the XNOR gate and to output a Booth encoded bit; a second NOR gate configured to receive the output of the first XOR gate and the Booth encoded bit and to output an enable signal configured to control logic gating of the Booth decoder; a third NOR gate configured to receive the enable signal and an inverse of the third bit of the at least one input and to output a select signal (Argade: col 4 lines 4-10; Table 1, wherein f.sub.zero corresponds to an enable signal, f.sub.minus corresponds to a select signal, and f.sub.two corresponds to a Booth encoded bit; col 4 equations 6-8, wherein the equations are logically equivalent to the claimed gate structure).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the Booth encoder of Katayama with the encoding scheme of Argade. One would have been motivated to combine these references because both references disclose Booth multipliers, and combining prior art elements according to known methods to yield predictable results (producing the indicated Booth encoder outputs).
As per claim 4 Katayama/Argade further teaches The compute-in-memory device of claim 3, wherein: the second bit is a more significant bit of the at least one input than the first bit; and the third bit is a most significant bit of the at least one input (Katayama: Table 2, wherein the y[2i+1], y[2i], and y[2i-1] correspond to the third bit, second bit, and first bit, respectively).
As per claim 5 Katayama further teaches The compute-in-memory device of claim 1
However, while Katayama discloses generating partial products, Katayama does not explicitly disclose the circuitry to contain multiplexers and adders. Thus, Katayama does not teach wherein the Booth decoder includes: a plurality of multiplexers; and a plurality of adders.
Argade teaches wherein the Booth decoder includes: a plurality of multiplexers (Argade: Fig. 2; col 4 lines 41-49); and a plurality of adders (Argade: Fig. 1 element 108; col 4 lines 25-29).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the partial product generators of Katayama with the ALU of Argade (Fig. 1 element 111). One would have been motivated to combine these references because both references disclose Booth multipliers, and combining prior art elements according to known methods to yield predictable results (producing partial products for the Booth algorithm).
As per claim 6, Katayama/Argade further teaches The compute-in-memory device of claim 5, wherein a first multiplexer of the plurality of multiplexers is configured to receive a select signal from the Booth encoder, a first number of bits of the at least one weight and a first number of inverted bits of the at least one weight, and to selectively output the first number of bits of the at least one weight or the first number of inverted bits of the at least one weight based on the select signal (Argade: Fig. 2 element 201, wherein data paths exists where the weight value is input 0 and inverse weight value is input 1 of element 201, and f.sub.minus is a select signal).
As per claim 7, Katayama/Argade further teaches The compute-in-memory device of claim 5, wherein a first adder of the plurality of adders is configured to: receive an enable signal and Booth encoded bit of the at least one input from the Booth encoder (Argade: Fig. 2 element 202 and Fig. 1 element 108; wherein f.sub.zero and f.sub.minus corresponds to the enable signal and Booth encoded bit, as the enable signal and Booth encoded bit, as claimed, are not correlated to a defined representation, and thus has the scope of any enable signal and Booth-related bit, respectively);
receive a first number of bits of the at least one weight or a first number of inverted bits of the at least one weight from a first multiplexer of the plurality of multiplexers (Argade: Fig. 2 element 201, 203; wherein the output of element 201 corresponds to the output of the first multiplexer);
and execute an operation on the first number of bits of the at least one weight or the first number of inverted bits of the at least one weight based on the enable signal or the Booth encoded bit of the at least one input (Argade: Fig. 1 element 108 and Fig. 2 element 202; col 5 lines 10-14).
As per claim 8, Katayama/Argade further teaches The compute-in-memory device of claim 7, wherein the first adder is configured such that executing an operation on the first number of bits of the at least one weight or the first number of inverted bits of the at least one weight based on the enable signal or the Booth encoded bit of the at least one input includes logic gating the first adder based on the enable signal (Argade: Fig. 2 element 202, wherein element 202 logic gates the received input weight or input inverted weight).
As per claim 10, Katayama/Argade further teaches The compute-in-memory device of claim 7, wherein the first adder is further configured to: receive a select signal from the Booth encoder; and add a 1 bit to the least significant bit of the first number of inverted bits of the at least one weight based on the select signal (Argade: Fig. 1 element 108 of note c.sub.in; col 4 lines 26-28, as the select signal and Booth encoded bit as claimed may represent the same signal).
As per claim 11, Katayama/Argade further teaches The compute-in-memory device of claim 7, wherein the first adder is configured to: receive outputs of at least two multiplexers of the plurality of multiplexers (Argade: Fig. 1 element 107and Fig. 2 element 201; col 4 lines 25-29) and; add outputs of the at least two multiplexers to generate at least part of the plurality of partial products (col 4 lines 25-29; col 4 lines 50-51).
Claims 13, 15-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Katayama in view of Raha et al. (US 20210397414 A1, hereinafter “Raha”).
As per claim 13, the claim is directed to a method that implements the same or similar features as the compute-in-memory device of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, while Katayama discloses multiplier circuitry for booth multiplication, Katayama does not explicitly disclose the multiplier being a compute-in-memory circuit. Thus, Katayama does not teach a Booth encoder of the compute-in-memory-device; and a Booth decoder of the compute-in-memory device.
Raha teaches a Booth encoder of the compute-in-memory-device; and a Booth decoder of the compute-in-memory device (Raha: [0044]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the system of Katayama with the system of Raha. One would have been motivated to combine these references because both references disclose systems with Booth multipliers, and combining prior art elements according to known methods to yield predictable results (performing Booth multiplication near or in memory).
As per claim 15, Katayama/Raha further teaches The method of claim 13, wherein operating on the weight by the Booth decoder comprises directly mapping the weight generating a directly mapped weight (Katayama: Fig. 6A; [0054]; wherein Fig. 6A shows the mapping of weight bits).
As per claim 16, Katayama/Raha further teaches The method of claim 15, wherein operating on the weight by the Booth decoder further comprises left shifting the directly mapped weight (Katayama: Fig. 6B elements 452, 462, 472, 482; [0057]).
As per claim 17, Katayama/Raha further teaches The method of claim 15, wherein operating on the weight by the Booth decoder comprises inverting the weight generating an inverted weight (Katayama: Fig. 6B elements 451, 461; [0057]).
As per claim 18, Katayama/Raha further teaches The method of claim 17, wherein operating on the weight by the Booth decoder further comprises left shifting the inverted weight (Katayama: Katayama: Fig. 6B elements 452, 462; [0057]).
As per claim 20, Katayama/Raha further teaches The method of claim 13, further comprising: adding a plurality of portions of the partial product, including the portion of the partial product, generating the partial product (Katayama: Fig. 5 element 490; [0050]);
and adding a plurality of partial products, including the partial product, prior to generating all partial products of a Booth multiplication of the plurality of subsets of an input data and the weight (Katayama: Fig. 5 elements 491, 492, 493; [0058]).
Claims 14, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Katayama/Raha in view of Argade.
As per claim 14, Katayama/Raha further teaches The method of claim 13.
However, while Katayama discloses partial product multiplication by 0 (Fig. 6B element 471), Katayama does not explicitly disclose gating the input. Thus, Katayama does not teach wherein operating on the weight by the Booth decoder comprises logic gating the weight.
Argade teaches wherein operating on the weight by the Booth decoder comprises logic gating the weight (Fig. 2 element 202).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the partial product generators of Katayama with the ALU of Argade (Fig. 1 element 111) for at least the same reasons as discussed above in claim 5.
As per claim 19, Katayama/Raha further teaches The method of claim 17.
However, while Katayama discloses inverting input values (Fig. 6B elements 451, 461), Katayama does not explicitly disclose adding a “1” value to the least significant bit of the inverted weight. Thus, Katayama does not teach wherein operating on the weight by the Booth decoder further comprises adding a “1” value to a least significant bit of the inverted weight.
Argade teaches wherein operating on the weight by the Booth decoder further comprises adding a “1” value to a least significant bit of the inverted weight (Fig. 1 element 108; of note c.sub.in = f.sub.minus input into the adder).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the partial product generators of Katayama with the ALU of Argade (Fig. 1 element 111) for at least the same reasons as discussed above in claim 5.
Allowable Subject Matter
Claim 12 is allowed.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 9, the prior art of record does not teach or suggest a combination as claimed including: wherein a first adder of the plurality of adders is configured to: receive an enable signal and a Booth encoded bit of the at least one input from the Booth encoder;
shifting, by the shifter, the first number of bits of the at least one weight or the first number of inverted bits of the at least one weight based on the based on the Booth encoded bit.
Katayama discloses adders in Booth multiplication that include shifting (Fig. 6B elements 452, 462, 472, 482). Katayama does not suggest the shifting is done based on a Booth encoded bit. Therefore, Katayama does not teach or suggest a combination as claimed including the limitations identified above.
Argade discloses selecting between an input or a shifted input based on a Booth encoded bit (Fig. 2 element 200). Argade does not suggest shifting in the adder based on the Booth encoded bit. Therefore, Argade does not teach or suggest a combination as claimed including the limitations identified above.
Raha discloses shifting the output of the MAC ([0048]). Raha does not suggest the shifting is done based on a Booth encoded bit. Therefore, Raha does not teach or suggest a combination as claimed including the limitations identified above.
Chiang (US 20080222227 A1, hereinafter “Chiang”) discloses Booth multiplication with a shift signal bit that is input into a multiplexer (Fig. 4A). Chiang does not suggest the shifting of values based on the shift signal bit is performed in the adder (Fig. 11). Therefore, Chiang does not teach or suggest a combination as claimed including the limitations identified above.
As to claim 12, the prior art of record does not teach or suggest a combination as claimed including: a plurality of multiplexers coupled to weight data input lines and an output of the third NOR gate;
and a plurality of adders, wherein a first adder of the plurality of adders is coupled to outputs of a subset of the plurality of multiplexers, the output of the first NOR gate, the output of the second NOR gate, and the output of the third NOR gate.
Katayama discloses adders in Booth multiplication with a plurality of adders (Fig. 5). Katayama does not suggest the adder receiving signals corresponding to the outputs of the first, second, and third NOR gates. Therefore, Katayama does not teach or suggest a combination as claimed including the limitations identified above.
Argade discloses means to select values based on select signals (Fig. 2) and an adder (Fig. 1 element 108). Argade does not suggest the adder receiving outputs of the corresponding multiplexers and outputs of the corresponding first, second, and third NOR gates, in the manner claimed. Therefore, Argade does not teach or suggest a combination as claimed including the limitations identified above.
Raha discloses a multi-precision Booth multiplier. Raha does not suggest the multiplier using signal bits. Therefore, Raha does not teach or suggest a combination as claimed including the limitations identified above.
Chiang discloses Booth multiplication with three signal bits that are input into a multiplexer (Fig. 4A). Chiang does not suggest the adder receiving the corresponding outputs of the first, second, and third NOR gates. Therefore, Chiang does not teach or suggest a combination as claimed including the limitations identified above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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