Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7, 12-14 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Brist” (US 2009/0325415).
Regarding claim 7, Brist anticipates 7. An integrated circuit apparatus comprising: an integrated circuit die (Figs. 6-7, [0065]; die 141);
and a package substrate comprising circuitry to interconnect the integrated circuit die with a main circuit board (Figs. 6-7, 10, [0065], [0072]; interposer 155 interconnects the die 141 with the motherboard 165);
wherein the integrated circuit die is coupled to a first side of the package substrate and a second side of the package substrate opposite the first side comprises a plurality of electrical connectors arranged in an array of rows and columns (Figs. 5E, 6-7, [0038], [0051], [0065]; the die 141 is coupled to a top side of the interposer 155 and a bottom side of the interposer 155 comprises connectors arranged in an array of rows and columns, see Fig. 5E),
wherein a distance between a connector and its neighboring connectors in its column is less than a distance between the connector and its neighboring connectors in its row (Figs. 5E, 6-7, [0038], [0051], [0065]; a distance between a connector and its neighboring connectors in its column is less than a distance between the connector and its neighboring connectors in its row, see Fig. 5E, annotated below).
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Regarding claim 12, Brist anticipates 12. A system comprising: a main circuit board (Figs. 6-7, 10, [0065], [0072]; motherboard 165);
and a package coupled to the main circuit board, the package comprising: an integrated circuit die (Figs. 6-7, [0065]; die 141);
and a package substrate comprising circuitry to interconnect the integrated circuit die with the main circuit board (Figs. 6-7, 10, [0065], [0072]; interposer 155 interconnects the die 141 with the motherboard 165);
wherein the integrated circuit die is coupled to a first side of the package substrate and a second side of the package substrate opposite the first side comprises a plurality of electrical connectors arranged in a compressed array pattern (Figs. 5C, 5E, 6-7, [0038], [0051], [0065]; the die 141 is coupled to a top side of the interposer 155 and a bottom side of the interposer 155 comprises connectors arranged in a compressed array pattern, see Fig. 5E),
wherein a distance between a connector and its neighboring connectors in a direction of compression is less than a distance between the connector and its neighboring connectors in other directions (Figs. 5C, 5E, 6-7, [0038], [0051], [0065]; a distance between a connector and its neighboring connectors in a direction of compression is less than a distance between the connector and its neighboring connectors in other directions, see Fig. 5E).
Regarding claim 13, Brist anticipates 13. The system of claim 12, wherein the array pattern is a hexagonal array pattern (Figs. 5C, 5E, 6-7, [0038], [0051], [0065]; the array pattern is a hexagonal array pattern, see Figs. 5C, 5E).
Regarding claim 14, Brist anticipates 14. The system of claim 12, wherein the array pattern is a rectangular array pattern (Figs. 5C, 5E, 6-7, [0038], [0051], [0065]; the array pattern is a rectangular array pattern, see Fig. 5E).
Regarding claim 19, Brist anticipates 19. The system of claim 12, wherein the main circuit board is a motherboard and the integrated circuit die comprises a processor (Figs. 6-7, 10, [0065], [0072], [0084]; the main circuit board is a motherboard 165 and the die 141 is a processor).
Regarding claim 20, Brist anticipates 20. The system of claim 12, further comprising a socket coupled to the main circuit board, the socket comprising a set of pins to interconnect the package and the main circuit board (Fig. 10, [0072]; the socket comprising a set of pins to interconnect the package and the mother board 165).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Brist in view of “Mora” (US 6,479,319).
Regarding claim 1, Brist discloses 1. An integrated circuit apparatus comprising:
an integrated circuit die (Figs. 6-7, [0065]; die 141);
and a package substrate comprising circuitry to interconnect the integrated circuit die with a main circuit board (Figs. 6-7, 10, [0065], [0072]; interposer 155 interconnects the die 141 with the motherboard 165);
wherein the integrated circuit die is coupled to a first side of the package substrate and a second side of the package substrate opposite the first side comprises a plurality of electrical connectors arranged in a hexagonal array pattern (Figs. 5C, 6-7, [0038], [0051], [0065]; the die 141 is coupled to a top side of the interposer 155 and a bottom side of the interposer 155 comprises connectors arranged in a hexagonal array pattern, see Fig. 5C).
Brist does not disclose wherein a distance between a connector of a hexagonal pattern and its neighboring connectors in a first direction is less than a distance between the connector and its other neighboring connectors of the hexagonal pattern.
Mora discloses wherein a distance between a connector of a hexagonal pattern and its neighboring connectors in a first direction is less than a distance between the connector and its other neighboring connectors of the hexagonal pattern (Fig. 2, col. 3, lines 48-55; the staggered array 10 of the contacts 14 is offset from an adjacent row and column of contacts 14).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Brist’s integrated circuit apparatus with Mora’s offset staggered array of contacts in order to allow for an optimal routing of the traces and allow for a greater number of traces in a relatively reduced surface area, as suggested by Mora at col. 3, lines 56-61.
Regarding claim 6, Brist in view of Mora discloses the claimed invention as applied to claim 1, above.
Brist does not disclose the limitations of claim 6.
Mora discloses 6. The apparatus of claim 1, wherein the hexagonal array pattern defines a plurality of hexagonal patterns of neighboring connectors surrounding a center electrical connector, wherein a distance between the center electrical connector and its neighboring connectors of the hexagonal pattern in a first direction is less than a distance between the center connector and its other neighboring connectors of the hexagonal pattern (Fig. 2, col. 3, lines 48-55; the staggered array 10 of the contacts 14 is offset from an adjacent row and column of contacts 14 reads on this limitation).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Brist in view of Mora and “Siang” (US 2012/0228783).
Regarding claim 2, Brist in view of Mora discloses the claimed invention as applied to claim 1, above.
Brist discloses the pairs of electrical circuits are arranged in the first direction (Figs. 5C, 5E, [0049]; the connection pattern includes pairs of electrical circuits arranged in the first direction).
Brist does not disclose respective pairs of the electrical connectors are connected to corresponding differential pairs of the integrated circuit.
Siang discloses respective pairs of the electrical connectors are connected to corresponding differential pairs of the integrated circuit (Figs. 2A, 2B, [0018], [0022]; respective pairs of electrical connectors Net1A, Net1B, Net2A and Net2B, are connected to corresponding differential pairs of the integrated circuit).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Brist’s integrated circuit apparatus, as modified by Mora, with Siang’s differential pairs of connectors in order to improve the differential impedance requirement that does not affect the efficiency of power delivery circuits to supply clean-voltages from the IC package bond fingers up the die, as suggested by Siang at [0022].
Regarding claim 3, Brist in view of Mora and Siang discloses the claimed invention as applied to claim 2, above.
Brist does not disclose the limitations of claim 3.
Siang discloses 3. The apparatus of claim 2, wherein the differential pairs are high-speed input/output connections for the integrated circuit (Figs. 2A, 2B, [0018], [0022]; the differential pairs are high-speed I/O connections for the integrated circuit).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Brist in view of Mora, Siang and “Zhang“ (CN112788832A).
Regarding claim 4, Brist in view of Mora and Siang discloses the claimed invention as applied to claim 2, above.
Brist does not disclose the limitations of claim 4.
Zhang discloses 4. The apparatus of claim 2, wherein the hexagonal array pattern has a signal to ground ratio of 1:1.5 (page 4, middle, the differential via hole arrangement has a signal to ground ratio of 1:1.5).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Brist’s integrated circuit apparatus, as modified by Mora and Siang, with Zhang’s signal to ground ratio since Sun at page 4, middle, teaches that this is a “traditional differential vial hole arrangement.” Therefore, a person having ordinary skill would have understood that has a signal to ground ratio of 1:1.5 was well known in the art.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Brist in view of Mora, Siang and “Chang“ (CN112541318A).
Regarding claim 5, Brist in view of Mora and Siang discloses the claimed invention as applied to claim 2, above.
Brist does not disclose the limitations of claim 5.
Chang discloses 5. The apparatus of claim 2, wherein the hexagonal array pattern has a signal to ground ratio of 1:2 (page 4, middle; the ratio of the signal to ground is 1:2).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Brist’s integrated circuit apparatus, as modified by Mora and Siang, with Chang’s signal to ground ratio in order to improve the channel isolation of the high-speed differential signal, as suggested by Chang at page 4, middle.
Claims 8-9 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Brist in view of Siang.
Regarding claim 8, Brist discloses the claimed invention as applied to claim 7, above.
Brist discloses the pairs of electrical circuits are arranged in the column direction (Figs. 5C, 5E, [0049]; the connection pattern includes pairs of electrical circuits arranged in the column direction).
Brist does not disclose respective pairs of the electrical connectors are connected to corresponding differential pairs of the integrated circuit.
Siang discloses respective pairs of the electrical connectors are connected to corresponding differential pairs of the integrated circuit (Figs. 2A, 2B, [0018], [0022]; respective pairs of electrical connectors Net1A, Net1B, Net2A and Net2B, are connected to corresponding differential pairs of the integrated circuit).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Brist’s integrated circuit apparatus with Siang’s differential pairs of connectors in order to improve the differential impedance requirement that does not affect the efficiency of power delivery circuits to supply clean-voltages from the IC package bond fingers up the die, as suggested by Siang at [0022].
Regarding claim 9, Brist in view of Siang discloses the claimed invention as applied to claim 8, above.
Brist does not disclose the limitations of claim 9.
Siang discloses 9. The apparatus of claim 8, wherein the differential pairs are high-speed input/output connections for the integrated circuit (Figs. 2A, 2B, [0018], [0022]; the differential pairs are high-speed I/O connections for the integrated circuit).
Regarding claim 15, Brist discloses the claimed invention as applied to claim 12, above.
Brist discloses the pairs of electrical circuits are arranged in the direction of compression (Figs. 5C, 5E, [0049]; the connection pattern includes pairs of electrical circuits arranged in the direction of compression).
Brist does not the array pattern comprises sets of differential pair connections for the integrated circuit.
Siang discloses the array pattern comprises sets of differential pair connections for the integrated circuit (Figs. 2A, 2B, [0018], [0022]; respective pairs of electrical connectors Net1A, Net1B, Net2A and Net2B, are connected to corresponding differential pairs of the integrated circuit).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Brist’s integrated circuit apparatus with Siang’s differential pairs of connectors in order to improve the differential impedance requirement that does not affect the efficiency of power delivery circuits to supply clean-voltages from the IC package bond fingers up the die, as suggested by Siang at [0022].
Regarding claim 16, Brist in view of Siang discloses the claimed invention as applied to claim 15, above.
Brist does not disclose the limitations of claim 16.
Siang discloses 16. The system of claim 15, wherein at least certain of the differential pair connections are high-speed input/output connections for the integrated circuit (Figs. 2A, 2B, [0018], [0022]; the differential pairs are high-speed I/O connections for the integrated circuit).
Regarding claim 17, Brist in view of Siang discloses the claimed invention as applied to claim 16, above.
Brist does not disclose the limitations of claim 17.
Siang discloses 17. The system of claim 16, wherein at least certain of the differential pair connections are Peripheral Component Interconnect Express (PCIe) connections for the integrated circuit (Figs. 2A, 2B, [0004], [0018], [0022]; the differential pair connections are PCI-E electrical interface connections for the integrated circuit).
Regarding claim 18, Brist in view of Siang discloses the claimed invention as applied to claim 16, above.
Brist does not disclose the limitations of claim 16.
Siang discloses 18. The system of claim 16, wherein the main circuit board comprises a set of differential pairs arranged in two rows, the set of differential pairs connected to respective traces on the same layer of the main circuit board (Figs. 2A, 2B, [0017], [0018], [0022]; the differential pairs of the external interface 212 are arranged in two rows, the set of differential pairs connected to respective traces or wires 208 on the same layer of the circuit board).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Brist in view of Siang and “Millard“ (US 2012/0052738).
Regarding claim 10, Brist in view of Siang discloses the claimed invention as applied to claim 8, above.
Brist does not disclose the limitations of claim 10.
Millard discloses 10. The apparatus of claim 8, wherein a first pair of electrical connectors corresponding to a first differential pair is arranged at a distance of 1.5 pins from a second pair of electrical connectors corresponding to a second differential pair (Fig. 6, [0033]; the pair separation distance Dp is 1.5 times the contact separation distance Dc).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Brist’s integrated circuit apparatus, as modified by Siang, with Millard’s separation distance for differential pairs of connectors with respect to each other in order to effectively operate at high transmission speeds such as ten gigabits per second, as suggested by Millard at [0005].
Regarding claim 11, Brist in view of Siang discloses the claimed invention as applied to claim 8, above.
Brist does not disclose the limitations of claim 11.
Millard discloses 11. The apparatus of claim 8, wherein a first pair of electrical connectors corresponding to a first differential pair is arranged at a distance of 2 pins from a second pair of electrical connectors corresponding to a second differential pair (Fig. 6, [0033]; the pair separation distance Dp is two times greater than the contact separation distance Dc).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Brist’s integrated circuit apparatus, as modified by Siang, with Millard’s separation distance for differential pairs of connectors with respect to each other in order to effectively operate at high transmission speeds such as ten gigabits per second, as suggested by Millard at [0005].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
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/STANLEY TSO/Primary Examiner, Art Unit 2847