DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election, without traverse, of group I : claims 1-14 in the “Response to Election / Restriction Filed -09/30/2025”, is acknowledged. Applicant request of adding group III claims 20-23 to the election is persuasive.
In view of the above, this office action considers claims 1-23 pending for prosecution, of which, non-elected claims 15-19 are withdrawn, and elected claims 1-14 and 20-23 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (400; Fig 4B; [0079]) = (element 400; Figure No. 4B; Paragraph No. [0079]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-10 are rejected under 35 U.S.C. 102(a) (2) as being anticipated by Maldonado-Garcia; Maribel et al. (US 20220310909 A1) hereinafter Maldonado; see alternative rejection of claims 1-4 in section II, infra).
1. Maldonado teaches a memory device (400) comprising (see the entire document, Figures 4B, 3A-3B along with Figures 1-4A as referenced earlier in the art, specifically, as cited below):
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Maldonado Figure 4B
a memory cell (400; Fig 4B; [0079+] or 54a in Figs 3A-3B) comprising a storage element (402; Fig 4A) including a phase change memory (PCRAM; [0080]); and
a bilayer ({472, 474}) formed on a first side and a second side of the memory cell (402), the bilayer including an inner layer (472) comprising a first nitride ([0081]) and an outer layer (474) comprising a second nitride ((SiON; [0082)).
2. The memory device of claim 1, Maldonado further teaches, wherein the first nitride is silicon nitride (SIN; [0081]) and the second nitride is silicon nitride (SiON; [0082).
3. The memory device of claim 1, Maldonado further teaches, (the device) further comprising a dielectric material (70; Fig 3B) between a side of the bilayer and a side of a second bilayer encapsulating a second memory cell adjacent to the memory cell
4. The memory device of claim 1, Maldonado further teaches, wherein the storage element (402) comprises a chalcogenide material (PCRAM a phase change chalcogenide material [0002, 0034]).
5. The memory device of claim 1, Maldonado further teaches, wherein the inner layer (472) has an average thickness that is less (Fig 4b and [0071]: where 472’s thickness construed as 10A and 474’s thickness as 50A ) than an average thickness of the outer layer (474).
6. The memory device of claim 1, Maldonado further teaches wherein the inner layer (472) has an average thickness of between 10 and 30 angstroms ([0071]).
7. The memory device of claim 1, Maldonado wherein the outer layer (474) has an average thickness of between 20 to 50 angstroms (construed from [0071], in some embodiments, the encapsulation layer may be deposited with a thickness in a range of 20 Å to 30 Å).
8. The memory device of claim 1, Maldonado further teaches, wherein a conformality exhibited by the outer layer 274 is higher than (construed from [0082] 474 is grown by oxidizing 472; 474 inherently had higher conformality) a conformality exhibited by the inner layer (272).
9. The memory device of claim 1, Maldonado further teaches, wherein an overhang thickness of a top portion of the bilayer (Figs 3B, 4B) that extends past the first side of the memory cell is less than 1.5 times a thickness of the bilayer on the first side of the memory cell at a selector device of the memory cell.
10. The memory device of claim 1, Maldonado further teaches, wherein an average thickness of the inner layer is greater (construed from Fig 3B, 4B) towards the top of the memory cell than along the first side or second side of the memory cell.
Claims 1-4 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by DONG; Cha Deok et al. (US 20230171967 A1) hereinafter Dong . see alternative rejection of claims 1-4 in section I, supra
1. Dong teaches a memory device comprising (see the entire document, Figures 5C-5E along with Figures 1-5B and 6 as referenced earlier or later in the art, specifically, as cited below):
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Dong Figure 5E
a memory cell (520; Figs 5E; [0111+]) comprising a storage element (302/524) including a phase change memory ([0030] construed from the relation that variable resistance layer 524 at [0113] and that of 125 at [0030]); and
a bilayer ({550-1, 550-2}) formed on a first side and a second side of the memory cell, the bilayer including an inner layer (550-1) comprising a first nitride ([0073/ 0119])) and an outer layer (550-2)) comprising a second nitride (construed from [0073,0119]).
2. The memory device of claim 1, Dong further teaches, wherein the first nitride is silicon nitride and the second nitride is silicon nitride (SiN.sub.4; [0073/ 0119]).
3. The memory device of claim 1, Dong further teaches, (the device) further comprising a dielectric material (540-1. 540-2) between a side of the bilayer and a side of a second bilayer encapsulating a second memory cell adjacent to the memory cell
4. The memory device of claim 1, Dong further teaches, wherein the storage element (524) comprises a chalcogenide material (a phase change material such as a chalcogenide-based material [0030] construed from the relation that variable resistance layer 524 at [0113] and that of 125 at [0030])).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over DONG; Cha Deok et al. (US 20230171967 A1) hereinafter Dong; in view of YOON; Young Hee et al. (US 20180061891 A1); hereinafter Yoon.
11. Dong as applied to the memory device of claim 1, does not expressly disclose, the device further comprising a plurality of memory chips, wherein a memory chip of the plurality of memory chips comprises the memory cell, though Dong suggests in (paragraphs [0002, 0004] and (Fig 1A) memory devices and their applications in electronic devices or systems.
However, in the analogous art, Yoon teaches a (Fig 12; [0044+]) a computer system of this example embodiment may include a processor 500, a cache memory 507 to 509, and a plurality of system memories 516 to 519, wherein ([0050]) the system memories 516 to 519 may include a near memory of a PRAM memory; and [0051] the computer system according to an embodiment may be interfaced with a dual in-line memory module (DIMM) that is used as a storage device on which the semiconductor integrated circuit device is mounted. The semiconductor integrated circuit device mounted on the DIMM may include the PRAM according to an embodiment.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use Dong’s comprises the memory cells in plurality of memory chips in Yoon’s system, and thereby, the combination of (Dong and Yoon) will have a device comprising a plurality of memory chips, wherein a memory chip of the plurality of memory chips comprises the memory cell (Dong), since this application will usage Dong’s memory cell as suggested by Dong.
12. The combination of (Dong and Yoon) as applied to the memory device of claim 11, further comprising a memory controller ([0048]) to communicate with the plurality of memory chips.
13. The combination of (Dong and Yoon) as applied to the memory device of claim 1 (with the same rational established in claim 11 above) , wherein the memory device comprises a solid state drive (DIMM and the computer system (e.g., a CPU package; Yoon [0052)].
14. The combination of (Dong and Yoon) as applied to the memory device of claim 1 (with the same rational established in claim 11 above) wherein the memory device comprises a dual in-line memory module (DIMM Yoon [0051]).
Claims 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over f YOON; Young Hee et al. (US 20180061891 A1); hereinafter Yoon; in view of DONG; Cha Deok et al. (US 20230171967 A1) hereinafter Dong
20. Yoon teaches a system comprising (see the entire document, Figure 12 paragraph [0044=] along with Figures 1-11 as referenced earlier or later in the art, specifically, as cited below) :
a memory chip (near memory) comprising (a plurality of system memories 516 to 519 ):
a memory array (Fig 1A ) comprising ([0020] a cell array of a variable resistive memory device ):
a plurality of memory cells (MC; Figs 2-3), wherein a memory cell comprises a storage element (a storage layer [0021]) including a phase change memory (MC; Fig 2; [0021] ) a phase-change material such as a chalcogenide material) ; and
Yoon does not expressly disclose:
a plurality of bilayers, wherein a bilayer is formed on a first side and a second side of the memory cell, the bilayer including an inner layer comprising a first nitride and an outer layer comprising a second nitride.
However in the analogous art as disclosed in section II above, Dong teaches a memory device comprising a memory cell (520; Figs 5E; [0111+]) comprising a storage element (302/524) including a phase change memory ([0030] construed from the relation that variable resistance layer 524 at [0113] and that of 125 at [0030]), wherein a bilayer ({550-1, 550-2}) is formed on a first side and a second side of the memory cell, the bilayer including an inner layer (550-1) comprising a first nitride ([0073/ 0119])) and an outer layer (550-2)) comprising a second nitride (construed from [0073,0119]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to contemplate Dong’s bilayers for Yoon MC, and thereby, the combination of (Yoon and Dong) will have a bilayer as claimed., since this bilayer as encapsulation layer protect the memory cell from external influences (Dong [0053]).
21. The combination of (Yoon and Dong) as applied to the system of claim 20, Yoon further teaches, (the system) further comprising a second memory chip and a controller [0048]) coupled to the memory chip and the second memory chip.
22. The combination of (Yoon and Dong) as applied to the system of claim 20, Yoon further teaches, (the system), further comprising a processor (500; Fig 12; [0045]) to generate data to be stored by the memory array, the processor to couple to the memory chip through a storage device controller of a storage drive comprising the memory chip.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over f YOON; Young Hee et al. (US 20180061891 A1); hereinafter Yoon; in view of DONG; Cha Deok et al. (US 20230171967 A1) hereinafter Dong; and in further view of REDAELLI; Andrea et al. (US 20230171967 A1) hereinafter Redaelli
23. The combination of (Yoon and Dong) as applied to the system of claim 22, Yoon does not express disclose, (the system) further comprising, one or more of: a battery communicatively coupled to the processor (500), a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.
However, in the analogous art, Redaelli teaches a stacked memory device ([0001) wherein ([0102]) the crosspoint architecture comprises a three dimensional (3D) crosspoint (3DXP) nonvolatile memory architecture and the system includes one or more of: wherein the processor comprises a multicore central processing unit (CPU); a display communicatively coupled to the processor; a battery to power the system; or a network interface communicatively coupled to the processor.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to contemplate Redaelli’s teaching for combination of (Yoon and Dong), and thereby, the combination of (Dong and Yoon and Redaelli ) will have a system as claimed since this inclusion , at least, provide no-interruption usage for Yoon system.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached on M-F: 8:30AM - 6:00 PM. EST.
Examiner interviews are available via telephone, in-person, and video The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached on M-F: 8:30AM - 6:00 PM. EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
October 10, 2025