DETAILED ACTION
This action is responsive to the amendment received February 20, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21, 22, 25-27, 31-33, 39, 40, 44, and 45 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sudo (US 2013/0065326).
(Re Claim 21) Sudo teaches a semiconductor device comprising: a plurality of fins having parallel lengths extending in a horizontal direction, the plurality of fins comprising a first fin and a second fin which are separated from each other by an isolation region; and the isolation region comprising a first portion proximate to the first fin, a second portion proximate to the second fin, and a third portion disposed between the first portion and the second portion, wherein the first and second portions each comprise a liner that comprises (i) a first vertical section immediately adjacent to the respective first or second fin and (ii) a second vertical section adjacent to and in direct contact with the third portion, wherein an upper surface of the first vertical section is substantially coplanar with an upper surface of the second vertical section (see Fig. 13A-13C, fins 30, isolation vertical first/second portions 26, third portion 28).
(Re Claim 22) wherein: each of the plurality of fins extends above a horizontal plane comprising a top surface of a substrate; and at least a portion of the isolation region extends below the horizontal plane (horizontal plane at top surface of 21).
(Re Claim 25) further comprising: a gate structure formed over the first and second fins (gate 32).
(Re Claim 26) wherein an upper surface of the third portion is substantially coplanar with an upper surface of the first portion (see Fig. 13C).
(Re Claim 27) wherein an upper surface of the third portion is substantially coplanar with upper surfaces of the first and second portions (see Fig. 13C).
(Re Claim 31) wherein a width of at least a portion of the first fin is substantially the same as a width of the third portion of the isolation region (see Fig. 13C).
(Re Claim 32) wherein the liners of the first and second portions comprise a discontinuous dielectric material liner disposed between the first and second fins (see Fig. 13C).
(Re Claim 33) Sudo teaches a semiconductor device comprising: a plurality of fins having parallel lengths extending in a first horizontal direction, the plurality of fins comprising a first fin, a second fin adjacent to the first fin, a third fin adjacent to the second fin, and a fourth fin adjacent to the third fin, wherein a center-to-center distance between the second and third fins is about 2 times a center-to-center distance between the first and second fins; the first fin comprises an inward-facing side that faces the second fin; the second fin comprises an inward-facing side that faces the third fin and an opposite outward-facing side that faces the first fin; the third fin comprises an inward-facing side that faces the second fin and an opposite outward-facing side that faces the fourth fin; the fourth fin comprises an inward-facing side that faces the third fin; the inward-facing sides of the second and third fins are separated from each other by a first isolation region comprising a first portion proximate to the second fin, a second portion proximate to the third fin, and a third portion disposed between the first portion and the second portion; and the first and second portions each comprise a liner that comprises (i) a first vertical section disposed on the inward-facing side of the second or third fin and (ii) a second vertical section adjacent to and in direct contact with the third portion (see Fig. 13A-13C, fins 30, isolation first/second vertical first/second portions 26, third portion 28).
(Re Claim 39) wherein an upper surface of the third portion is substantially coplanar with an upper surface of the first portion (see Fig. 13C)
(Re Claim 40) wherein an upper surface of the third portion is substantially coplanar with upper surfaces of the first and second portions (see Fig. 13C).
(Re Claim 44) wherein a width of at least a portion of the second fin is substantially the same as a width of the third portion of the first isolation region (see Fig. 13C).
(Re Claim 45) wherein the liners of the first and second portions comprise a discontinuous dielectric material liner disposed between the second and third fins (see Fig. 13C).
Claims 21, 29, 30, 33, 34, 42, and 43 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US 2015/0249127).
(Re Claim 21) Xie teaches a semiconductor device comprising: a plurality of fins having parallel lengths extending in a horizontal direction, the plurality of fins comprising a first fin and a second fin which are separated from each other by an isolation region; and the isolation region comprising a first portion proximate to the first fin, a second portion proximate to the second fin, and a third portion disposed between the first portion and the second portion, wherein the first and second portions each comprise a liner that comprises (i) a first vertical section immediately adjacent to the respective first or second fin and (ii) a second vertical section adjacent to and in direct contact with the third portion, wherein an upper surface of the first vertical section is substantially coplanar with an upper surface of the second vertical section (see Fig. 2N, fins 107, isolation vertical first/second portions 109F, third portion 114).
(Re Claim 29) wherein the liners comprise a silicon nitride (¶39).
(Re Claim 30) wherein the liners have a thickness of less than about 5 nm (¶39).
(Re Claim 33) Xie teaches a semiconductor device comprising: a plurality of fins having parallel lengths extending in a first horizontal direction, the plurality of fins comprising a first fin, a second fin adjacent to the first fin, a third fin adjacent to the second fin, and a fourth fin adjacent to the third fin, wherein a center-to-center distance between the second and third fins is about 2 times a center-to-center distance between the first and second fins; the first fin comprises an inward-facing side that faces the second fin; the second fin comprises an inward-facing side that faces the third fin and an opposite outward-facing side that faces the first fin; the third fin comprises an inward-facing side that faces the second fin and an opposite outward-facing side that faces the fourth fin; the fourth fin comprises an inward-facing side that faces the third fin; the inward-facing sides of the second and third fins are separated from each other by a first isolation region comprising a first portion proximate to the second fin, a second portion proximate to the third fin, and a third portion disposed between the first portion and the second portion; and the first and second portions each comprise a liner that comprises (i) a first vertical section disposed on the inward-facing side of the second or third fin and (ii) a second vertical section adjacent to and in direct contact with the third portion (see Fig. 2N, fins 107, isolation vertical first/second portions 109F, third portion 114).
(Re Claim 34) further comprising: second isolation regions disposed between the (iii) outward-facing side of the second fin and the inward-facing side of the first fin, and (iv) between the outward-facing side of the third fin and the inward-facing side of the fourth fin, wherein the second isolation regions each comprise a liner that comprises (v) a vertical section disposed on the inward-facing side of the first or fourth fin, and (vi) a vertical section disposed on the outward-facing side of the second or third fin (see Fig. 2N: 110 and 109).
(Re Claim 42) wherein the liners comprise a silicon nitride (¶39).
(Re Claim 43) wherein the liners have a thickness of less than about 5 nm (¶39).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 28, 30, 41, and 43 are rejected under 35 U.S.C. 103 as being unpatentable over Sudo as applied above and further in view of Lee et al. (US 2004/0256647) and Tsai et al. (US 2013/0043506).
(Re Claims 28 and 41) wherein the liners comprise a dielectric metal oxide.
(Re Claims 30 and 43) wherein the liners each have a thickness of less than about 5 nm.
Sudo is silent regarding the liners comprising a dielectric metal oxide and does not disclose a thickness. It is noted Sudo performs multiple operations to form both the liners and the gate dielectric of the same material (see Figs. 8C, 9C, and 10C). This is because Sudo wants to preserve mask 12 when etching back 28 because mask 12 prevents fin height loss when subsequently oxidizing the fin sidewalls and is later used to protect the silicon fins when patterning the polysilicon gate. A PHOSITA would recognize several improvements can be made to Sudo’s fin-fet, including using a metal gate rather than a polysilicon gate and depositing a high-k gate dielectric rather than thermally oxidizing the fins. With these obvious changes, a high-k gate dielectric material can be deposited rather formed by thermal oxidation thereby avoiding a high temperature oxidation step, then mask 12 is not needed during the LOCOS-like oxidation, and when using a metal gate, the metal can be selectively etched with respect to the fins without needing the mask 12. One may simply deposit the high-k dielectric as layer 26 following Fig. 8C, and it does not matter if mask 12 remains in place or is removed, although removing the unnecessary mask may allow for smaller/thinner devices. Related art from Tsai teaches (¶¶17,29) the gate may be formed from either polysilicon or metal and teaches the gate dielectric may be either silicon oxide or a high-k metal oxide. Related art from Lee also teaches the gate dielectric may either be thermally grown silicon oxide or a deposited high-k metal oxide (¶104) and teaches the equivalent thickness in a range of 0.3-10 nm, preferrable 0.3-3 nm and when using a high-k metal oxide, this will be thinner. Conventional metal oxide high-k gate dielectrics are known to offer several advantages over conventional thermal oxide, for example high-k materials allows for increased gate capacitance while reducing leakage, can be deposited at lower temperatures thereby reducing the thermal budget, a thinner film can be used to provide the same functional insulation as a thicker silicon oxide film making high-k materials more scalable. A metal gate offers several advantages over a polysilicon gate, specifically lower resistance, the ability to tune the work function, and metals can be deposited at much lower temperature than poly-Si. In view of the prior art and these known advantages of using these materials in a fin-fets, a PHOSITA would be motivated to form a high-k gate dielectric following Fig. 8C, and use an appropriate thickness according to the prior at, and to use a metal gate electrode in Sudo’s fin-fet to form an improved, higher performance fin-fet with a lower resistance metal gate and high-k metal oxide gate insulator while eliminating process steps including the high temperature oxidation and polysilicon deposition steps. With these obvious modifications to Sudo’s fin-fet, the liner is the high-k metal oxide gate dielectric having a thickness within the claimed range.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Sudo teaches the amended limitations of claims 21 and 33, see Fig. 13C, first and second portions 26 having ends with upper surfaces that are coplanar in the horizontal plane between 32 and 21. Similarly, Xie teaches the amended limitations of claims 21 and 33, see Fig. 2N, first and second portions 109F having ends with upper surfaces that are coplanar in the horizontal plane.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898