Office Action Predictor
Application No. 17/751,093

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
May 23, 2022
Examiner
BELOUSOV, ALEXANDER
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., LTD.
OA Round
3 (Non-Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
3y 0m
To Grant
89%
With Interview

Examiner Intelligence

76%
Career Allow Rate
386 granted / 507 resolved
Without
With
+12.7%
Interview Lift
avg trend
3y 0m
Avg Prosecution
28 pending
535
Total Applications
career history

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
61.4%
+21.4% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
12.2%
-27.8% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1-9, 13 & 24 are rejected under 35 U.S.C. 103 as being unpatentable over US-2022/0237359) by Peng et al (“Peng”) in view of (US-2018/0294226) by Lee et al (“Lee”). Regarding claim 1, Peng discloses in FIGs. 6A-G (rotate drawings for readability, clockwise 90 degrees) and related text, e.g., a semiconductor device (Title) comprising: a standard cell (par. 116; 6A-G are standard cells) comprising: a plurality of active patterns (par. 339) extending in a first direction (patterns 202, horizontal in FIG. 2F; same thing in FIGs. 6, per par. 339; also shown as “X” in top right corners of FIGs. 6B-G), the plurality of active patterns being spaced apart from each other in a second direction (“Y” direction as shown in top right corners of FIGs. 6B-G) intersecting the first direction, a gate structure (various 606’s shown in FIG. 6E) intersecting the plurality of active patterns (see FIG. 2F for how its gates intersect its active) and extending in the second direction (“Y”), and source/drain regions respectively provided on the plurality of active patterns on both sides of the gate structure (see FIG. 2F for visual example; gates are shown, intersections with active are shown; source/drain are to the left and right of the intersections); a plurality of signal lines (see FIGs. 6B-C; (mx1, mx2, clkb, cp, etc. are shown as “signal lines) extending on a first level of the standard cell (see how “mx1” is marked/shaded) in the first direction (“X”), and electrically connected to the standard cell (FIGs. 6A-G are standard cells; hence, meeting limitations); and a first power strap and a second power strap (see FIG. 6E for detailed view (not detailed view is FIG. 6B); 650d (VDD) and 650a (VSS) can be “first” and “second”; however, at least 4 objects meeting limitations are shown in FIG. 6E) extending on the first level of the standard cell (see how “VDD/VSS” is marked/shaded; it has the same shading as “mx1”; hence, it is intended to be on the same level, “first”, for the sake of naming it) in the first direction (“X”), each of the first power strap and the second power strap electrically connected to one or more of the source/drain regions (see FIG. 1A; overall circuit is shown; power and ground symbols are shown; they are shown to electrically connect to sources/drains), the first power strap and the second power strap configured to supply power to the standard cell (they are shown inside the standard cell, as was discussed above; also, see FIG. 1A and related text as was discussed above), wherein each of the first power strap and the second power strap is provided on a same row as one of the plurality of signal lines (see FIG. 6E; 650D is in the same row as mx1; 650a is in the same row as mx2), wherein one or more of the plurality of signal lines are provided between the first power strap and second strap in second direction (first of all, see FIG. 6E; note the topmost border of “first power strap” 650d and the bottommost border of 650a; one or more of the plurality of signal lines has to be provided between those two borders, in order to be “provided between”; now see other figures among 6C-D; there are many signals that fit between those 2 borders; for example, a signal line marked “D” in FIG. 6B’s top left corner; it fits between those 2 borders; thus meeting limitations). Peng does not disclose “a first power line extending in the first direction on a second level, below the first level, on the standard cell, the first power line overlapping the first power strap in a third direction perpendicular to the first direction”. Peng also does not disclose “wherein each of the first power strap and the second power strap has a first width equal to a second width of the one of the plurality of signal lines”. Lee discloses in FIG. 3C and related text, e.g., “a first power line (L01c or L02c; par. 31) extending in the first direction on a second level (in the instant case, M1 or M2; below M3 or M2), below the first level (in the instant case, M2 or M3), on the standard cell (see Title), the first power line overlapping the first power strap in a third direction perpendicular to the first direction (in the instant case L02c overlaps L03c, or L01c overlaps L02c; thus meeting limitation; the “third direction” is vertical; please note that Lee explicitly teaches presence of signals on higher layers (M2 or M3) [Wingdings font/0xE0] see par. 31; hence, signal lines will be present on the same level as power strap (M2 or M3), as is required by claim limitations).” It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Peng with “a first power line extending in the first direction on a second level, below the first level, on the standard cell, the first power line overlapping the first power strap in a third direction perpendicular to the first direction” and with “wherein each of the first power strap and the second power strap has a first width equal to a second width of the one of the plurality of signal lines”, in order to reduce a chance of voltage drop (or an IR drop) on a pattern (par. 3 of Lee; this is the whole point of his invention; Lee teaches presence of power metallization on multiple levels, all to deal with potential IR drop), and in order to achieve desired current carrying capacity and desired voltage drop and can be arbitrarily increased or decreased (par. 3 of Peng), respectively. To elaborate briefly on the above, the cited limitations refer to concepts that are addressed in sophomore year of Electrical Engineering undergraduate program; specifically, the ability of wiring of particular width to carry particular amount of current and to do so with a limited voltage drop; the most important scientific concept of Electrical Engineering that Voltage = Current * Resistance (also known as Ohm’s Law); thus, for a particular wiring Resistance is known, as a manufacturing process constant; Input Voltage is known; therefore, the amount of Current that circuit can carry can be calculated; one can also calculated the Voltage drop over a particular length of wiring. Thus, they are a result effective variables (referring to Applicant’s arguments). In simplest terms, the Applicant claims that at least 3 pieces of wiring have the same width; the width of particular wiring is simply a design consideration; if one wants a specific current capacity, and/or specific voltage drop, one will use a particular width to achieve that result; hence, the claimed widths are just a matter of obvious design choice, in a particular design, in a particular manufacturing process; and thus, such modification is very obvious to a POSITA. Peng also explicitly teaches in par. 3, that any dimensions can be arbitrarily increased or decrease. The Examiner’s elaboration above is giving some background as to why someone would want to do that. It is an Electrical Engineering undergraduate program concept, and thus below level of POSITA and very obvious to POSITA. A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Regarding claim 2, the combined device of Peng and Lee disclose in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claim, except “wherein each of the first power strap and the second power strap has a first width equal to a second width of the one of the plurality of signal lines”. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Peng with “wherein each of the first power strap and the second power strap has a first width equal to a second width of the one of the plurality of signal lines”, since Peng explicitly teaches that such modifications are within the bounds of his invention (see par. 3; “In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion”. A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). When the above explicit teachings of Peng (about arbitrariness of dimensions) are applied to device of FIG. 6E, the widths of 650d/650c, 650a (middle portion; directly under mx2), mx1 and mx2 could be adjusted to match for arbitrary reason, as Peng explicitly teaches. Regarding claim 3, the combined device of Peng and Lee disclose in cited figures and related text, e.g., wherein the plurality of signal lines are arranged to have a same pitch in the second direction (see FIG. 6C; signal lines appear to “have a same pitch” in “Y” direction; hence, the limitations are at the very least obvious). Regarding claim 4, the combined device of Peng and Lee disclose in cited figures and related text, e.g., wherein at least one of the first power strap and the second power strap is provided on a boundary of the standard cell in the first direction (FIG. 6E, 650D is on the cell boundary 201b). Regarding claim 5, the combined device of Peng and Lee disclose in cited figures and related text, e.g., wherein at least one of the first power strap and the second power strap is provided in the standard cell (both 650d and 650a have at least some portions that are in the standard cell; hence, meeting limitations). Regarding claim 6, the combined device of Peng and Lee disclose in cited figures and related text, e.g., wherein the first power strap (FIG. 6E, 650d) is provided on a first boundary (top of 201b) of the standard cell in the first direction, and the second power strap (650a) is provided in a region inside the standard cell, adjacent (Webster: “not distant”) to a second boundary (bottom of 201b) positioned opposite to the first boundary. Regarding claim 7, the combined device of Peng and Lee disclose in cited figures and related text, e.g., wherein the one of the plurality of signal lines includes two signal lines (mx1 and mx2), each of the two signal lines respectively positioned at one end of each of the first power strap and the second power strap (see FIG. 6E; the left end of mx1 and mx2 faces the right end of 650d and 650a). Regarding claim 8, the combined device of Peng and Lee disclose in cited figures and related text, e.g., wherein at least one of the first power strap or the second power strap includes two power straps respectively positioned at both ends of the one of the plurality of signal lines (for example, mx1 has 650d on one end and 650c on the other end; thus meeting limitations). Regarding claim 9, the combined device of Peng and Lee disclose in cited figures and related text, e.g., wherein the standard cell further includes a first contact structure (see FIG. 3D, to see “contact structures”; V0, VD and VB are shown at the very least) connected to one of the source/drain regions (see FIG. 1A; it is all one electrical circuit; hence, each and every single one of V0/VD/VB electrically connects to source/drain regions) and positioned in a third direction (“Z” in FIG. 3D), perpendicular to the first and second directions (as shown by the symbol in top right corner of FIG. 3D), and a second contact structure (various 216’s in FIG. 6F) connected to the gate structure (see par. 160 for discussion of their connection to the gate) and positioned in the third direction (as was already discussed regarding FIG. 3D). Regarding claim 13, the combined device of Peng and Lee disclose in cited figures and related text, e.g., wherein each of the plurality of active patterns includes an active fin (see FIG. 3D, 302d1; also, see par. 202; fin type devices are explicitly taught) protruding in a third direction (“Z” in fig. 3D), perpendicular to the first and second directions (see symbol in top right corner), and the gate structure includes a gate electrode intersecting the active pattern and extending in the second direction (FIG. 2F shows intersection of active and gate in the specified directions, as was already discussed above) and a gate insulating film provided between the gate electrode and the active fin (par. 587; “gate dielectric” it being between “gate electrode” and “active fin” is notoriously well-known). Regarding claim 24, the combined device of Peng and Lee disclose in cited figures and related text, e.g., a semiconductor device (see claims above) comprising: a plurality of active patterns extending in a first direction (see claims above), the plurality of active patterns being spaced apart from each other in a second direction different from the first direction (see claims above); a gate structure intersecting the plurality of active patterns (see claims above) and extending in the second direction (see claims above), and a source region provided a first side of the gate structure and a drain region provided on a second side of the gate structure (see claims above); a plurality of signal lines extending in the first direction on a first level (see claims above); a first power strap extending on the first level in the first direction on a same row as a first signal line (see claims above), among the plurality of signal lines, the first power strap electrically connected to one of the source region or the drain region (see claims above); and a first power line extending in the first direction on a second level, below the first level, the first power line overlapping the first power strap in a third direction perpendicular to the first direction (see claim 1), wherein the first power strap has a first width equal to a second width of the one of the plurality of signal lines (see claim 1), and wherein one or more of the plurality of signal lines are provided between the first power strap and second strap in second direction (see claim 1). Conclusion Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Alexander Belousov/Patent Examiner, Art Unit 2894 12/27/25 /Mounir S Amer/Primary Examiner, Art Unit 2818
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Prosecution Timeline

May 23, 2022
Application Filed
Apr 19, 2025
Non-Final Rejection — §103
Jun 05, 2025
Interview Requested
Jun 12, 2025
Examiner Interview Summary
Jun 12, 2025
Applicant Interview (Telephonic)
Jul 16, 2025
Response Filed
Sep 30, 2025
Final Rejection — §103
Oct 27, 2025
Examiner Interview Summary
Oct 27, 2025
Applicant Interview (Telephonic)
Dec 02, 2025
Request for Continued Examination
Dec 10, 2025
Response after Non-Final Action
Dec 27, 2025
Non-Final Rejection — §103
Feb 19, 2026
Interview Requested
Apr 02, 2026
Response Filed

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
89%
With Interview (+12.7%)
3y 0m
Median Time to Grant
High
PTA Risk
Based on 507 resolved cases by this examiner