Prosecution Insights
Last updated: April 19, 2026
Application No. 17/751,909

FIELD TERMINATION STRUCTURE FOR MONOLITHICALLY INTEGRATED POWER SEMICONDUCTOR DEVICES

Final Rejection §103§112
Filed
May 24, 2022
Examiner
HOQUE, MOHAMMAD M
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
610 granted / 719 resolved
+16.8% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
34 currently pending
Career history
753
Total Applications
across all art units

Statute-Specific Performance

§103
51.9%
+11.9% vs TC avg
§102
27.6%
-12.4% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 719 resolved cases

Office Action

§103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. The limitation "wherein the field termination structure is devoid of trenches between adjacent ones of the power semiconductor devices”, cited in claim 1 is a negative limitation that lacks sufficient support in the specification as originally filed. Specifically, the MPEP states “The mere absence of a positive recitation is not basis for an exclusion. Any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement” (MPEP §2173.05(i)). Applicant is pointing to fig. 1, 12-23 of the specification as a support of the amendment. However, the specification doesn’t explicitly state, not to place any trench between adjacent ones of the power semiconductor devices and this absence of a positively taught connection does not provide sufficient support for the claimed scope of an open ended device that may comprise any further elements with the sole exclusion of trenches found in the cited prior art reference. This is considered an attempt to define what Applicant did not invent in contrast to what Applicant invented. For examination, the instant limitataion will be considered: Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20160020276 A1, hereinafter Lu‘276) of record. Regarding independent claim 1, Lu‘276 teaches, “A semiconductor die (fig. 1-33; ¶¶ [0006] – [0154]), comprising: a semiconductor substrate (2, 1, 8, 26, 25, fig. 3); a plurality of power semiconductor devices (101a, 101b) formed in the semiconductor substrate and sharing one or more common doped regions (1, ‘n+ drain layer’, ¶ 0105) that form a common power terminal (8, ‘drain electrode’) at a first side of the semiconductor substrate (bottom side), wherein al a second side of the semiconductor substrate (top side) opposite the first side, each power semiconductor device (101a, 101b, fig. 1) has an individual power terminal (102a, 102b) that is electrically coupled to one or more individual doped regions (¶ 0124, ‘n+ source regions’) that are isolated from the other power semiconductor devices; and a field termination structure (4, ‘A p-type JTE region’, fig. 2-4) that separates the one or more individual doped regions (source regions) of the power semiconductor devices (101a, 101b) from one another and from an edge of the semiconductor substrate, ((wherein the field termination structure comprises: a first part designed for a bidirectional electric potential gradient during operation of the power semiconductor devices and configured to prevent a space charge region that arises in one power semiconductor device from reaching an adjacent power semiconductor device under both directions of the bidirectional electric potential gradient; and a second part designed for a unidirectional electric potential gradient during operation of the power semiconductor devices and configured to prevent a space charge region that arises in one power semiconductor device from reaching an edge of the semiconductor substrate under a single direction of the unidirectional electric potential gradient, Regarding the limitataion, “wherein the field termination structure comprises: a first part designed for a bidirectional electric potential gradient during operation of the power semiconductor devices and configured to prevent a space charge region that arises in one power semiconductor device from reaching an adjacent power semiconductor device under both directions of the bidirectional electric potential gradient; and a second part designed for a unidirectional electric potential gradient during operation of the power semiconductor devices and configured to prevent a space charge region that arises in one power semiconductor device from reaching an edge of the semiconductor substrate under a single direction of the unidirectional electric potential gradient”, Lu‘276 teaches a field termination structure (4) between two semiconductor devices (101a, 101b) and any two portions of this field termination structure can be mapped to a first and a second part. But Lu‘276 are not explicit on these functionalities of the claimed device. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function alone. If the examiner has a "reason to believe" that a functional limitation can be performed inherently without modification by the prior art structure, the examiner should establish a prima facie case, and then shift the burden to the applicant to prove otherwise. See In re Swinehart, 169 USPQ 226 (CCPA 1971); In re Schreiber, 44 USPQ2d 1429 (Fed. Cir. 1997). Also, these two functionalities cited in are intended use recitation. The examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641(CCPA); In re Otto, 136 USPQ 458,459 (CCPA 1963). Further, a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2114.II. Regarding claim 3, Lu‘276 further teaches, “The semiconductor die of claim 1, wherein the plurality of power semiconductor devices are power MOSFETs (metal-oxide-semiconductor field-effect transistors}, wherein the one or more common doped regions include a common drain region (8) of a first conductivity type (n+), and wherein the one or more individual doped regions of the power semiconductor devices include a body region (3c, 3d) of a second conductivity type opposite the first conductivity type and a source region of the first conductivity type adjacent the body region”. Claims 2, 4-5 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lu‘276 as applied to claim 1 above, and further in view of KUBOUCHI et al. (US 20200395215 A1, Kubochi‘215) of record. Regarding claim 2, Lu‘276 teaches all the limitations described in claim 1. But Lu‘276 is silent upon the provision of wherein the plurality of power semiconductor devices are IGBTs (insulated gate bipolar transistors), wherein the one or more common doped regions include a common collector region of a second conductivity type, and wherein the one or more individual doped regions of the power semiconductor devices include a body region of the second conductivity type and an emitter region a first conductivity type opposite the second conductivity type adjacent the body region. However, Kubochi‘215 teaches a the plurality of power semiconductor devices are IGBTs (insulated gate bipolar transistors), wherein the one or more common doped regions include a common collector region (22, fig. 4) of a second conductivity type (P+), and wherein the one or more individual doped regions of the power semiconductor devices include a body region of the second conductivity type (14) and an emitter region (12, ¶ 0132) a first conductivity type opposite the second conductivity type adjacent the body region. Lu‘276 and Kubochi‘215 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lu‘276 with the features of Kubochi‘215 because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lu‘276 and Kubochi‘215 to include a collector region of conductivity for an IGBT according to the teachings of Kubochi‘215 as this is essential and conventional feature of an IGBT. Regarding claim 4, Lu‘276 modified with Kubochi‘215 further teaches, “The semiconductor die of claim 1, wherein between adjacent ones of the power semiconductor devices, the field termination structure comprises: a plurality of rings of the second conductivity type (44a, fig. 21 of Lu‘276 and 92 in fig. 4 of Kubochi‘215) encircling each power semiconductor device; and at least one ring of the first conductivity type (202, fig. 4, Kubochi‘215) interposed between a first group and a second group of the rings of the second conductivity type”. Regarding claim 5, Lu‘276 modified with Kubochi‘215 further teaches, “The semiconductor die of claim 4, further comprising field plates (94, fig. 4 of Kubochi‘215) above the semiconductor substrate and electrically coupled to the rings of the second conductivity type (92)”. Regarding claim 10, Lu‘276 modified with Kubochi‘215 further teaches, “The semiconductor die of claim 1, wherein between adjacent ones of the power semiconductor devices, the field termination structure comprises: a first group of rings of the second conductivity type (44a, fig. 21-22 of Lu‘276) encircling a first one of the adjacent power semiconductor devices (101a); a second group of rings of the second conductivity type (44b, fig. 21-22 of Lu‘276) encircling a second one of the adjacent power semiconductor devices (101b); a first ring of the first conductivity type (202, fig. 4 of Kubochi‘215) interposed between the rings included in the first group of rings of the second conductivity type; and a second ring of the first conductivity type (202, fig. 4 of Kubochi‘215) interposed between two rings included in the second group of rings of the second conductivity type”. Regarding claim 11, Lu‘276 modified with Kubochi‘215 further teaches, “The semiconductor die of claim 10, further comprising field plates (94, fig. 4 of Kubochi‘215) above the semiconductor substrate and electrically coupled to the rings of the second conductivity type (92)”. Regarding claim 12, Lu‘276 modified with Kubochi‘215 further teaches, “The semiconductor die of claim 11, wherein the first and second rings of the first conductivity type (202, fig. 4 of Kubochi‘215) are on opposite sides of a central region of the field termination structure, wherein a first one of the field plates (94, fig. 4 of Kubochi‘215) laterally extends towards the central region so as to at least partly extend aver the first ring of the first conductivity type (202), and wherein a second one of the field plates (94, fig. 4 of Kubochi‘215) laterally extends towards the central region so as to at least partly extend over the second ring of the first conductivity type (202)”. Regarding claim 13, Lu‘276 modified with Kubochi‘215 further teaches, “The semiconductor die of claim 12, wherein the first one of the field plates laterally extends beyond the first ring of the first conductivity type in a direction of the central region, and wherein the second one of the field plates laterally extends beyond the second ring of the first conductivity type in a direction of the central region (fig. 16B, Kubochi‘215)”. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over NISHIMURA et al. (US 20200091135 A1, hereinafter Nishimura‘135) of record. Regarding independent claim 1, Nishimura‘135 teaches, “A semiconductor die (fig. 1-29; ¶¶ [0048] – [0167]), comprising: a semiconductor substrate (SB, fig. 3); a plurality of power semiconductor devices (TR1/AR1, TR2/TR2) formed in the semiconductor substrate (SB) and sharing one or more common doped regions (3a) that form a common power terminal (11) at a first side of the semiconductor substrate (SB), wherein al a second side of the semiconductor substrate opposite the first side, each pawer semiconductor device has an individual power terminal (SE, DE etc) that is electrically coupled to one or more individual doped regions (8a, 8b, ) that are isolated from the other power semiconductor devices; and a field termination structure (AR3) that separates the one or more individual doped regions (SE, DE etc) of the power semiconductor devices (TR1/AR1, TR2/TR2) from one another and from an edge of the semiconductor substrate (SB), ((wherein the field termination structure comprises: a first part designed for a bidirectional electric potential gradient during operation of the power semiconductor devices and configured to prevent a space charge region that arises in one power semiconductor device from reaching an adjacent power semiconductor device under both directions of the bidirectional electric potential gradient; and a second part designed for a unidirectional electric potential gradient during operation of the power semiconductor devices and configured to prevent a space charge region that arises in one power semiconductor device from reaching an edge of the semiconductor substrate under a single direction of the unidirectional electric potential gradient, Regarding the limitataion, “wherein the field termination structure comprises: a first part designed for a bidirectional electric potential gradient during operation of the power semiconductor devices and configured to prevent a space charge region that arises in one power semiconductor device from reaching an adjacent power semiconductor device under both directions of the bidirectional electric potential gradient; and a second part designed for a unidirectional electric potential gradient during operation of the power semiconductor devices and configured to prevent a space charge region that arises in one power semiconductor device from reaching an edge of the semiconductor substrate under a single direction of the unidirectional electric potential gradient”, Nishimura‘135 teaches a field termination structure (AR3) between two semiconductor devices (TR1/AR1, TR2/TR2) and two portions of this field termination structure can be mapped to a first and a second part using broadest reasonable interpretation (BRI). But Nishimura‘135 are not explicit on these functionalities of the claimed device. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function alone. If the examiner has a "reason to believe" that a functional limitation can be performed inherently without modification by the prior art structure, the examiner should establish a prima facie case, and then shift the burden to the applicant to prove otherwise. See In re Swinehart, 169 USPQ 226 (CCPA 1971); In re Schreiber, 44 USPQ2d 1429 (Fed. Cir. 1997). Also, these two functionalities cited in are intended use recitation. The examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641(CCPA); In re Otto, 136 USPQ 458,459 (CCPA 1963). Further, a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2114.II. Response to Arguments Applicant’s arguments with respect to the newly amended claims have been considered but are moot because the arguments do not apply to any of the references being as used in the current rejection. Applicant argues: [Page 12] of REMARKS, the Office Action failed to identify with any specificity the alleged first and second parts of Lu's field termination structure. Examiner’s reply: Any two portions of the Lu's field termination structure can be mapped to the first and second parts of the field termination structure of Lu. Similar observation is also applied to Nishimura. Examiner’s Note The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

May 24, 2022
Application Filed
Aug 09, 2025
Non-Final Rejection — §103, §112
Oct 21, 2025
Response Filed
Feb 24, 2026
Final Rejection — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+9.3%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 719 resolved cases by this examiner. Grant probability derived from career allow rate.

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