DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1, 3, 5, 11, 12, 18 – 20, 22, 23, 27, 35, 36 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462).
With regard to claim 1, Jeon et al. disclose a thin film transistor substrate (for example, see fig. 4) comprising:
a substrate (100);
a first thin film transistor (T2) disposed on the substrate (100); and
a second thin film transistor (T1) disposed on the substrate (100),
wherein the first thin film transistor (T2) is a switching transistor (for example, column 7, lines 53, 54) includes: a first active layer (A2) having a first channel portion (C2);
a first gate insulating layer (referred to as “114A1” by examiner’s annotation shown in fig. 4 below; wherein the gate insulating portion 114A1 is made from the gate insulating layer 114) on the first active layer (A2);
a first gate electrode (G2) on the first gate insulating layer (114A1) wherein the first active layer (A2) is disposed between the first gate electrode (G2) and the substrate (100);
a first source electrode (referred to as “S2A” by examiner’s annotation shown in fig. 4 below; wherein the source electrode S2A, is an electrode portion forming via hole CNT3 and connected to a source region S2) connected to the first active layer (A2); and
a first drain electrode (referred to as “D2A” by examiner’s annotation shown in fig. 4 below; wherein the drain electrode D2A is an electrode portion forming a via hole and connected to a drain region D2) spaced apart from the first source electrode (S2A) and connected to the first active layer (A2),
wherein the second thin film transistor (T1) is a driving transistor (for example, see column 11, lines 46 – 48) includes:
a conductive material layer (BML) disposed on the substrate (100);
a first buffer layer (111) disposed above the conductive material layer (BML);
a second active layer (A1) having a second channel portion (C1) above the first buffer layer (111);
a second gate insulating layer (referred to as “114A2” by examiner’s annotation shown in fig. 4 below; wherein the gate insulating portion 114A2 is made from the gate insulating layer 114) disposed on the second active layer (A1);
a second gate electrode (G1) disposed on the second gate insulating layer (114A2);
a second source electrode (referred to as “S1A” by examiner’s annotation shown in fig. 4 below; wherein the second source electrode S1A, is an electrode portion forming via hole CNT1 and connected to a source region S1) connected to the second active layer (A1); and
a second drain electrode (referred to as “D1A” by examiner’s annotation shown in fig. 4 below; wherein the second drain electrode D1A is an electrode portion forming a via hole and connected to a drain region D1) spaced apart from the second source electrode (S1A) and connected to the second active layer (A1), wherein the conductive material layer (BML) is connected to the second source electrode (S1A) and overlaps with the second channel portion (C1);
wherein the first thin film transistor (T2) further comprises a first pad layer (an electrode DL, formed under the electrical connections, functioning as a first pad layer) disposed between the substrate (100) and the first buffer layer (111),
wherein the first pad layer (DL) and the conductive material layer (BML) are disposed on different layers (layers DL, BML located on the different areas, functioning as different layers) and do not overlap each other.
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Jeon et al. do not clearly disclose the first pad layer overlapped with the first channel wherein a distance layer between the first pad layer and the first channel portion is different from a distance between the conductive material layer and the second channel portion.
However, Gong et al. disclose the first pad layer (the layer 222 functioning as the first pad layer) overlapped with the first channel (the first channel forming in the active layer 41) wherein a distance layer (referred to as “X1” by examiner’s annotation shown in fig. 2 below) between the first pad layer (222) and the first channel portion (the first channel portion forming in a central region of the active layer 41) is different from a distance (referred to as “X2” by examiner’s annotation shown in fig. 2 below) between the conductive material layer (60) and the second channel portion (the second channel portion forming in a central region of the second active layer 21).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al.’s device to have the first pad layer overlapped with the first channel wherein a distance layer between the first pad layer and the first channel portion is different from a distance between the conductive material layer and the second channel portion as taught by Gong et al. in order to enhance a high light efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 3, Jeon et al. disclose the conductive material layer (BML), made of multi-layered metal structure, inherently has a light shielding characteristic. (for example, column 9, lines 41 – 45).
With regard to claim 5, Jeon et al. disclose the first buffer layer (111) is disposed between the substrate (100) and the first active layer (A2) and between the substrate (100) and the second active layer (A1).
With regard to claim 11, Jeon et al. disclose the first gate insulating layer (114A1) and the second gate insulating layer (114A1) have a same thickness (a thickness of the insulating layer 114).
With regard to claim 12, Jeon et al. disclose the first gate insulating layer (114A1) and the second gate insulating layer (114A1) are integrally formed (formed from the insulating layer 114).
With regard to claim 18, Gong et al. disclose the distance (X1) between the first pad layer (222) and the first channel portion (the first channel portion forming the active layer 41) is greater than the distance (X1) between the conductive material layer (60) and the second channel portion (the second channel portion forming the active layer 21).
With regard to claim 19, Jeon et al. disclose the first pad layer (DL functioning as the first pad layer) does not overlap with the second channel portion (C1).
With regard to claim 20, Jeon et al. disclose the first pad layer (DL) has conductivity, made of multi-layered metal structure, inherently has a light shielding characteristic. (for example, column 9, lines 41 – 45).
With regard to claim 22, Jeon et al. disclose a second buffer layer (110) disposed between the substrate (100) and the first buffer layer (111).
(112, or 111, 112)
With regard to claim 23, Jeon et al. disclose the conductive material layer (BML) is disposed between the first buffer layer (111) and the second buffer layer (110).
With regard to claim 27, Jeon et al. disclose the first pad layer (DL) is disposed between the first buffer layer (111) and the second buffer layer (110).
With regard to claim 35, Jeon et al. disclose a display device (for example, see fig. 4) comprising a thin film transistor substrate comprising:
a substrate (100);
a first thin film transistor (T2) disposed on the substrate (100); and
a second thin film transistor (T1) disposed on the substrate (100),
wherein the first thin film transistor (T2) is a switching transistor (for example, column 7, lines 53, 54) includes: a first active layer (A2) having a first channel portion (C2);
a first gate insulating layer (referred to as “114A1” by examiner’s annotation shown in fig. 4 below; wherein the gate insulating portion 114A1 is made from the gate insulating layer 114) on the first active layer (A2);
a first gate electrode (G2) on the first gate insulating layer (114A1) wherein the first active layer (A2) is disposed between the first gate electrode (G2) and the substrate (100);
a first source electrode (referred to as “S2A” by examiner’s annotation shown in fig. 4 below; wherein the source electrode S2A, is an electrode portion forming via hole CNT3 and connected to a source region S2) connected to the first active layer (A2); and
a first drain electrode (referred to as “D2A” by examiner’s annotation shown in fig. 4 below; wherein the drain electrode D2A is an electrode portion forming a via hole and connected to a drain region D2) spaced apart from the first source electrode (S2A) and connected to the first active layer (A2),
wherein the second thin film transistor (T1) is a driving transistor (for example, see column 11, lines 46 – 48) includes:
a conductive material layer (BML) disposed on the substrate (100);
a first buffer layer (111) disposed above the conductive material layer (BML);
a second active layer (A1) having a second channel portion (C1) above the first buffer layer (111);
a second gate insulating layer (referred to as “114A2” by examiner’s annotation shown in fig. 4 below; wherein the gate insulating portion 114A2 is made from the gate insulating layer 114) disposed on the second active layer (A1);
a second gate electrode (G1) disposed on the second gate insulating layer (114A2);
a second source electrode (referred to as “S1A” by examiner’s annotation shown in fig. 4 below; wherein the second source electrode S1A, is an electrode portion forming via hole CNT1 and connected to a source region S1) connected to the second active layer (A1); and
a second drain electrode (referred to as “D1A” by examiner’s annotation shown in fig. 4 below; wherein the second drain electrode D1A is an electrode portion forming a via hole and connected to a drain region D1) spaced apart from the second source electrode (S1A) and connected to the second active layer (A1), wherein the conductive material layer (BML) is connected to the second source electrode (S1A) and overlaps with the second channel portion (C1);
wherein the first thin film transistor (T2) further comprises a first pad layer (an electrode DL, formed under the electrical connections, functioning as a first pad layer) disposed between the substrate (100) and the first buffer layer (111),
wherein the first pad layer (DL) and the conductive material layer (BML) are disposed on different layers (layers DL, BML located on the different areas, functioning as different layers) and do not overlap each other, and a display element (OLED) connected to the second thin film transistor (T1) of the thin film transistor substrate.
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Jeon et al. do not clearly disclose the first pad layer overlapped with the first channel wherein a distance layer between the first pad layer and the first channel portion is different from a distance between the conductive material layer and the second channel portion.
However, Gong et al. disclose the first pad layer (the layer 222 functioning as the first pad layer) overlapped with the first channel (the first channel forming in the active layer 41) wherein a distance layer (referred to as “X1” by examiner’s annotation shown in fig. 2 below) between the first pad layer (222) and the first channel portion (the first channel portion forming in a central region of the active layer 41) is different from a distance (referred to as “X2” by examiner’s annotation shown in fig. 2 below) between the conductive material layer (60) and the second channel portion (the second channel portion forming in a central region of the second active layer 21).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al.’s device to have the first pad layer overlapped with the first channel wherein a distance layer between the first pad layer and the first channel portion is different from a distance between the conductive material layer and the second channel portion as taught by Gong et al. in order to enhance a high light efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 36, Jeon et al. disclose the display element (OLED) includes an organic light emitting diode.
3. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and further in view of Kang et al. (9,536,934).
With regard to claim 2, Jeon et al. and Gong et al. do not clearly disclose the second thin film transistor has an s-factor larger than that of the first thin film transistor.
However, Kang et al. disclose the second thin film transistor (1) has an s-factor larger than that of the first thin film transistor (2). (for example, see column 10, lines 38 – 40, figs. 1, 2).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al. and Gong et al.’s device to have the second thin film transistor has an s-factor larger than that of the first thin film transistor as taught by Kang et al. in order to ensure the switching thin film transistor has higher switching performance and display of grayscale for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
4. Claims 6, 7, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and further in view of Xue (11,502,752).
With regard to claims 6, 7, 33, Jeon et al. and Gong et al. do not clearly disclose the first buffer layer has a thickness of 50 nm to 300 nm, wherein the second gate insulating layer has a thickness of 0.75 times to 5 times or 1 to 3.5 times of the first buffer layer.
However, Xue discloses the first buffer layer has a thickness of 50 nm to 300 nm, wherein the second gate insulating layer has a thickness of 0.75 times to 5 times or 1 to 3.5 times of the first buffer layer. (for example, see column 10, lines 38 – 40, figs. 1, 2 disclose the buffer layer having the thickness of about 2000 Å = 200 nm, and the gate insulating layer having a thickness of about 2000 Å = 200 nm. Therefore, the second gate insulating layer has a thickness equal to a thickness of the first buffer layer, 1 time within the range of 0.75 times to 5 times or 1 to 3.5 times).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al. and Gong et al.’s device to have the buffer layer having the thickness of about 2000 Å = 200 nm, and the gate insulating layer having a thickness of about 2000 Å = 200 nm, and the second gate insulating layer has a thickness equal to a thickness of the first buffer layer as taught by Xue in order to ensure minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
5. Claims 21, 28 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and further in view of PARK et al. (2017/0162822).
With regard to claims 21, 28, Jeon et al. and Gong et al. do not clearly disclose the first pad layer is connected to the first gate electrode.
However, PARK et al. disclose the first pad layer (the conductive layer 114 functioning as the first pad layer) is connected to the first gate electrode (a gate electrode 135 functioning as the first gate electrode). (for example, see fig. 5).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al. and Gong et al.’s device to have the first pad layer is connected to the first gate electrode as taught by PARK et al. in order to securely provide a voltage to the device for enhance a high efficiency of the light emitting device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
6. Claims 31, 34 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and further in view of Yamazaki et al. (12,080,717).
With regard to claims 31, 34, Jeon et al. and Gong et al. do not clearly disclose the active layer includes: a first oxide semiconductor layer; and a second oxide semiconductor layer disposed on the first oxide semiconductor layer; a third oxide semiconductor layer disposed on the second oxide semiconductor layer.
However, Yamazaki et al. disclose the active layer includes: a first oxide semiconductor layer (199a); and a second oxide semiconductor layer (199b) disposed on the first oxide semiconductor layer (199a); a third oxide semiconductor layer (199c) disposed on the second oxide semiconductor layer (199b). (for example, fig. 20).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al. and Gong et al.’s device to have the active layer includes: a first oxide semiconductor layer; and a second oxide semiconductor layer disposed on the first oxide semiconductor layer; a third oxide semiconductor layer disposed on the second oxide semiconductor layer as taught by Yamazaki et al. in order to enhance a high efficiency of a mobility in the channel region for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claims 8, 9, 13 - 16, 29, 30 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and further in view of NOH et al. (2018/0033849).
With regard to claims 8 - 9, Jeon et al. and Gong et al. do not clearly disclose the first buffer layer disposed on the conductive material layer; and a buffer insulating layer disposed on the hydrogen blocking layer wherein the hydrogen blocking layer includes silicon nitride.
However, NOH et al. disclose the first buffer layer (111, 112) includes: a hydrogen blocking layer (an insulating layer 111, made of silicon nitride, for example, see paragraph [0103], and the same as the Applicant’s blocking layer, so the silicon nitride layer 111 functioning as a hydrogen blocking layer in order to sufficiently block hydrogen diffusion, wherein there is a large amount of hydrogen in the a-Si layer, such hydrogen may create adverse effects during the subsequent crystalizing process; for example, paragraph [0109]) disposed on (on a bottom surface) the conductive material layer (112); and a buffer insulating layer (112) disposed on the hydrogen blocking layer (111); the hydrogen blocking layer (111) includes silicon nitride.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al. and Gong et al.’s device to have the first buffer layer disposed on the conductive material layer; and a buffer insulating layer disposed on the hydrogen blocking layer wherein the hydrogen blocking layer includes silicon nitride as taught by NOH et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claims 13 - 16, Jeon et al. and Gong et al. do not clearly disclose the first gate insulating layer includes: a gate insulator; and an interface layer, wherein the interface layer having a top surface material, is disposed to be closer to the first channel portion than the gate insulator wherein the interface layer comprises silicon oxide; wherein the interface layer includes SiO2.
However, NOH et al. disclose the first gate insulating layer (114) includes: a gate insulator (the nitride film SIN, may be deposited directly on the gate insulating layer 113, functioning as a gate insulator; for example, see paragraph [0080]); and an interface layer (the oxide film SIO, may be preferably deposited on the nitride film SIN, functioning as an interface layer; for example, see paragraph [0080]), functioning as disposed on the interface layer), wherein the interface layer (the oxide film SIO) having a top surface material, is disposed to be closer to the first channel portion (the central portion forming in the first active layer 141) than the gate insulator (portion sides of the nitride film SIN); wherein the interface layer comprises silicon oxide (for example, see paragraph [0080]); wherein the interface layer (silicon oxide) inherently includes SiO2.
Applicant’s claim 14 does not distinguish over Jeon et al. and Gong et al. and NOH et al. reference regardless of the process used to form the interface layer because only the final product is relevant, not the process of making such as “a metal organic chemical vapor deposition (MOCVD) method”.
Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Fitzgerald, 205 USPQ 594, 596 (CCPA); In re Marosi et al., 218 USPQ 289 (CAFC); and most recently, In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) all of which make it clear that it is the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has burden of proof in such cases, as the above case law makes clear.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al. and Gong et al.’s device to have the first gate insulating layer includes: a gate insulator; and an interface layer, wherein the interface layer having a top surface material, is disposed to be closer to the first channel portion than the gate insulator wherein the interface layer comprises silicon oxide; wherein the interface layer includes SiO2 as taught by NOH et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claims 29, 30, Jeon et al. and Gong et al. do not clearly disclose the oxide semiconductor material includes IZO.
However, NOH et al. disclose the first active layer (141) includes an oxide semiconductor material. (for example, see paragraph [0073]) wherein the oxide semiconductor material includes IZO (for example, see paragraph [0073]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al. and Gong et al.’s device to have the oxide semiconductor material includes IZO as taught by NOH et al. in order to enhance a mobility efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
8. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and NOH et al. (2018/0033849) and further in view of Kim et al. (7,554,118).
With regard to claim 10, Jeon et al., Gong et al. and NOH et al. do not clearly disclose the hydrogen blocking layer has a thickness of 100 nm.
However, Kim et al. disclose the hydrogen blocking layer (an insulating layer 110 made of silicon nitride material, the same material as Applicant’s invention, and functioning as the hydrogen blocking layer) has a thickness of 1000 angstroms = 100 nm. (for example, see column 6, lines 18 – 19, fig. 1B).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al., Gong et al. and NOH et al.’s device to have the hydrogen blocking layer has a thickness of 100 nm as taught by Kim et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
9. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and NOH et al. (2018/0033849) and further in view of Yamazaki et al. (9,112,041).
With regard to claim 17, Jeon et al., Gong et al. and NOH et al. do not clearly disclose the interface layer has a thickness of 1 nm to 10 nm.
However, Yamazaki et al. disclose a silicon oxide film, functioning as the interface layer, has a thickness of 5 nm. (for example, see column 18, lines 33 – 40).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al., Gong et al. and NOH et al.’s device to have the interface layer has a thickness of 1 nm to 10 nm as taught by Yamazaki et al. in order to ensure minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
10. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and further in view of Sato (9,276,051).
With regard to claim 24, Jeon et al., Gong et al. do not clearly disclose the first pad layer is disposed between the substrate and the second buffer layer.
However, Sato discloses the first pad layer (171, fig. 7) is disposed between the substrate (120) and the second buffer layer (161).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al., Gong et al.’s device to have the first pad layer is disposed between the substrate and the second buffer layer as taught by Sato in order to ensure minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
11. Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (11495650) in view of Gong et al. (11817462) and Sato (9,276,051) and further in view of PARK et al. (2017/0162822).
With regard to claim 26, Jeon et al., Gong et al. and Sato do not clearly disclose the first pad layer is connected to the first gate electrode.
However, PARK et al. disclose the first pad layer (the conductive layer 114 functioning as the first pad layer) is connected to the first gate electrode (a gate electrode 135 functioning as the first gate electrode). (for example, see fig. 5).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Jeon et al., Gong et al. and Sato’s device to have the first pad layer is connected to the first gate electrode as taught by PARK et al. in order to securely provide a voltage to the device for enhance a high efficiency of the light emitting device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Response to Amendment
12. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
13. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812