DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Arguments
The portions of the claims previously subject to the 112 rejections have been amended or canceled, and those 112 rejections are withdrawn. See the new 112 rejections below.
The applicant states on page 6 that “claim 47 is amended to recite that the seed area ‘is substantially level with the selective growth mask layer,’ without referencing the geometry to an etch-back of the pedestal.” Claim 47 has in fact been amended to remove this claim language.
The applicant argues on pages 7 and 8 that the “where the source and drain regions were etched away." That the claimed “opening-bounded, above-mask growth” is not disclosed by Tang because “[t]his selective epitaxy occurs in and along source/drain cavities and sidewalls defined by STI/spacers in Tang. The regrown regions therefore occupy the recesses and are not ‘entirely above’ a top surface of a mask covering the pedestal top, or grown through an opening bounded by the mask, from a coplanar top seed as claimed.” However, Tang FIGS. 8 and 9 clearly discloses the epitaxial layer is entirely above the top surface of the growth mask. The rejection is not overcome.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 46-49, 52-56, and 60-65 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 46, 48, 54, 56, 60, 61, and 64 recite “the seed area”, which lacks antecedent basis.
The remaining claims are rejected based on their dependencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 46-48, 52, 55, 56, 60-62, and 65 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tang, US 2013/0026539, in view of Glass, US 2014/0001520, and Doyle, US 2009/0057846, and in evidence of Doornbos, US 2011/0169101.
Claim 46: Tang discloses
providing a semiconductor substrate (400);
forming a nanostructured pedestal (500) on the semiconductor substrate, the pedestal having a top surface and a side surface (FIG. 6A);
forming, at the top surface of the pedestal, the seed area wherein the seed area comprises a first material (silicon, [0028]), and is approximately coplanar with a top surface of the selective growth mask layer (FIG. 8A);
and growing a heteroepitaxial layer (900) on the seed area (top of 500), the heteroepitaxial layer comprising a second material that is different from the first material ([0048]);
and wherein the heteroepitaxial layer above the selective growth mask layer has a trapezoidal cross-sectional shape proximate to the seed area.
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Tang does not go into the details of the formation of growth mask (STI) 320. Doyle discloses:
providing a selective growth mask layer on the top surface and side surface of the pedestal (FIG. 3A);
removing a portion of the selective growth mask layer to expose the top surface of the pedestal (FIG. 3F).
It would have been obvious to have used this technique in Tang, particularly when forming a device with different fin heights, e.g., when integrating memory and logic transistors (Doyle at [0001]).
Tang does not disclose the dimensions of the seed area. However, the claimed dimensions were known in the art. See e.g. Glass, which discloses discloses that “[t]he techniques provided herein can be applied, for example, to benefit any technology nodes (e.g., 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, 14 nm, and 10 nm transistors, and lower)” ([0030]). It was known in the art that fins in finFETs were typically of the same order in size as the node used to manufacture the device. As evidence, see Doornbos at [0101], which sets forth that “a fin width of 15 nm [is] a typical value for the 22 nm node”. Those in the art would expect at least the 45 nm, 32 nm, 22 nm, 14 nm nodes, and potentially the 65 nm and 10 nm nodes, to produce fins between 10 nm and 100 nm.
Claim 47: removing a portion of the selective growth mask layer to expose the top surface of the pedestal, provides an opening bounded laterally by one or more top edges of one or more sidewalls of the selective growth mask layer (Tang FIG. 8A).
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Claim 48: the heteroepitaxial layer converges toward a point distal to the seed area (top of 900, FIG. 9A).
Claim 52: the entire heteroepitaxial layer is above a top surface of the selective growth mask layer (FIG. 9A).
Claim 55 the heteroepitaxial layer forms a portion of a transistor (Tang claim 1).
Claim 56: Tang discloses
providing a semiconductor substrate (400);
forming a nanostructured pedestal (500) on the semiconductor substrate, the pedestal having a top surface and a side surface;
forming, at the top surface of the pedestal, the seed area (FIG. 8a), wherein the seed area comprises a first material (silicon, [0028]), is approximately coplanar with the one or more top edges of the selective growth mask layer;
and growing a heteroepitaxial layer (900) on the seed area and opening, the heteroepitaxial layer comprising a second material that is different from the first material (FIG. 9A), ([0048]), wherein a portion of the heteroepitaxial layer above the selective growth mask layer has a trapezoidal cross-sectional shape extending laterally outward from the seed area and another portion of the heteroepitaxial layer above the selective growth mask layer converging inward toward a point distal to the seed area.
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Tang does not go into the details of the formation of growth mask (STI) 320. Doyle discloses:
providing a selective growth mask layer on the top surface and side surface of the pedestal (FIG. 3A);
removing a portion of the selective growth mask layer to expose the top surface of the pedestal (FIG. 3F).
It would have been obvious to have used this technique in Tang, particularly when forming a device with different fin heights, e.g., when integrating memory and logic transistors (Doyle at [0001]).
The opening of Tang is bounded laterally by one or more top edges of one or more sidewall barriers of the selective growth mask layer:
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Tang does not disclose the dimensions of the seed area. However, the claimed dimensions were known in the art. See e.g. Glass, which discloses that “[t]he techniques provided herein can be applied, for example, to benefit any technology nodes (e.g., 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, 14 nm, and 10 nm transistors, and lower)” ([0030]). It was known in the art that fins in finFETs were typically of the same order in size as the node used to manufacture the device. As evidence, see Doornbos at [0101], which sets forth that “a fin width of 15 nm [is] a typical value for the 22 nm node”. Those in the art would expect at least the 45 nm, 32 nm, 22 nm, 14 nm, and potentially the 65 nm and 10 nm nodes, to produce fins between 10 nm and 50 nm.
Claims 58 and 59: Tang discloses a process that is the same as the present claimed process in the important aspects, including use of heteroepitaxy and the size of the seed area (see the present application at [0031]). Thus those in the art would expect the same outcome, including the same defects or lack thereof. “Where, as here, the claimed and prior art products are identical or substantially identical, or are produced by identical or substantially identical processes, the PTO can require an applicant to prove that the prior art products do not necessarily or inherently possess the characteristics of his claimed product. See In re Ludtke, supra. Whether the rejection is based on ‘inherency’ under 35 USC 102, on ‘prima facie obviousness’ under 35 USC 103, jointly or alternatively, the burden of proof is the same, and its fairness is evidenced by the PTO's inability to manufacture products or to obtain and compare prior art products.” In re Best, 562 F.2d 1252,1254,195 USPQ 430, 433-434 (CCPA 1977).
Claim 60: the heteroepitaxial layer slopes outwardly proximate to the seed area (FIG. 9A).
Claim 61: the heteroepitaxial layer slopes inwardly distal from the seed area (FIG. 9A).
Claim 62: the entire heteroepitaxial layer is above a top surface of the selective growth mask layer (FIG. 9A).
Claim 65: the heteroepitaxial layer forms a portion of a transistor (Tang claim 1).
Claim 49 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tang in view of Doyle, Glass and Lai, US 2011/0079829 A1 and in evidence of Doornbos Tang does not illustrate that the selective growth mask layer is formed on at least three sides of the pedestal, including front and back sidewalls of the pedestal. Tang shows a small piece of the device. However, this feature was well-known in the art. See e.g. Lai FIGS. 1 and 2A, which shows semiconductor fins 102a and 102 surrounded on all sides by growth mask 103. This would have been the ordinary and expected arrangement for Tang and obvious as a way to form a finFET.
Claims 53, 54, 63, and 64 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tang in view of Doyle, Glass and Von Kanel, US 2013/0037857 and in evidence of Doornbos. (001) silicon substrates were by far the most common, including for epitaxy. See e.g. Von Kanel, [0010], various other paragraphs which disclose SiGe heteroepitaxy on (001) silicon. It would have been obvious to have used (001) silicon in Tang as the most common, expected, and known for use with SiGe heteroepitaxy.
Conclusion
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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