Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/4/2025 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/12/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 2/26/2026 have been fully considered but they are not persuasive. Examiner thanks Applicant for Applicant’s cooperation in the prosecution process and for Applicant’s concise analysis of the prior Office Action 12/29/2025 (Prior Office Action) found in Applicant's Remarks. The Remarks assert that:
1) Lu does not anticipate the limitations of claim 25 because Lu does not teach “one or more through silicon vias (TSVs) coupled through an empty-space region within an input/output (I/O) circuitry of the memory macro unit”
2) Lu’s disclosure teaches away from the claimed approach of claim 25.
3) Lu in view of Nautiyal fail to show macro-internal TSV placement and I/O architecture of “an input/output (1/O) circuitry of the memory macro unit, wherein the I/O circuitry comprises: one or more column multiplexers arranged in segments, each segment configured to interface with a respective sub-region of a memory array; and a shared driver segment configured to provide sense-amplifier enable, bitline precharge, and write-clock signals to the one or more column multiplexer segments” as in claim 1.
4) Lu teaches away from the architectural approaches of Nautiyal.
5) Lu in view of Law and Nautiyal fail to teach claim 19 since Law teaches TSV placement at chip, tile, or macro level for power distribution, Lu and Nautiyal fail to show macro-internal I/O-based TSV positioning logic.
6) Lu in view of Law and Nautiyal emphasize architectural approaches that steer design choices away from the claimed method.
The Manual of Patent Examining Procedure (MPEP) states that “[d]uring patent examination, the pending claims must be ‘given their broadest reasonable interpretation consistent with the specification.’” MPEP §2111 [R-5] citing Phillips v. AWH Corp., 415 F.3d 1303, 75 USPQ2d 1321 (Fed. Cir. 2005). MPEP §2171 also states that the claims of an application “define the metes and bounds of the subject matter that will be protected....”.
In regards to the first assertion, the Remarks may assert a valid interpretation of the limitation of "one or more through silicon vias (TSVs) coupled through an empty-space region within an input/output (I/O) circuitry of the memory macro unit ", Examiner respectfully submits that the interpretation asserted by the Remarks is not the broadest reasonable interpretation.
Lu teaches one or more through silicon vias (TSVs) (filled dot in fig3 and 410 in fig4, [36, 41]) coupled through an empty-space region (region with only TSV 410, fig3 and 4, [40, 41]) within an input/output (I/O) circuitry (316, YUMX and SA/WD/PD, fig3, [35]) of the memory macro unit, the empty-space region (region with 422/420 adjacent to 428/438/447/448, fig4) being disposed adjacent to at least one column multiplexer tile (YUMX, fig3) and a shared-driver region of the I/O circuitry (316 and SA/WD/PD, fig3 and 4, [35]).
Examiner respectfully submits that the broadest reasonable interpretation of the term "empty-space region" and "input/output (I/O) circuitry" includes region with only TSVs as shown in fig3 and 4 as empty-space region located within an input/output (I/O) circuitry (circuitry connect with TSV in fig4) of the memory macro unit.
In regards to the second assertion, arguments that the alleged anticipatory prior art is ‘nonanalogous art’ or ‘teaches away from the invention’ or is not recognized as solving the problem solved by the claimed invention, [are] not ‘germane’ to a rejection under section 102." Twin Disc, Inc. v. United States, 231 USPQ 417, 424 (Cl. Ct. 1986) (quoting In re Self, 671 F.2d 1344, 213 USPQ 1, 7 (CCPA 1982)). See also State Contracting & Eng’ g Corp. v. Condotte America, Inc., 346 F.3d 1057, 1068, 68 USPQ2d 1481, 1488 (Fed. Cir. 2003). The question of whether a reference is analogous art is not relevant to whether that reference anticipates. A reference may be directed to an entirely different problem than the one addressed by the inventor, or may be from an entirely different field of endeavor than that of the claimed invention, yet the reference is still anticipatory if it explicitly or inherently discloses every limitation recited in the claims.
In regards to the third assertion , an analysis that interprets each reference alone and requires each reference to teach all the limitations, i.e. both TSVs and a shared driver segment configured to provide bitline precharge, and write-clock signals to the one or more column multiplexer segments in this case, would appear to be a piecemeal analysis; and one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413,208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091,231 USPQ 375 (Fed. Cir. 1986).
Lu teaches one or more through silicon vias (TSVs) (filled dot in fig3 and 410 in fig4, [36, 41]) at least partially coupled through an input/output (I/O) circuitry (316, YUMX and SA/WD/PD, fig3, [35]) of the memory macro unit, wherein the I/O circuitry comprises: one or more column multiplexers (YUMX, fig3, [35]) arranged in segments, each segment configured to interface with a respective sub-region of a memory array (308.1-308.4 SEC, fig3, [35]); and a shared driver segment (SA, fig3 and 4, [35] ) configured to provide sense-amplifier enable ([37]). Lu does not explicitly show, a shared driver segment configured to provide bitline precharge, and write-clock signals to the one or more column multiplexer segments. Nautiyal teaches a shared driver segment (fig1) configured to provide sense-amplifier enable (110, fig1, [10]), bitline precharge (blprech, fig1, [15]), and write-clock signals (wclk, fig1, [19]) to the one or more column multiplexer segments (106, fig1, [10]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Nautiyal and Lu to form the multiplexer circuitry as in fig1 of Nautiyal in region 326 and 316 around the TSV region. The motivation to do so is to improve read and write margins and increase read and write efficiency (Nautiyal, [7]).
Lu in view of Nautiyal teaches the structural limitations of the claim; therefore, the claimed properties are inherently possessed by Lu in view of Nautiyal. When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).).
In regards to the fourth assertion, a prior art reference does not teach away from a concept if it does “not criticize, discredit, or otherwise discourage the solution claimed.” In re Fulton, 391 F.3d 1195, 1201. Lu teaches stacked memory with TSVs coupled through I/O with one or more column multiplexers (YUMX, fig3, [35]) and a shared driver segment (SA, fig3 and 4, [35] ) configured to provide sense-amplifier enable ([37]). Nautiyal teaches a shared driver segment (fig1) configured to provide sense-amplifier enable (110, fig1, [10]), bitline precharge (blprech, fig1, [15]), and write-clock signals (wclk, fig1, [19]) to the one or more column multiplexer segments (106, fig1, [10]). Nautiyal does not teach away from multiplexer circuitry with shared driver segment used in a stacked memory with TSVs coupled through I/O circuits. Nautiyal provides the motivation to modify the Shared driver segment by improve read and write margins and increase read and write efficiency (Nautiyal, [7]). While this motivation may not be exactly the same as the solution proposed by the application at hand, the rationale of the court in Kahn (In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006)) states that a different motivation can still be used to establish a prima facie case of obviousness. Combination can be met with a reasonable expectation for success since the references are related to formation of memory device. As such, Examiner respectfully submits that the there is sufficient motivation to combine Lu and Nautiyal, and that the combination of Lu and Nautiyal teaches all the limitations of claim 1. Therefore, a prima facie case of obviousness has been established, and the claims of the inventions stand properly rejected.
In regards to the fifth assertion, an analysis that interprets each reference alone and requires each reference to teach all the limitations, i.e. process flow chats, TSVs, and a shared driver segment configured to provide bitline precharge, and write-clock signals to the one or more column multiplexer segments in this case, would appear to be a piecemeal analysis; and one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413,208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091,231 USPQ 375 (Fed. Cir. 1986).
Lu teaches one or more through silicon vias (TSVs) (filled dot in fig3 and 410 in fig4, [36, 41]) located in a empty space region (region with 422/420 adjacent to 428/438/447/448, fig4) formed within an I/O block (circuitry connect with TSV in fig4). Law teaches a computer-readable storage medium (layout stored in media, [38]) comprising instructions that (fig10), when executed by a processor (processor of computer, [38]), cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs) (30/32, fig6A [30]); determining whether dimensions of a memory macro unit is greater than a size threshold ([26]), wherein the size threshold corresponds to the received user input ([26]); and determining one or more through silicon via (TSV) (30/32, fig6A [30]) positioning. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lu and Law to use the TSV placement process as in Law to design the layout of Lu. The motivation to do so is to reduce chip area usage and reduce blockage to signal routing (Law, [8]). Nautiyal teaches a shared driver segment (fig1) configured to provide sense-amplifier enable (110, fig1, [10]), bitline precharge (blprech, fig1, [15]), and write-clock signals (wclk, fig1, [19]) to the one or more column multiplexer segments (106, fig1, [10]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lu in view of Law and Nautiyal to form the multiplexer circuitry as in fig1 of Nautiyal in region 326 and 316 around the TSV region. The motivation to do so is to improve read and write margins and increase read and write efficiency (Nautiyal, [7]). Lu in view of Law and Nautiyal teaches the limitations of the claim; therefore, the claimed properties are inherently possessed by Lu in view of Law and Nautiyal.
In regards to the sixth assertion, a prior art reference does not teach away from a concept if it does “not criticize, discredit, or otherwise discourage the solution claimed.” In re Fulton, 391 F.3d 1195, 1201. Lu teaches stacked memory with TSVs coupled through I/O with one or more column multiplexers (YUMX, fig3, [35]) and a shared driver segment (SA, fig3 and 4, [35] ) configured to provide sense-amplifier enable ([37]). Nautiyal teaches a shared driver segment (fig1) configured to provide sense-amplifier enable (110, fig1, [10]), bitline precharge (blprech, fig1, [15]), and write-clock signals (wclk, fig1, [19]) to the one or more column multiplexer segments (106, fig1, [10]).
Law teaches a process flow used for TSV placement. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lu and Law to use the TSV placement process as in Law to design the layout of Lu.
Law does not teach away from using the process flow to locate the TSVs in fig3 of Lu and Nautiyal does not teach away from multiplexer circuitry with shared driver segment used in a stacked memory of Lu with TSVs coupled through I/O circuits. Law provides the motivation to reduce chip area usage and reduce blockage to signal routing (Law, [8]) and Nautiyal provides the motivation to modify the Shared driver segment by improve read and write margins and increase read and write efficiency (Nautiyal, [7]). While this motivation may not be exactly the same as the solution proposed by the application at hand, the rationale of the court in Kahn (In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006)) states that a different motivation can still be used to establish a prima facie case of obviousness. Combination can be met with a reasonable expectation for success since the references are related to formation of memory device. As such, Examiner respectfully submits that the there is sufficient motivation to combine Lu, Law and Nautiyal, and that the combination of Lu, Law and Nautiyal teaches all the limitations of claim 19. Therefore, a prima facie case of obviousness has been established, and the claims of the inventions stand properly rejected.
In light of the discussion above, Examiner respectfully submits that independent claims 1, 19 and 25 stand properly rejected and all the claims dependent on claims 1, 19 and 25 (i.e. 2-14, 20, 23-24 and 26) stand properly rejected as well. Furthermore, Examiner respectfully submits that the Remarks and Amendments have been fully considered, but found to be not persuasive. Therefore, this action is made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 25 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. US 2020/0098406.
Re claim 25, Lu teaches an integrated circuit (fig3 and 4) comprising:
a memory macro unit (TP1-3, fig3, [35]); and
one or more through silicon vias (TSVs) (filled dot in fig3 and 410 in fig4, [36, 41]) coupled through an empty-space region (region with only TSV 410, fig3 and 4, [40, 41]) within an input/output (I/O) circuitry (316, YUMX and SA/WD/PD, fig3 and 4, [35]) of the memory macro unit, the empty-space region (filled dot in fig3 and 410 in fig4, [36, 41]) being disposed adjacent to at least one column multiplexer tile (YUMX, fig3) and a shared-driver region of the I/O circuitry (316 and SA/WD/PD, fig3 and 4, [35]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14, 23-24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al .US 2020/0098406 in view of Nautiyal et al. US 2019/0325948.
Re claim 1, Lu teaches an integrated circuit (fig3) comprising:
a memory macro unit (TP1-3, fig3, [35]); and
one or more through silicon vias (TSVs) (filled dot in fig3 and 410 in fig4, [36, 41]) at least partially coupled through an input/output (I/O) circuitry (316, YUMX and SA/WD/PD, fig3 and 4, [35]) of the memory macro unit,
wherein the I/O circuitry (circuitry connected with TSVs of 420 and 422, fig4) comprises:
one or more column multiplexers (YUMX, fig3, [35]) arranged in segments, each segment configured to interface with a respective sub-region of a memory array (308.1-308.4 SEC, fig3, [35]); and
a shared driver segment (SA, fig3 and 4, [35] ) configured to provide sense-amplifier enable ([37]).
Lu does not explicitly show, a shared driver segment configured to provide bitline precharge, and write-clock signals to the one or more column multiplexer segments.
Nautiyal teaches a shared driver segment (fig1) configured to provide sense-amplifier enable (110, fig1, [10]), bitline precharge (blprech, fig1, [15]), and write-clock signals (wclk, fig1, [19]) to the one or more column multiplexer segments (106, fig1, [10]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Nautiyal and Lu to form the multiplexer circuitry as in fig1 of Nautiyal in region 326 and 316 around the TSV region of Lu. The motivation to do so is to improve read and write margins and increase read and write efficiency (Nautiyal, [7]).
Re claim 2, Lu modified above teaches the integrated circuit of claim 1, wherein one or more TSVs is coupled within the I/O circuitry of the memory macro unit (Lu, TSV in region 326, fig3 and 4).
Re claim 3, Lu modified above teaches the integrated circuit of claim 1, wherein the I/O circuitry comprises respective input/output (I/O) circuitry blocks for memory arrays of the memory macro unit (Lu, YUMX for each 308.1-308.4 SEC, fig3, [35]) .
Re claim 4, Lu modified above teaches the integrated circuit of claim 1, wherein each of the I/O circuitry comprises a region for shared: sense amplifier driver circuitry, precharge driver circuitry, and write driver control circuitry (Lu, SA in 326 and blprech and wclk as in Nautiya add in region 316 between TSVs, fig3 and 4), and wherein the shared region consolidates the driver circuitry to form an empty-space region for TSV placement (Lu, region with 422/420 adjacent to 428/438/447/448, fig4) within the I/O circuitry (Lu, circuitry connect with TSV in fig4).
Re claim 5, Lu modified above teaches the integrated circuit of claim 1, wherein the one or more TSVs are positioned vertically through and substantially perpendicular to the I/O circuitry of the memory macro unit (Lu, fig3 and 4).
Re claim 6, Lu modified above teaches the integrated circuit of claim 5, wherein the one or more TSVs are configured to transmit power, ground, I/O signals, or address pre-decoding signals (Nautiyal, fig1).
Re claim 7, Lu modified above teaches the integrated circuit of claim 1, wherein the memory macro unit comprises: one or more word-line decoder blocks (Nautiyal, ROWDEC/COLDEC in 102, fig1, [12]); one or more memory arrays (Nautiyal, 102, fig1, [12]) coupled to the one or more word-line decoder blocks; and control circuitry (Nautiyal, 104, 106, 120, 122, 110, fig1) coupled to the one or more word-line decoder blocks (Nautiyal, ROWDEC/COLDEC in 102, fig1, [12]) and the one or more memory arrays (Nautiyal, 102, fig1, [12]).
Re claim 8, Lu modified above teaches the integrated circuit of claim 7, wherein at least one of the TSVs are respectively positioned at least partially in a white-space adjacent to the control circuitry (Lu, TSV between YUMX, peripheral circuit 316 and circuit with SA, WD or PD, fig3 and 4).
Re claim 9, Lu modified above teaches the integrated circuit of claim 7, wherein a first TSV (Lu, 410.11, fig4) of the one or more TSVs (Lu, 410, fig4) is positioned vertically at least partially through a region adjacent to the control circuitry (Lu, region around 420.1 adjacent to SA, WD or PD, fig4) and at least partially through a first I/O circuitry (Lu, YUMX, fig4 and 4), wherein a second TSV (Lu, 410.12, fig4) of the one or more TSVs (Lu, 410, fig4) is positioned vertically at least partially through a region adjacent to the control circuitry (Lu, region around 420.2 adjacent to SA, WD or PD, fig4) and at least partially through a second I/O circuitry (Lu, YUMX, fig4 and 4).
Re claim 10, Lu modified above teaches the integrated circuit of claim 7, wherein a TSV of the one or more TSVs is positioned vertically through a region adjacent to a word-line decoder block and the control circuitry (Lu, TSV region adjacent to 316, with decoder, fig3 and 4).
Re claim 11, Lu modified above teaches the integrated circuit of claim 10, wherein the one or more TSVs are configured to route global signals comprising: external clock signals, internal memory clock signals, pre-decoded address signals, memory bank read output signals, or memory bank write input signals (Nautiyal, fig1).
Re claim 12, Lu modified above teaches the integrated circuit of claim 1, wherein the integrated circuit comprises two or more memory macro units, and wherein the two or more memory macro units are coupled vertically by the one or more TSVs (Lu, fig3 and 4).
Re claim 13, Lu modified above teaches the integrated circuit of claim 1, wherein the memory macro unit is folded on two or more tiers (Lu, fig4).
Re claim 14, Lu modified above teaches the integrated circuit of claim 1, wherein the integrated circuit is formed through face-to-face wafer stacking, face-to-back wafer stacking, or monolithic 3D integration (Lu, fig4).
Re claim 23, Lu modified above teaches the integrated circuit of claim 1, wherein the one or more column multiplexers and the shared driver segment (Lu, peripheral circuit, region with SA/WD/PD and YUMX formed around TSV, fig3 and 4) are arranged adjacent to a keep- out zone (KOZ) region reserved for through-silicon via (TSV) placement (Zone with only TSV 410 as in Lu fig4), and wherein the KOZ region (Lu, region with 422/420 adjacent to 428/438/447/448) is located within the I/O circuitry of the memory macro unit (Lu, circuitry connected with TSVs of 420 and 422, fig4).
Re claim 24, Lu modified above teaches the integrated circuit of claim 23, wherein the one or more column multiplexers (Lu, YUMX, fig3) are arranged into multiple segments, and the I/O circuitry (Lu, peripheral circuit, SA/WD/PD, and YUMX, fig3) further comprises selection logic configured to independently enable each segment based on a column address (Lu, fig3; Nautiyal, fig1).
Re claim 26, Lu modified above teaches the integrated circuit of claim 1, wherein the empty-space region corresponds to a keep-out-zone (KOZ) region (Lu, region with only TSV 410, fig4, [40, 41]) reserved for TSV placement within the I/O circuitry (316, YUMX and SA/WD/PD, fig3 and 4, [35]).
Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al .US 2020/0098406 in view of Nautiyal et al. US 2019/0325948 and Law et al. US 2011/0001249.
Re claim 19, Lu teaches a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including:
one or more through silicon vias (TSVs) (filled dot in fig3 and 410 in fig4, [36, 41]);
determining one or more through silicon via (TSV) (filled dot in fig3 and 410 in fig4, [36, 41]) positionings at least partially in an input/output circuitry (YUMX, peripheral circuit 316 and SA, fig3, [35]) of the memory macro unit (TP1-3, fig3, [35]) based on the determined dimensions of the memory macro unit,
wherein the I/O circuitry comprises:
one or more column multiplexers (YUMX, fig3, [35]) arranged in segments, each segment configured to interface with a respective sub-region of a memory array (308.1-308.4 SEC, fig3, [35]), and
a shared driver segment (SA, fig3 and 4, [35] ) configured to provide sense-amplifier enable ([37]).
Lu does not explicitly show receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias; determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and a shared driver segment configured to provide sense-amplifier enable, bitline precharge, and write-clock signals to the one or more column multiplexer segments.
Law teaches a computer-readable storage medium (layout stored in media, [38]) comprising instructions that (fig10), when executed by a processor (processor of computer, [38]), cause the processor to perform operations including:
receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs) (30/32, fig6A [30]);
determining whether dimensions of a memory macro unit is greater than a size threshold ([26]), wherein the size threshold corresponds to the received user input ([26]); and determining one or more through silicon via (TSV) (30/32, fig6A [30]) positioning.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lu and Law to use the TSV placement process as in Law to design the layout. The motivation to do so is to reduce chip area usage and reduce blockage to signal routing (Law, [8]).
Nautiyal teaches a shared driver segment (fig1) configured to provide sense-amplifier enable (110, fig1, [10]), bitline precharge (blprech, fig1, [15]), and write-clock signals (wclk, fig1, [19]) to the one or more column multiplexer segments (106, fig1, [10]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lu in view of Law and Nautiyal to form the multiplexer circuitry as in fig1 of Nautiyal in region 326 and 316 around the TSV region. The motivation to do so is to improve read and write margins and increase read and write efficiency (Nautiyal. [[7]).
Re claim 20, Lu modified above teaches the computer-readable storage medium of claim 19, wherein determining the TSV positionings comprises selecting a TSV location within an empty-space region (Lu, region with 422/420 adjacent to 428/438/447/448, fig4) formed by the segmented column multiplexers (YUMX, fig3, [35]) and the shared driver segment (SA, fig3 and 4, [35]), and further comprising: generating an output based on the one or more optimized TSV positionings (Law, [38]); and providing the output to an integrated circuit design tool (Law, [38]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOMING LIU/Examiner, Art Unit 2812
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