The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “the top metal pattern layer (4) and the bottom metal pattern layer (5) are electrically insulated from each other except at locations between the at least two MOSFET bare dies (2) and the several metal connection blocks (3)”, as recited in claim 1, is unclear as to how the top metal pattern layer (4) and the bottom metal pattern layer (5) can be electrically insulated from each other because the claim requires that the top metal pattern layer (4) and the bottom metal pattern layer (5) are not electrically insulated from each other (since they are not electrically insulated from each other at locations between the at least two MOSFET bare dies (2) and the several metal connection blocks (3)”.
The claimed limitation of “to isolate the MOSFET bare dies and the metal connection blocks from each other”, as recited in claim 1, is unclear as to how blocks to isolate the MOSFET bare dies and the metal connection blocks are isolated from each other, because figure 2 clearly depicts that the MOSFET bare dies 2 and the metal connection blocks 3 are electrically connected to each other via metal 4 and solder 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 11-12, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (2016/0322453) in view of Rothberg et al. (2018/0364201).Regarding claim 1, Lu et al. teach in figure 29 and related text a package structure of an embedded power module with low parasitic inductance and high heat dissipation efficiency, comprising
a top insulation layer 986, a top metal pattern layer (lead frame which includes element 921), a solder layer 945 (see element 24 in figure 3), a device layer (the entire area in the middle of device 910), a bottom metal pattern layer (lead frame which includes element 908), and a bottom insulation layer 986 sequentially arranged from top to bottom,
wherein both the top insulation layer and the bottom insulation layer have partial openings, and exposed parts of the top metal pattern layer and the bottom metal pattern layer at opening positions serve as a top electrode terminal and a bottom electrode terminal, respectively;
the device layer comprises at least two MOSFET bare dies 900 and several metal connection blocks (parts of the lead frame), and is filled with void between the MOSFET bare dies and the metal connection blocks to isolate the MOSFET bare dies and the metal connection blocks from each other; and
drain electrodes 23 (see figure 3) of the MOSFET bare dies 20 are connected with the top metal pattern layer through the solder layer, source electrodes 22 and gate electrodes of the MOSFET bare dies are electrically connected to the bottom metal pattern layer (see figure 3), respectively, and upper and lower surfaces of the metal connection blocks are electrically connected to the top metal pattern layer and the bottom metal pattern layer, respectively, and
the top metal pattern layer 921 and the bottom metal pattern layer 908 are electrically insulated from each other (in the area separating 924 and 962) except at locations between the at least two MOSFET bare dies and the several metal connection blocks.
Lu et al. do not explicitly state that the various conductive adhesives are formed of solder, and do not teach that the void is filled with insulation filler.
Lu et al. teach in figure 3 and related text that conductive adhesive 24 is formed of solder.
Rothberg et al. teach in figure 3 and related text a device layer comprises at least two MOSFET bare dies and several metal connection blocks, and is filled with insulation filler 312, 320 between the MOSFET bare dies and the metal connection blocks to isolate the MOSFET bare dies and the metal connection blocks from each other.
Lur et al. and Rothberg et al. are analogous art because they are directed to interconnect structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lur et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the various conductive adhesives of solder, and to fill the void with insulation filler, as taught by Rothberg et al., in Lur et al.’s device, in order to simplify the processing steps of making the device and in order to provide better protection to the device, respectively.
Regarding claims 2 and 3, in the combined device the insulation filler is further extended and filled between the MOSFET bare dies and the bottom metal pattern layer, and plurality of blind vias (the vertical connections in figure 29 of Lu et al.) are at intervals provided in the insulation filler between the MOSFET bare dies and the bottom metal pattern layer, and the source electrodes and the gate electrodes are electrically connected to the bottom metal pattern layer directly through the metal plating layer, respectively, and
wherein the insulation filler is further extended and filled between the metal connection blocks and the bottom metal pattern layer, and a plurality of blind vias are provided at intervals in the insulation filler between the metal connection blocks and the bottom metal pattern layer, and the metal connection blocks are electrically connected to the bottom metal pattern layer through the metal plating layer.
Prior art’s device does not teach providing a metal plating layer on an inner wall of each blind via.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to provide a metal plating layer on an inner wall of each blind via in prior art’s device in order to provide better current flow in the vias, as is well known in the art.
Regarding claim 4, Lu et al. teach in figure 29 and related text that the upper surfaces of the metal connection blocks are connected to the top metal pattern layer through the solder layer.
Regarding claim 5, Lu et al. teach in figures 3 and 29 and related text that the metal connection blocks have the same height as that of the MOSFET bare dies.
Regarding claim 6, in the combined device the insulation filler is further extended and filled to a vacant portion of the top metal pattern layer, and is connected with a lower surface of the top insulation layer; or the insulation filler is further extended and filled to a vacant portion of the bottom metal pattern layer, and is connected with an upper surface of the bottom insulation layer.
Regarding claim 7, in the combined device the top insulation layer is further extended downward and filled to a vacant portion of the top metal pattern layer, and is connected with the insulation filler in the device layer; or the bottom insulation layer is further extended upward and filled to a vacant portion of the top metal pattern layer, and is connected with the insulation filler in the device layer.
Regarding claim 8, the combined device of a power module entirely presents a multi-layer plate-like structure, and the top metal pattern layer and the bottom metal pattern layer are each substantially planar (at least part thereof).
Regarding claim 9, Lu et al. teach in figures 3 and 29 and related text that there is a plurality of top electrode terminals and bottom electrode terminals, respectively.
Regarding claim 11, Lu et al. teach in figure 29 and related text that a top surface of each of the at least two MOSFET bare dies 900 is fully in contact with the top metal pattern layer 921 via the solder layer 945.
Regarding claim 12, Lu et al. do not teach that one of the several metal connection blocks is placed centrally between the at least two MOSFET bare dies.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to place one of the several metal connection blocks centrally between the at least two MOSFET bare dies in prior art’s device in order to provide better support to the MOSFET bare dies.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (2016/0322453) and Rothberg et al. (2018/0364201), as applied to claim 1 above, and further in view of Kataoka (20220200663).
Lu et al. and Rothberg et al. teach substantially the entire claimed structure, as applied to claim 1 above, except teaching the bottom electrode terminal is configured to connect to a circuit board, and the top electrode terminal is configured to connect to a decoupling capacitor.
Kataoka teach in figure 9 and related text one side electrode terminal 110 is configured to connect to a circuit board 52, and a second side electrode terminal is configured to connect to a decoupling capacitor 54.
Kataoka, Lur et al. and Rothberg et al. are analogous art because they are directed to interconnect structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lur et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to configure the bottom electrode terminal to connect to a circuit board, and the top electrode terminal to connect to a decoupling capacitor, as taught by Kataoka, in Lur et al.’s device, in order to use the device in application which requires connections between capacitors and circuit boards.
Note that it is well known in the art to connect semiconductor devices to circuit boards.
Response to Arguments
1. Applicants argue that Lu fails to disclose the claimed metal connection blocks since structures 907 and 912 are connected to the semiconductor dies.
1. Applicants disclose in figure 2 of the present invention that the MOSFET bare dies 2 and the metal connection blocks 3 are electrically connected to each other via metal 4 and solder 6. Therefore, it is understood that structures 907 and 912 are connected to the semiconductor dies and being separated from each other by void 940.
2. Applicants argue that Lu does not teach that “the top metal pattern layer (4) and the bottom metal pattern layer (5) are electrically insulated from each other except at locations between the at least two MOSFET bare dies (2) and the several metal connection blocks (3)”, because “Lu requires direct electrical communication between the upper and lower metal structures via conductive adhesive layers”.
2. Even if Lu requires direct electrical communication between the upper and lower metal structures via conductive adhesive layers, the present invention also requires direct electrical communication between the upper and lower metal structures via conductive adhesive layers.
3. Applicants argue that Lu does not teach that plurality of blind vias because the vertical connections in figure 29 of Lu et al. cannot be plurality of blind vias.
3. It is unclear as to why the vertical connections in figure 29 of Lu et al. cannot be plurality of blind vias since Lu et al. teach plurality of said vertical connections.
4. Applicants argue that Lu does not teach that the top metal pattern layer and the bottom metal pattern layer are each substantially planar.
4. It is noted that at least part of the top metal pattern layer and part of the bottom metal pattern layer are each substantially planar.
5. Applicants argue that Lu does not teach that "a top surface of each of the at least two MOSFET bare dies (2) is fully in contact with the top metal pattern layer (4) via the solder layer (6)", because “structure 920 is spaced-apart from semiconductor die 902."
5. Figure 29 of Lu et al. depicts structure 920 is spaced-apart from semiconductor die 902 via layer 946.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
4/16/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights