DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/24/2026 has been entered.
Status of Claims
The present application is being examined under the claims filed 02/24/2026. Claims 1-19 are pending. Claims 1-19 are rejected.
Response to Arguments
I. Applicant's arguments filed 02/24/2026 have been fully considered but they are not persuasive.
II. Regarding claim 1 (and, analogously, claims 9 and 10), applicant states "there are a number of places in the Office Action where the Examiner appears to make incorrect statements relating to both the scope of the claims and what the prior art actually discloses." While applicant does not clearly specify what parts of the present claims are being compared to Naemi, in the interest of compact prosecution, examiner attempts to clarify the arguments as follows:
III. Regarding the argument that "there is no single program in Naemi in which energy decisions are included as part of the same program code as the critical operations" and "Naeimi does not teach embedding energy threshold evaluation into the instruction execution model itself."
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., "embedding energy threshold evaluation into the instruction execution model itself" (emphasis added)) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.D 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The claims require “at least one energy barrier instruction,” which comprises “a threshold energy” and is “wherein the energy barrier instruction is logically stored together with the instructions specifying the one or more operations as part of the same program code.” Under broadest reasonable interpretation, this may include any instruction that is limited by the amount of energy required to run it [i.e., a threshold energy] that is otherwise initiated within the program code for operation of the device [i.e., stored in the same location as the program code].
Naeimi Col. 14 Lines 45-50 states in a software implementation, “instruction code (software) includes energy decisions explicitly—that is, pre-existing software may be tailored to include the energy decisions” (emphasis added). For example, Naeimi Col. 15 Lines 1-5 explains an example use case of the method to “read temperatures at one millisecond (msec) intervals… If there is insufficient energy to do that, then it is acceptable to slip the temperature sensor read time until there is additional energy available,” therefore an instruction to gather a temperature reading would serve as an energy barrier instruction, as the sensing instruction is not run until there is sufficient energy available. Alternatively, the pseudocode in Naeimi Col. 15 Table 1 explicitly has a single instruction [e.g., “e.g. "if energy.available < energy.work.read_temp + volatile_queue.entries *energy.checkpoint:"] that serves as an energy barrier to the following operations, which are within the same program code.
IV. Finally, applicant argues the integration of the functionality of the controller and processor are improper because "two units being part of the same device does not equate to the units being one and the same in functional terms". Examiner respectfully disagrees.
Naeimi specifically notes in Col. 8 Lines 5-15 that the controller 176, processor 180, or related circuitry may be separate devices, or part of the same device. Furthermore, Naeimi Col. 5 Lines 33-42 teaches "a controller 176, which may include or be separate from a processor 180" and in Naeimi FIG. 1, processor 180 is shown to be a component of controller 176, and interface with other elements of data processing device 100 from within controller 176. A controller device containing the processor would comprise the functionality of both devices. There is not a meaningful distinction between controller 176 performing the tasks or the processor 180 performing the tasks, because the processor 180 is a part of controller 176.
V. Applicant’s additional arguments filed 06/26/2025 have been considered but are moot due to the new grounds of rejection, as well as the newly cited portions of the references previously presented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4-8, 10-13, 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Naeimi et. al. (US 10061376 B2) [previously cited] in view of Blumrich et. al. (US 2011/0219215 A1).
Regarding Claim 1, Naeimi discloses a computing system (Naeimi FIG. 1, data processing device 100) comprising:
a processing unit comprising a decode unit (Naeimi FIG. 1, processor 180 and controller 176 [see Col. 8 Lines 5-15, controller 176, processor 180, or related circuitry may be separate devices, or part of the same device, see response to arguments]; and Naeimi Col 8 Lines 19-22, the processor is used to perform data processing operations comprising machine-executable instructions [i.e., processor can decode instructions specifying the one or more operations]);
a program memory associated with the processing unit (Naeimi FIG. 1, processor 180 and controller 176 connected to the volatile memory (e.g., cache) 186 [i.e., program memory])); and
a power management unit (Naeimi FIG. 1, energy estimator 172);
wherein the processing unit is configured to retrieve from the program memory, decode, and execute instructions specifying one or more operations (Naeimi Col. 8 Lines 19-25, processor 180 is configured to perform a data processing operations by reading machine-executable instructions [also see Col. 24 lines 8-10, machine-readable storage [i.e., program memory] includes machine-readable instructions, that when executed, implement the method described]) and at least one energy barrier instruction (Naeimi Col. 9 lines 65-67 and Col. 10 lines 1-15, energy needs are associated with the data processing work [i.e., the operations have an energy barrier]; also see Col. 14 lines 45-52, each operation has energy cost and Col. 16 Table 2, the process is gated by energy required),
wherein the energy barrier instruction is a single instruction relating to energy usage that is logically stored together with the instructions specifying the one or more operations as part of the same program code, with the one or more operations logically following the energy barrier instruction in the code (Naeimi Col. 14 lines 45-50, if viewed as software, then instruction code (software) includes energy decisions explicitly—that is, pre-existing software may be tailored to include the energy decisions [i.e., instructions for energy decisions logically stored together with the instructions specifying the one or more operations as part of the same program code]; and Naeimi Col. 15 [Table 1], energy is checked in a single instruction [e.g. "if energy.available < energy.work.read_temp + volatile_queue.entries *energy.checkpoint:", i.e., a single instruction]), the energy barrier instruction comprises a threshold energy (Naeimi Col. 15 [Table 1], energy.avaliable [i.e., threshold] is checked before carrying out operations), and the energy barrier instruction, when executed, causes the processing unit to:
request from the power management unit a first indication that the threshold energy is currently available (Naeimi Col 6 lines 1-9, estimates are based on a measure of an existing [i.e., current] voltage of the transient energy storage 170; and Naeimi Col. 5 Lines 33-42, energy estimator 172 [i.e., power management unit] is configured to determine the expected amount of energy available 130 to the data processing device 100, and its counters are used by power management logic (e.g., a controller 176) [i.e., the power management logic requests energy availability from the power management unit]);
if the first indication is received, completely execute the one or more operations without interruption […] (Naeimi Col. 15 lines 60-66, when the device depletes its available energy, it will start the process at the top after energy becomes available again [i.e., complete execution of operations without interruption required]; and Naeimi Col. 15 lines 66-67 and Col. 16 lines 1-5, avoid reading the sensor if there is insufficient energy available to both read the sensor and checkpoint all the queue entries to avoid spending energy to collect samples, which might then be lost due to lack of energy [i.e., complete all operations after the energy barrier without interruption]); and
if the first indication is not received, enter an energy conserving mode (Naeimi Col. 10 Lines 46-52, power management strategies [i.e., modes] based on energy available include waiting [i.e., an energy conserving mode] for additional harvested energy to become available; and Naeimi Col. 15 [Table 1], sleep when there is not enough energy available).
Naeimi does not explicitly disclose:
if the first indication is received, completely execute the one or more operations without interruption in a single atomic run;
In the analogous art of scheduling instructions, Blumrich teaches:
completely execute the one or more operations without interruption in a single atomic run (Blumrich par. 44, the programmer will put instructions in a program delimiting sections in which transactional memory is desired… this may be done by marking the sections as requiring atomic execution);
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Naeimi and Blumrich before him, before the effective filing date of the claimed invention, to combine Naeimi’s energy gated operations running without interruption with Blumrich’s method for implementing atomic instructions, the motivation being to guarantee atomicity of the instructions in various systems by allowing all instructions to run without interruption (Blumrich par. 9-10, method is directed towards execution in a multiprocessor system, and in particular guaranteeing atomicity in such a system).
Regarding Claim 2, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein the processing unit is configured to, if the first indication is received, execute the one or more operations and then continue to execute instructions in the program code until the next energy barrier instruction is encountered (Naemi Col. 16 Table 2, method contains a loop in which operations are continued as long as sufficient energy is available, and operations are halted to wait for more energy if an energy barrier is encountered without sufficient energy).
Regarding Claim 4, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein the processing unit comprises one or more of a fetch unit, a load/store unit (Naeimi Col 3 lines 47-67, regarding saving program state and reloading at a later time [load/store unit required order to complete the described checkpointing functionality]), and a change of flow unit.
Regarding Claim 5, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein if the first indication is not received, the energy barrier instruction causes the processor to wait in energy conserving mode until a second indication is received that threshold energy has become available (Naeimi Col. 10 Lines 46-52, power management strategies [i.e., modes] based on energy available include waiting for additional harvested energy to become available [which is an energy conserving mode]; also see FIG 3. step 390, low power (idle mode) if expected value of available energy is less than checkpoint energy), and to exit the energy conserving mode and execute the one or more operations in response to receipt of the second indication (Naeimi Col 16 Table 2, pseudocode shows waiting for more energy in else portion of main loop [it only exits this portion of code if available energy meets energy needs; return for query of energy is an indication]; also see Naeimi Col. 15 Table 1, remain in sleep state until energy check is passed).
Regarding Claim 6, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein the power management unit (Naeimi FIG. 1, energy estimator 172) configured to receive the request from the processing unit, determine whether the threshold energy is available, and return the first or second indication when it is determined that the threshold energy is available (Naeimi Col. 5 Lines 33-42, energy estimator 172 is configured to determine the expected amount of energy available 130 to the data processing device 100, and its counters are used by power management logic; and Naeimi Col. 16 Table 2, pseudocode shows loop that determines if energy is available, do work from both queues [return for query of energy is an indication]).
Regarding Claim 7, Naeimi in view of Blumrich discloses the computing system of claim 1, comprising an energy storage unit (Naeimi FIG. 1, energy storage 170) for supplying energy to the processing unit (Naeimi Col. 7, Lines 51-59, the processor is an energy consumer for the device).
Regarding Claim 8, Naeimi in view of Blumrich discloses the computing system of claim 7, wherein determining whether the threshold energy is available by the power management unit comprises determining whether the threshold energy is present on the energy storage unit (Naeimi Col 6 Lines 4-9, energy availability estimates are based on a measure of existing voltage in energy storage 170).
Regarding Claim 10, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein the threshold energy represents an amount of energy required to execute the one or more operations (Naeimi Col. 15 lines 66-67 and Col. 16 lines 1-5, avoid reading the sensor [i.e., threshold energy for operations, see Table 1] if there is insufficient energy available to both read the sensor and checkpoint all the queue entries) or an estimate of the amount of energy required to execute the one or more operations (Naeimi FIG. 2 step 250 and Col. 10 lines 34-45, comparing the expected value of energy available and the work and checkpoint energy costs [threshold is whether or not to continue operation based on energy required]).
Regarding Claim 11, Naeimi in view of Blumrich discloses the computing system of claim 10, wherein the processing unit is configured to run the one or more operations (Naeimi Col. 8 Lines 19-25, processor 180 is configured to perform a data processing operations and machine-executable instructions [also see col. 24 lines 8-10, machine-readable storage includes machine-readable instructions, that when executed, implement a method as described herein]), to measure an amount of energy required to execute the one or more operations (Naeimi FIG. 3 steps 230 and 240, where energy required to execute the work tasks is calculated [also see col. 10 lines 1-20 on ways work energy expenditure is measured]), and to adapt the threshold energy to the amount of energy measured (Naeimi FIG. 3 step 250, method 200 includes comparing 250 the expected value of energy available and the work and checkpoint energy costs [threshold energy amount to continue operations is dictated by the work and checkpoint energy costs, which are updated after the measuring step]).
Regarding Claim 12, Naeimi in view of Blumrich discloses the computing system of claim 10, wherein the threshold energy represents an estimate of the amount of energy required to execute the one or more operations (Naeimi Col. 15 lines 26-28, e.g., work energy estimate is sub-divided and based on cost to read the temperature sensor and the energy to transmit a sample [which are operations]) and the amount of energy is determined using static code analysis (Naeimi Col. 14 lines 45-52, a practical system implementation could be designed to include energy costs explicitly; and Naeimi Col 15 Table 1, code uses explicit values for cost of operations [ex. energy.work.read_temp]; also see Col. 14 lines 45-52, each operation has energy cost; and Naeimi Col. 15 Lines 29-34, work energy counter is used to analyze the cost of performing the necessary operations in the code).
Regarding Claim 13, Naeimi in view of Blumrich discloses the computing system of claim 7, comprising a counter configured to increment every time a fixed amount of energy is added to the energy storage unit and decrement every time the fixed amount of energy is removed from the energy storage unit (Naeimi Col. 5 lines 30-42, energy estimator 172 maintains counters of available energy for the data processing device, which may be incremented or decremented when energy is added or used [also see Col. 15 lines 31-37, the work energy counter is constant i.e., fixed]).
Regarding Claim 16, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein the energy conserving mode is one or more of a state wherein memory is retained (Naeimi Col 11 lines 12-21, if there is not sufficient energy to finish a process, the process checkpointed [saved/retained] and the data processing device sleeps), a state wherein the clock is stopped (Naeimi Col. 16 Table 2, system is slept [i.e., operations are stopped] while waiting for more energy), complete shut-down of the system, and switching off of RAM.
Regarding Claim 18, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein the processing unit is a core processing unit (Naeimi Col. 17 Lines 59-62, CPU is a core).
Regarding Claim 19, Naeimi discloses a method for operating a computing system (Naeimi FIG. 3, method for selecting a power management strategy for data processing device 100).
The remainder of claim 19 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claims 3, 9, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Naeimi in view Blumrich, further in view of Elboim et. al. (US 10782772 B2) [previously cited].
Regarding Claim 3, Naeimi in view of Blumrich discloses the computing system of claim 1, processing unit comprises a register file (Naeimi FIG. 1, non-volatile memory 184 or volatile memory 186; also see Naeimi Col. 20 lines 23-31, volatile state is held in the cache and some is also held in volatile registers inside the core) [and performs algorithmic operations] (Naeimi Col. 3 lines 1-14, processor calculates incremental results).
Naeimi does not explicitly disclose:
wherein the processing unit comprises a register file and an algorithmic logic unit.
In the analogous art of power saving by calculating expected energy expenditure, Elboim discloses using a processing unit with an arithmetic logic unit (Elboim Col 3 Lines 12-16, processor core 111 may carry out the instructions of a computer program in order to perform the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions [an ALU must be present to perform the arithmetic operations]).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Naeimi, Blumrich, and Elboim before them, before the effective filing date of the claimed invention, to combine Naeimi and Blumrich’s processing unit with Elboim’s ALU, the motivation being to carry out calculations by the processor to perform the described functionality (Elboim Col 1 lines 35-46).
Regarding Claim 9, Naeimi in view of Blumrich discloses the computing system of claim 1.
Naeimi does not explicitly disclose wherein the threshold energy of the energy barrier instruction is configurable.
In the analogous art of power saving by calculating expected energy expenditure, Elboim teaches:
wherein the threshold energy of the energy barrier instruction (Elboim Col. 6 lines 59-63, processes are not executed unless enough energy is available; and Col. 5 lines 1-4, signals for execution include VSTART, VSTOP, a wake-up event, a timeout event) is configurable (Elboim Col 7 lines 5-22, VSTART signal defines a voltage level at the energy storage 120 to start an operation, and may be dynamically adjusted [i.e., configured]).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Naeimi, Blumrich, and Elboim before them, before the effective filing date of the claimed invention, to combine Naeimi and Blumrich’s system of energy provisioning with Elboim’s configurable threshold levels, the motivation being to adapt to different power consumption requirements (Elboim Col 1 lines 35-46).
Regarding Claim 17, Naeimi in view of Blumrich discloses the computing system of claim 1.
wherein the system […] compris[es] a plurality of blocks including:
the processing unit (Naeimi FIG. 1, processor 180 and controller 176 [see Col. 8 Lines 5-15, controller 176, processor 180, or related circuitry may be separate devices, or part of the same device]) and the program memory (Naeimi FIG. 1, processor 180 and controller 176 connected to the volatile memory (e.g., cache) 186 [i.e., program memory]).
Naeimi does not explicitly disclose wherein the system is a monolithic system on chip.
In the analogous art of power saving by calculating expected energy expenditure, Elboim teaches wherein the system is a monolithic system on chip (Elboim FIG. 1, SoC 100; also see claim 1, a plurality of execution functions integrated in a system on chip (SoC)) comprising a plurality of blocks including:
the processing unit (Elboim FIG. 1, MCU 100) and the program memory (Elboim FIG. 1, retention memory 140).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Naeimi, Blumrich, and Elboim before them, before the effective filing date of the claimed invention, to combine Naeimi and Blumrich’s method of energy evaluation with Elboim’s architecture, the motivation being to lower energy needs by offering multiple “execution functions” in a single device (Elboim Col. 1, Lines 27-34).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Naeimi in view Blumrich, further in view of Higgs et. al. (US 10627888 B2) [previously cited].
Regarding Claim 14, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein the energy barrier instruction […] includes the energy threshold (Naeimi Col. 9 lines 65-67 and Col. 10 lines 1-15, energy needs associated are with the instructions is the minimum energy needed to carry out work [i.e., the threshold]; and Naeimi Col. 15-16 [Tables 1-2], energy.avaliable is checked against energy needed [i.e., threshold] before carrying out operations).
Naeimi does not explicitly disclose wherein the energy barrier instruction comprises a plurality of fields, and one of the plurality of fields includes the energy threshold.
In the analogous art of optimizing power consumption in an electrical device through mode switching, Higgs teaches:
wherein the […] instruction comprises a plurality of fields (Higgs FIG. 2, wait event instruction showing fields 202-214 to store different parameters), and one of the plurality of fields includes the […] threshold (Higgs FIG. 3, sleep instructions contain parameters of operations threshold; and Higgs Col. 5 Lines 10-16, SDI field is used to control entry and exit of the power-saving state and contains additional information that the software developer would like to pass to the hardware).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Naeimi, Blumrich, and Higgs before them, before the effective filing date of the claimed invention, to combine Naeimi and Blumrich’s method for saving power by switching modes based on a threshold set for an operation with Higgs’s instruction structure, the motivation being to further optimize power consumption for a device by controlling individual parameters of operation (Higgs Col 1 lines 20-31).
Regarding Claim 15, Naeimi in view of Blumrich discloses the computing system of claim 1, wherein the energy barrier instruction […] specifies a type of the energy conserving mode (Naeimi Col. 10 Lines 46-52, power management strategies [i.e., modes] based on energy available; also see FIG 3. step 390, idle mode if expected value of available energy is less than checkpoint energy; also see Col. 16 Table 2, operations performed [i.e., mode] are changed based on amount of energy available).
Naeimi does not explicitly disclose wherein the energy barrier instruction comprises a plurality of fields, and one of the plurality of fields specifies a type of the energy conserving mode.
In the analogous art of optimizing power consumption in an electrical device through mode switching, Higgs teaches:
wherein the […] instruction comprises a plurality of fields (Higgs FIG. 2, wait event instruction showing fields 202-214 to store different parameters), and one of the plurality of fields specifies a type of the energy conserving mode (Higgs Col. 5 Lines 10-16, SDI includes bits to select options including, but not limited to, “always power save”, “never power save”, etc. [i.e., energy conserving mode]).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Naeimi, Blumrich, and Higgs before them, before the effective filing date of the claimed invention, to combine Naeimi and Blumrich’s method for saving power by switching modes with Higgs’s instruction structure, the motivation being to further optimize power consumption for a device by controlling individual parameters of operation (Higgs Col 1 lines 20-31).
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE JIAWEI WENTZEL whose telephone number is (703) 756-4762. The examiner can normally be reached 9:30am-5:30pm ET (Mon-Fri).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.J.W./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175