Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6, 8, 10, 12-15, and 17-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Su et al. (US 2023/0086999).
Regarding claim 1, Su discloses a driving substrate, comprising:
a display area (A1) and a non-display area (A2), wherein the non-display area (A2) is located on at least one side of the display area (A1) [Fig. 19], and the driving substrate comprises:
a substrate (00) [Fig. 19];
a first thin film transistor structure (100) disposed on the substrate and corresponding to the non-display area (A2), wherein the first thin film transistor structure comprises a first light shielding layer (10), a first active layer (40), a first gate electrode (20), and a first source electrode (B2/301), and a first drain electrode (B3/302), the first light shielding layer (10) is multiplexed into a second gate electrode (layers 10 and 20 are interconnected), and the first light shielding layer (10) is electrically connected to the first gate electrode (20) [Figs. 4 and 18-19];
a second thin film transistor structure (200/DR) located on the substrate and corresponding to the display area (A1), wherein the second thin film transistor structure comprises a second light shielding layer (01), a second active layer (layer below layer 02 and connected to electrodes 031 and 032), a third gate electrode (02), a second source electrode (031), and a second drain electrode (032), and the second light shielding layer (01) is electrically connected to the second source electrode (031) [Fig. 19].
Regarding claim 3, Su discloses wherein the driving substrate further comprises:
a buffer layer (60) located on a side of the first light shielding layer away from the substrate [Figs. 4 and 18-19];
a gate insulating layer (50) located on a side of the first active layer away from the buffer layer [Figs. 4 and 18-19];
an interlayer dielectric layer (70) located on a side of the first gate electrode away from the gate insulating layer, wherein the interlayer dielectric layer comprises a first via hole (K2), a second via hole (K3), a third via hole (K4), and a fourth via hole (K1) [Figs. 4 and 18-19];
wherein the first via hole (K2), the second via hole (K3), and the third via hole (K4) penetrate the interlayer dielectric layer (70), and the fourth via hole (K1)penetrates the interlayer dielectric layer (70) and the buffer layer (60), and the first source electrode (301) and the first drain electrode (302) are electrically connected to the first active layer (40) through the second via hole (K3) and the third via hole (K4), respectively [Figs. 4 and 18-19];
a connection electrode, wherein the connection electrode (B1) comprises a first connection electrode (K2), a second connection electrode (K1), and a connection part (between K2 and K1), the first connection electrode (K2) and the second connection electrode are connected by the connection part, the connection part is located on the interlayer dielectric layer (70), the first connection electrode is disposed in the first via hole (K2), and the second connection electrode is disposed in the fourth via hole (K1) [Figs. 4 and 18-19];
a passivation layer (80) located on a side of the interlayer dielectric layer away from the first gate electrode and covering the first source electrode, the first drain electrode, and the connection electrode [Figs. 4 and 18-19].
Regarding claim 4, Su discloses wherein the connection electrode (B1) and the first source electrode (B2) are disposed in a same layer [Figs. 18 and paragraph 0165].
Regarding claim 5, Su discloses wherein the driving substrate further comprises:
a third thin film transistor structure (200/SW) located on the substrate and corresponding to the display area (A1), wherein the third thin film transistor structure comprises a third active layer, a fourth gate electrode (similar to 02), a third source electrode (similar to 031), and a third drain electrode (similar to 032) [Fig. 19].
Regarding claim 6, Su discloses wherein the first light shielding layer (10) and the second light shielding layer (10) are disposed in a same layer [Fig. 19];
the first active layer (40), the second active layer (similar to 40), and the third active layer (similar to 40) are disposed in a same layer [Fig. 19];
the first gate electrode (20), the third gate electrode (similar to 20), and the fourth gate electrode (similar to 20) are disposed in a same layer [Fig. 19];
the first source electrode (B2), the first drain electrode (B3), the second source electrode (similar to B2), the second drain electrode (similar to B3), the third source electrode (similar to B2), and the third drain electrode (similar to B3) are disposed in a same layer [Fig. 19 and paragraph 0165].
Regarding claim 8, Su discloses wherein an orthographic projection of the first light shielding layer (10) on the substrate covers an orthographic projection of the first active layer (40) on the substrate [Figs. 4 and 18-19 and paragraph 0095].
Regarding claim 10, Su discloses a display panel, wherein the display panel comprises a driving substrate (00) and a light-emitting functional layer [Figs. 19-20 and paragraphs 0173-0174], the light-emitting functional layer is disposed on the driving substrate and is located in and a display area paragraphs ]0173-0174], and the driving substrate comprises:
a substrate (00) [Fig. 19];
a first thin film transistor structure (100) disposed on the substrate (00) and corresponding to a non-display area (A2), wherein the first thin film transistor structure comprises a first light shielding layer (10), a first active layer (40), a first gate electrode (20), and a first source electrode (301), and a first drain electrode (302), the first light shielding layer (10) is multiplexed into a second gate electrode (20), and the first light shielding layer (10) is electrically connected to the first gate electrode (20) [Figs. 4 and 18-19];
a second thin film transistor structure (200/DR) located on the substrate and corresponding to the display area (A1), wherein the second thin film transistor structure comprises a second light shielding layer (similar to 10), a second active layer (similar to 40), a third gate electrode (02), a second source electrode (031), and a second drain electrode (032), and the second light shielding layer is electrically connected to the second source electrode (031) [Fig. 19].
Regarding claim 12, Su discloses wherein the driving substrate further comprises:
a buffer layer (60) located on a side of the first light shielding layer away from the substrate [Figs. 4 and 18-19];
a gate insulating layer (50) located on a side of the first active layer away from the buffer layer [Figs. 4 and 18-19];
an interlayer dielectric layer (70) located on a side of the first gate electrode away from the gate insulating layer, wherein the interlayer dielectric layer comprises a first via hole (K2), a second via hole (K3), a third via hole (K4), and a fourth via hole (K1) [Figs. 4 and 18-19];
wherein the first via hole (K2), the second via hole (K3), and the third via hole (K4) penetrate the interlayer dielectric layer (70), and the fourth via hole (K1)penetrates the interlayer dielectric layer (70) and the buffer layer (60), and the first source electrode (301) and the first drain electrode (302) are electrically connected to the first active layer (40) through the second via hole (K3) and the third via hole (K4), respectively [Figs. 4 and 18-19];
a connection electrode, wherein the connection electrode (B1) comprises a first connection electrode (K2), a second connection electrode (K1), and a connection part (between K2 and K1), the first connection electrode (K2) and the second connection electrode are connected by the connection part, the connection part is located on the interlayer dielectric layer (70), the first connection electrode is disposed in the first via hole (K2), and the second connection electrode is disposed in the fourth via hole (K1) [Figs. 4 and 18-19];
a passivation layer (80) located on a side of the interlayer dielectric layer away from the first gate electrode and covering the first source electrode, the first drain electrode, and the connection electrode [Figs. 4 and 18-19].
Regarding claim 13, Su discloses wherein the connection electrode (B1) and the first source electrode (B2) are disposed in a same layer [Figs. 18 and paragraph 0165].
Regarding claim 14, Su discloses wherein the driving substrate further comprises: a third thin film transistor structure (200/SW) located on the substrate and corresponding to the display area (A1), wherein the third thin film transistor structure comprises a third active layer, a fourth gate electrode (similar to 02), a third source electrode (similar to 031), and a third drain electrode (similar to 032) [Fig. 19].
Regarding claim 15, Su discloses wherein the first light shielding layer (10) and the second light shielding layer (10) are disposed in a same layer [Fig. 19];
the first active layer (40), the second active layer (similar to 40), and the third active layer (similar to 40) are disposed in a same layer [Fig. 19];
the first gate electrode (20), the third gate electrode (similar to 20), and the fourth gate electrode (similar to 20) are disposed in a same layer [Fig. 19];
the first source electrode (B2), the first drain electrode (B3), the second source electrode (similar to B2), the second drain electrode (similar to B3), the third source electrode (similar to B2), and the third drain electrode (similar to B3) are disposed in a same layer [Fig. 19 and paragraph 0165].
Regarding claim 17, Su discloses wherein an orthographic projection of the first light shielding layer (10) on the substrate covers an orthographic projection of the first active layer (40) on the substrate [Figs. 4 and 18-19 and paragraph 0095].
Regarding claim 18, Su discloses a manufacturing method of a driving substrate, wherein the manufacturing method of the driving substrate comprises the following steps:
providing a substrate (00) [Figs. 4, 8 and 18-19];
forming a first thin film transistor structure (100) and a second thin film transistor structure (200/DR) on the substrate [Figs. 4 and 18-19],
wherein the first thin film transistor structure (100) comprises a first light shielding layer (10), a first active layer (40), a first gate electrode (20), a first source electrode (301), and a first a drain electrode (302), the first light shielding layer (40) is multiplexed into a second gate electrode (interconnected), the first light shielding layer (10) and the first gate electrode (20) are electrically connected,
the second thin film transistor structure (200/DR) comprises a second light shielding layer (similar to 10), a second active layer (similar to 40), a third gate electrode (02), a second source electrode (031), and a second drain electrode (032), and the second light shielding layer (similar to 10) and the second source electrode (031) are electrically connected [Fig. 19].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 7, 9, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 2023/0086999) in view of Huang (CN 104977764), cited by Applicant.
Regarding claims 2 and 11, Su discloses wherein the first light shielding layer (10) is located on the substrate (00), and the driving substrate further comprises:
a buffer layer (60) located on a side of the first light shielding layer away from the substrate [Figs. 4 and 18-19];
a gate insulating layer (50) located on a side of the first active layer away from the buffer layer and covering the first active layer, wherein the gate insulating layer comprises a first via hole (K1) and the first via hole penetrates the buffer layer (60) [Figs. 4 and 18-19],
a connection electrode (B1) disposed in the first via hole [Figs. 4 and 18-19];
an interlayer dielectric layer (70) located on a side of the first gate electrode away from the gate insulating layer, wherein the interlayer dielectric layer comprises a second via hole (K3) and a third via hole (K4) [Figs. 4 and 18-19];
wherein the second via hole (K3) and the third via hole (K4) penetrates the interlayer dielectric layer (70), and the first source electrode and the first drain electrode (301/302) are electrically connected to the first active layer (40) through the second via hole and the third via hole (K3/K4), respectively [Figs. 4 and 18-19];
a passivation layer (80) located on a side of the interlayer dielectric layer away from the first gate electrode [Figs. 4 and 18-19].
However, Sue does not disclose the first via hole penetrating the gate insulating layer and the buffer layer.
Huang teaches a shielding layer (302), a gate electrode (306), and a first via hole penetrating the gate insulating layer (305) and the buffer layer (303) and connecting the gate electrode (306) to the shielding layer (304) [Fig. 3].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Su by including the first via hole connection as taught by Huang because it helps to enhance the thin film transistor and the current driving capability, and improve the display quality [See Abstract].
Regarding claims 7 and 16, Su teaches that the pixel circuit 200 includes a plurality of second transistors [paragraphs 0168-0171]. In addition, the court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 9, Su does not teach the material used to form the first, second and third active layers. However, metal oxide as the material of choice for active layers is conventional in the art. The court has held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960); Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Allowable Subject Matter
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Jose R Diaz/Primary Examiner, Art Unit 2815