DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The IDS filed on 03/10/2023 and 10/24/2025 have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Array substrate including an active layer comprising a first semiconductor and two second semiconductors, method of manufacturing array substrate, and display panel.
Claim Objections
Claim 11 is objected to because of the following informalities:
In claim 11, lines 7-8, “forming an active layer by making the two second semiconductors in contact with two ends of the first semiconductor respectively” should be change to --forming an active layer by making the second semiconductor in contact with the opposite ends of the first semiconductor respectively--. In order to improve clarity and provide proper antecedent basis.
In claim 11, lines 8-9, “the first semiconductor layer” should be change to --the first semiconductor-- for consistency to “a first semiconductor” as defined in claim 11, line 4.
In claim 11, lines 10-11, “the second semiconductor layer” should be change to --the second semiconductor-- for consistency to “a second semiconductor” as defined in claim 11, line 6.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-11, 13-15, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guo et al. (U.S. Pub. 2016/0343780).
In re claim 1, Guo discloses an array substrate, comprising a substrate 100 (see paragraph [0036] and fig. 5) and a driving transistor layer arranged on the substrate; wherein the driving transistor layer comprises at least one driving transistor 32 (see paragraph [0030] and fig. 5), each of the driving transistors 32 comprise: a gate electrode 15 (see paragraph [0036] and fig. 5); an active layer arranged opposite to a position of the gate electrode, the active layer comprising a first semiconductor 132 and two second semiconductors 131, the two second semiconductors 131 are arranged at opposite ends of the first semiconductor 132 and are respectively in contact with the first semiconductor 132 to form a first PN junction and a second PN junction (see paragraph [0030] and fig. 5, note that, Guo discloses that the first semiconductor (intermediate doped portion) 132 is a N-type semiconductor whereas the second semiconductors (side doped potions) 131 are P-type semiconductor, the first semiconductor 132 can also be an P-type semiconductor whereas the second semiconductors 131 are N-type semiconductor, see paragraph [0030]), and a conduction direction of the first PN junction and a conduction direction of the second PN junction are inverse; and a source drain layer arranged opposite to a position of the active layer, the source drain layer comprising a source electrode and a drain electrode 17, the source electrode is connected with the second semiconductor 131 at a position of the first PN junction, and the drain electrode being connected with the second semiconductor 131 at a position of the second PN junction (see paragraph [0036] and fig. 5).
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In re claim 2, as applied to claim 1 above, Guo discloses wherein the active layer is an NPN type semiconductor, the second semiconductor 131 is an N-type semiconductor layer, and the first semiconductor 132 is a P-type semiconductor layer (see paragraph [0030] and fig. 5, note that Guo discloses that the second semiconductor (side doped portions) 131 can be an N-type semiconductor whereas the first semiconductor (intermediate doped portion) 132 can be a P-type semiconductor).
In re claim 3, as applied to claim 1 above, Guo discloses wherein the active layer is a PNP type semiconductor, the first semiconductor 132 is an N-type semiconductor layer, and the second semiconductor 131 is a P-type semiconductor layer (see paragraph [0030] and fig. 5, note that Guo discloses that the first semiconductor (intermediate doped portion) 132 can be an N-type semiconductor and the second semiconductor (side doped portions) 131 can be a P-type semiconductor).
In re claim 6, as applied to claim 1 above, Guo discloses wherein the first semiconductor 132 comprises a channel region, and orthographic projections of two of the second semiconductors 131 on the substrate 100 are located on both sides of an orthographic projection of the channel region on the substrate 100 (see paragraph [0030] and fig. 5).
In re claim 7, as applied to claim 1 above, Guo discloses wherein the first semiconductor 132 comprises two end surfaces and a first surface connected with the two end surfaces, the first surface is facing away from the substrate 100, the two end surfaces are respectively located at opposite ends of the first surface, and one of the second semiconductors 131 is attached to a corresponding one of the end surfaces and/or the first surface (see paragraph [0030] and fig. 5).
In re claim 8, as applied to claim 2 above, Guo discloses wherein the first semiconductor 132 comprises two end surfaces and a first surface connected with the two end surfaces, the first surface is facing away from the substrate 100, the two end surfaces are respectively located at opposite ends of the first surface, and one of the second semiconductors 131 is attached to a corresponding one of the end surfaces and/or the first surface (see paragraph [0030] and fig. 5).
In re claim 9, as applied to claim 3 above, Guo discloses wherein the first semiconductor 132 comprises two end surfaces and a first surface connected with the two end surfaces, the first surface is facing away from the substrate 100, the two end surfaces are respectively located at opposite ends of the first surface, and one of the second semiconductors 131 is attached to a corresponding one of the end surfaces and/or the first surface (see paragraph [0030] and fig. 5).
In re claim 10, as applied to claim 1 above, Guo discloses wherein the driving transistor layer further comprises a gate insulating layer 14, a first protective layer 16, and a second protective layer 18, the gate insulating layer 14 is arranged on the substrate 100 and covers the gate electrode 15, the active layer (131,132) is arranged on the gate insulating layer 14, the first protective layer 16 covers the active layer (131,132) and is arranged on the gate insulating layer 14, and the second protective layer 18 covers the source drain layer 17 (see paragraphs [0031], [0032] and fig. 5).
In re claim 11, Guo discloses a method for manufacturing an array substrate, wherein the method comprises: providing a substrate 100 (see paragraph [0031] and figs. 1-5); forming a gate electrode 15 (see paragraph [0031] and fig. 5), a gate insulating layer 14 (see paragraph [0031] and fig. 5), and a first semiconductor 132 on the substrate 100 (see paragraph [0030] and fig. 5); wherein the gate insulating layer 14 covers the gate electrode 15, and the gate insulating layer 14 is located between the gate electrode 15 and the first semiconductor 132 (see paragraphs [0030], [0031] and fig. 5); forming a second semiconductor 131 at both opposite ends of the first semiconductor 132 respectively, and forming an active layer by making the two second semiconductors 131 in contact with two ends of the first semiconductor 131 respectively; the first semiconductor layer 132 is one of an N-type semiconductor and a P-type semiconductor, and the second semiconductor layer 131 is other one of the P-type semiconductor and the N-type semiconductor (see paragraph [0030] and fig. 5, note that, Guo discloses that the first semiconductor (intermediate doped portion) 132 is a N-type semiconductor whereas the second semiconductors (side doped potions) 131 are P-type semiconductor, the first semiconductor 132 can also be an P-type semiconductor whereas the second semiconductors 131 are N-type semiconductor, see paragraph [0030]); forming a source drain layer 17 on the active layer and electrically connecting a source electrode and a drain electrode of the source drain layer 17 with the two second semiconductors 131 respectively (see paragraph [0031] and fig. 5).
In re claim 13, Guo discloses a display panel, wherein the display panel comprises an array substrate and an opposite substrate, and the array substrate is arranged at an interval relative with the opposite substrate; the array substrate comprises a substrate 100 (see paragraph [0030] and fig. 5) and a driving transistor layer formed on the substrate 100; wherein the driving transistor layer comprises at least one driving transistor 32 (see paragraph [0030] and fig. 5), each of the driving transistors 32 comprise: a gate electrode 15 (see paragraph [0031] and fig. 5); an active layer (131,132) arranged opposite to a position of the gate electrode 15, the active layer comprising a first semiconductor 132 and two second semiconductors 131, the two second semiconductors 131 are arranged at opposite ends of the first semiconductor 132 and are respectively in contact with the first semiconductor 131 to form a first PN junction and a second PN junction, and a conduction direction of the first PN junction and a conduction direction of the second PN junction are inverse (see paragraph [0030] and fig. 5, note that, Guo discloses that the first semiconductor (intermediate doped portion) 132 is a N-type semiconductor whereas the second semiconductors (side doped potions) 131 are P-type semiconductor, the first semiconductor 132 can also be an P-type semiconductor whereas the second semiconductors 131 are N-type semiconductor, see paragraph [0030]); and a source drain layer 17 arranged opposite to a position of the active layer, the source drain layer 17 comprising a source electrode and a drain electrode, the source electrode is connected with the second semiconductor 131 at a position of the first PN junction, and the drain electrode being connected with the second semiconductor 131 at a position of the second PN junction (see paragraph [0031] and figs. 1-5).
In re claim 14, as applied to claim 13, Guo discloses wherein the active layer is an NPN type semiconductor, the second semiconductor 131 is an N-type semiconductor layer, and the first semiconductor 132 is a P-type semiconductor layer (see paragraph [0030] and fig. 5, note that Guo discloses that the second semiconductor (side doped portions) 131 can be an N-type semiconductor whereas the first semiconductor (intermediate doped portion) 132 can be a P-type semiconductor).
In re claim 15, as applied to claim 13 above, Guo discloses wherein the active layer is a PNP type semiconductor, the first semiconductor 132 is an N-type semiconductor layer, and the second semiconductor 131 is a P-type semiconductor layer (see paragraph [0030] and fig. 5, note that Guo discloses that the first semiconductor (intermediate doped portion) 132 can be an N-type semiconductor and the second semiconductor (side doped portions) 131 can be a P-type semiconductor).
In re claim 18, as applied to claim 13 above, Guo discloses wherein the first semiconductor 132 comprises a channel region, and orthographic projections of two of the second semiconductors 131 on the substrate 100 are located on both sides of an orthographic projection of the channel region on the substrate 100 (see paragraph [0030] and fig. 5).
In re claim 19, as applied to claim 13 above, Guo discloses wherein the first semiconductor 132 comprises two end surfaces and a first surface connected with the two end surfaces, the first surface is facing away from the substrate 100, the two end surfaces are respectively located at opposite ends of the first surface, and one of the second semiconductors 131 is attached to a corresponding one of the end surfaces and/or the first surface (see paragraph [0030] and fig. 5).
In re claim 20, as applied to claim 13 above, Guo discloses wherein the driving transistor layer further comprises a gate insulating layer 14 (see paragraph [0031] and fig. 5), a first protective layer 16 (see paragraph [0031] and fig. 5), and a second protective layer 18 (see paragraph [0032] and fig. 5), the gate insulating layer 14 is arranged on the substrate 100 and covers the gate electrode 15, the active layer (131,132) is arranged on the gate insulating layer 14, the first protective layer 16 covers the active layer and is arranged on the gate insulating layer 14, and the second protective layer 18 covers the source drain layer 17 (see paragraphs [0031], [0032] and fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (U.S. Pub. 2016/0343780), as applied to claims 2, 3, 14, and 15 above, and further in view of Lee et al. (U.S. Pub. 2008/0283828).
In re claims 4, 5, 16, and 17, as applied to claims 2, 3, 14, and 15 above, respectively, Guo is silent to wherein a material of the N-type semiconductor layer is an N-type inorganic semiconductor material, and a material of the P-type semiconductor layer is a P-type organic semiconductor material.
However, Lee discloses in a same field of endeavor, an array substrate, including, inter-alia, an active layer comprising a material of the N-type semiconductor layer is an N-type inorganic semiconductor material, and a material of the P-type semiconductor layer is a P-type organic semiconductor material (see paragraph [0009]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Lee into the array substrate of Guo in order to enable wherein a material of the N-type semiconductor layer is an N-type inorganic semiconductor material, and a material of the P-type semiconductor layer is a P-type organic semiconductor material in Guo to be formed in order to improve characteristics of the display device. Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (U.S. Pub. 2016/0343780), as applied to claim 11 above, and further in view of Noh et al. (U.S. Pub. 2013/0005079).
In re claim 12, as applied to claim 11 above, Guo is silent to wherein the first semiconductor and/or the second semiconductors is/are formed by evaporation or solution coating method.
However, Noh discloses in a same field of endeavor, an array substrate, including, inter-alia, wherein the first semiconductor 131 and/or the second semiconductors is/are formed by evaporation or solution coating method (see paragraph [0053]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Noh into the array substrate of Guo in order to enable wherein the first semiconductor and/or the second semiconductors is/are formed by evaporation or solution coating method in Guo to be performed because Noh suggested these techniques are well-known in the rat for forming active layer of the display device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Abe et al. (U.S. Pub. 2014/0353648) discloses an array substrate, comprising a substrate 21 and a driving transistor layer arranged on the substrate 21; wherein the driving transistor layer comprises at least one driving transistor, each of the driving transistors comprise: a gate electrode 26; an active layer 22 arranged opposite to a position of the gate electrode 26, the active layer 22 comprising a semiconductor material; and a source drain layer arranged opposite to a position of the active layer, the source drain layer comprising a source electrode 23 and a drain electrode 24, the source electrode 23 and the drain electrode 24 is connected to the active layer 22 (see paragraphs [0232], [0233] and fig. 9).
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/KHIEM D NGUYEN/ Primary Examiner, Art Unit 2892
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