DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4. 7, 11-14 and 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KO (US 20210193838).
Regarding claim 1, KO discloses an array substrate, comprising:
a substrate (substrate 600, see fig 6, para 198);
a first active layer disposed on the substrate (fig 6, 622, para 256), wherein the first active layer comprises a first channel portion (622 is a channel region, see fig 6, para 156);
a first gate electrode (gate electrode 635, see fig 6, para 133) disposed on the first active layer, wherein the first gate electrode is disposed opposite to the first channel portion (635 is on the opposite side of 630 from 622, see fig 6);
a second active layer (fig 6, 652, para 178) disposed on the first gate electrode, wherein the second active layer comprises a second channel portion (652 is a second channel region, see fig 6, para 178); and
a second gate electrode (fig 6, 665, para 133) disposed on the second active layer, wherein the second gate electrode is disposed opposite to the second channel portion (665 is on the opposite side of 660 from 652, see fig 6);
wherein the first active layer and the second active layer are connected in parallel (652 and 622 are connected in parallel by the conductors in H1 and H2, see fig 6, para 182), and wherein the first channel portion and the second channel portion are provided separately (622 and 652 are separate from each other, see fig 6).
Regarding claim 2, KO discloses the array substrate according to claim 1, wherein
the first active layer further comprises first conductor portions (conductive portions 624 and 623, see fig 6, para 179) positioned on both sides of the first channel portion, and wherein the second active layer further comprises second conductor portions (conductive portions 651 and 653, see fig 6, para 179) positioned on both sides of the second channel portion;
wherein the first conductor portions and the second conductor portions are electrically connected (651 is directly connected to 621 and 653 is directly connected to 623, see fig 6).
Regarding claim 3, KO discloses the array substrate according to claim 2, wherein the array substrate further comprises:
an interlayer insulating layer (fig 6, 640, para 160) disposed on the first active layer, wherein the interlayer insulating layer comprises a plurality of first through holes (holes H1 and H2, see fig 6, para 182), and
wherein each of the first through holes expose part of the first conductor portion (H1 and H2 expose parts of 621 and 623, see fig 6); wherein the second active layer is disposed on the interlayer insulating layer (652 is disposed on 640, see fig 6), the second conductor portion overlaps inner walls of the first through holes (651 and 653 overlap along a vertical direction with sidewalls of H1 and H2, see fig 6), and wherein the second conductor portions are connected to the first conductor portions through the first through holes (651 is connected to 621 by H1 and 653 is connected to 623 by H2, see fig 6).
Regarding claim 4, KO discloses the array substrate according to claim 3, wherein the array substrate further comprises:
a passivation layer (fig 6, 670, para 183) disposed on the interlayer insulating layer and covering the second gate electrode (670 covers 665, see fig 6), wherein the passivation layer comprises a plurality of second through holes (holes H3 and H4, see fig 6, para 187), and wherein each of the second through holes expose part of the second conductor portion (H3 exposes 651 and H4 exposes 653, see fig 6).
Regarding claim 7, KO discloses the array substrate according to claim 2, wherein a length of the first channel portion is less than a length of the second channel portion (because the 2nd channel 650 includes the diagonals it will have a longer length that 620 which is straight, see fig 6).
Regarding claim 11, KO discloses a method of manufacturing an array substrate, comprising:
providing a substrate (substrate 600, see fig 6, para 198);
forming a first active layer (fig 6, 622, para 256) on the substrate;
forming a first gate electrode (gate electrode 635, see fig 6, para 133) on the first active layer, wherein the first gate electrode is disposed opposite to a first channel portion of the first active layer (635 is on the opposite side of 630 from 622, see fig 6);
forming a second active layer (fig 6, 652, para 178) on the first gate electrode, wherein the first active layer and the second active layer are connected in parallel (652 and 622 are connected in parallel by the conductors in H1 and H2, see fig 6, para 182), and
wherein the first channel portion and a second channel portion of the second active layer are provided separately (622 and 652 are separate from each other, see fig 6); and
forming a second gate electrode on the second active layer (fig 6, 665, para 133), and wherein the second gate electrode is disposed oppositely to the second channel portion (665 is on the opposite side of 660 from 652, see fig 6).
Regarding claim 12, KO discloses a display panel, wherein
the display panel comprises an array substrate (the device can be an array substrate, see fig 2, which will include 600, see fig 2 and 5-6, para 2 and 132) and a light-emitting member (the OLED, see fig 3, para 91) positioned on one side of the array substrate, and
wherein the array substrate and the light-emitting member are combined into one (see para 129), and
wherein the array substrate comprises:
a substrate (substrate 600, see fig 6, para 198);
a first active layer disposed on the substrate (fig 6, 622, para 256), wherein the first active layer comprises a first channel portion (622 is a channel region, see fig 6, para 156);
a first gate electrode (gate electrode 635, see fig 6, para 133) disposed on the first active layer, wherein the first gate electrode is disposed opposite to the first channel portion (635 is on the opposite side of 630 from 622, see fig 6);
a second active layer (fig 6, 652, para 178) disposed on the first gate electrode, wherein the second active layer comprises a second channel portion (652 is a second channel region, see fig 6, para 178); and
a second gate electrode (fig 6, 665, para 133) disposed on the second active layer, wherein the second gate electrode is disposed opposite to the second channel portion (665 is on the opposite side of 660 from 652, see fig 6);
wherein the first active layer and the second active layer are connected in parallel (652 and 622 are connected in parallel by the conductors in H1 and H2, see fig 6, para 182), and
wherein the first channel portion and the second channel portion are provided separately (622 and 652 are separate from each other, see fig 6).
Regarding claim 13, KO discloses the display panel according to claim 12, wherein the first active layer further comprises
first conductor portions (conductive portions 624 and 623, see fig 6, para 179) positioned on both sides of the first channel portion, and wherein the second active layer further comprises second conductor portions (conductive portions 651 and 653, see fig 6, para 179) positioned on both sides of the second channel portion;
wherein the first conductor portions and the second conductor portions are electrically connected (651 is directly connected to 621 and 653 is directly connected to 623, see fig 6).
Regarding claim 14, KO discloses the display panel according to claim 13, wherein the array substrate further comprises:
an interlayer insulating layer (fig 6, 640, para 160) disposed on the first active layer, wherein the interlayer insulating layer comprises a plurality of first through holes (holes H1 and H2, see fig 6, para 182), and wherein each of the first through holes expose part of the first conductor portion (H1 and H2 expose parts of 621 and 623, see fig 6);
wherein the second active layer is disposed on the interlayer insulating layer (652 is disposed on 640, see fig 6), the second conductor portion overlaps inner walls of the first through holes (651 and 653 overlap along a vertical direction with sidewalls of H1 and H2, see fig 6), and wherein the second conductor portions are connected to the first conductor portions through the first through holes (651 is connected to 621 by H1 and 653 is connected to 623 by H2, see fig 6); and
a passivation layer (fig 6, 670, para 183) disposed on the interlayer insulating layer and covering the second gate electrode (670 covers 665, see fig 6), wherein the passivation layer comprises a plurality of second through holes (holes H3 and H4, see fig 6, para 187), and wherein each of the second through holes expose part of the second conductor portion (H3 exposes 651 and H4 exposes 653, see fig 6).
Regarding claim 17, KO discloses the display panel according to claim 15, wherein an orthographic projection of the first channel portion on the source electrode is positioned in the source electrode in a plan view direction of the array substrate (5 and 3 overlap along the vertical direction, see fig 2).
The display panel according to claim 13, wherein a length of the first channel portion is less than a length of the second channel portion (because the 2nd channel 650 includes the diagonals it will have a longer length that 620 which is straight, see fig 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over KO (US 20210193838) in view of SHI (US 20180190812).
Regarding claim 5, KO discloses the array substrate according to claim 2.
KO fails to explicitly disclose a device, wherein the array substrate further comprises:
a source and drain layer disposed between the substrate and the first active layer, wherein the source and drain layer comprises a source electrode and a drain electrode which are separately disposed, and wherein the source electrode and the drain electrode are respectively electrically connected to the first conductor portion on both sides of the first active layer.
SHI teaches a device, wherein the array substrate further comprises:
a source (fig 2, 5, para 4) and drain (fig 2, 4, para 4) layer disposed between the substrate and the first active layer (4 and 5 are between substrate 18 and active layer 3, see fig 2, para 36), wherein the source and drain layer comprises a source electrode (fig 2, 5, para 4) and a drain electrode (fig 2, 4, para 4) which are separately disposed (4 and 5 are separate, see fig 2), and wherein the source electrode and the drain electrode are respectively electrically connected to the first conductor portion on both sides of the first active layer (4 and 5 are connected to end portions of 3 which are heavily doped, see fig 2, para 36).
KO and SHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the source and drain electrodes of SHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the source and drain electrodes of SHI in order to improve the yield of the array substrate (see SHI para 58).
Regarding claim 6, KO discloses the array substrate according to claim 5.
KO fails to explicitly disclose a device, wherein an orthographic projection of the first channel portion on the source electrode is positioned in the source electrode in a plan view direction of the array substrate.
SHI teaches a device, wherein an orthographic projection of the first channel portion on the source electrode is positioned in the source electrode in a plan view direction of the array substrate (5 and 3 overlap along the vertical direction, see fig 2).
KO and SHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the source and drain electrodes of SHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the source and drain electrodes of SHI in order to improve the yield of the array substrate (see SHI para 58).
Regarding claim 15, KO discloses the display panel according to claim 13.
KO fails to explicitly disclose a device, wherein the array substrate further comprises:
a source and drain layer disposed between the substrate and the first active layer, wherein the source and drain layer comprises a source electrode and a drain electrode which are separately disposed, and
wherein the source electrode and the drain electrode are respectively electrically connected to the first conductor portion on both sides of the first active layer.
SHI teaches a device, wherein the array substrate further comprises:
a source (fig 2, 5, para 4) and drain (fig 2, 4, para 4) layer disposed between the substrate and the first active layer (4 and 5 are between substrate 18 and active layer 3, see fig 2, para 36), wherein the source and drain layer comprises a source electrode (fig 2, 5, para 4) and a drain electrode (fig 2, 4, para 4) which are separately disposed (4 and 5 are separate, see fig 2), and
wherein the source electrode and the drain electrode are respectively electrically connected to the first conductor portion on both sides of the first active layer (4 and 5 are connected to end portions of 3 which are heavily doped, see fig 2, para 36).
KO and SHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the source and drain electrodes of SHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the source and drain electrodes of SHI in order to improve the yield of the array substrate (see SHI para 58).
Regarding claim 16, KO discloses the display panel according to claim 15.
KO fails to explicitly disclose a device, wherein an orthographic projection of the first channel portion on the source electrode is positioned in the source electrode in a plan view direction of the array substrate.
SHI teaches a device, wherein an orthographic projection of the first channel portion on the source electrode is positioned in the source electrode in a plan view direction of the array substrate (5 and 3 overlap along the vertical direction, see fig 2).
KO and SHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the source and drain electrodes of SHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the source and drain electrodes of SHI in order to improve the yield of the array substrate (see SHI para 58).
Claim(s) 8 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over KO (US 20210193838) in view of CHEN (US 20170301701).
Regarding claim 8, KO discloses the array substrate according to claim 2.
KO fails to explicitly disclose a device, wherein a mass ratio of oxygen elements in the first channel portion is less than a mass ratio of oxygen elements in the second channel portion.
CHEN teaches a device, wherein a mass ratio of oxygen elements in the first channel portion is less than a mass ratio of oxygen elements in the second channel portion (first channel 120 can be Si and second channel region 160 can be IGZO which has a higher oxygen concentration than Si, see fig 2, para 20).
KO and CHEN are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the channel composition of CHEN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the channel composition of CHEN in order to have a device with high electron mobility and low leakage current (see CHEN para 21).
Regarding claim 18, KO discloses the display panel according to claim 13.
KO fails to explicitly disclose a device, wherein a mass ratio of oxygen elements in the first channel portion is less than a mass ratio of oxygen elements in the second channel portion.
CHEN teaches a device, wherein a mass ratio of oxygen elements in the first channel portion is less than a mass ratio of oxygen elements in the second channel portion (first channel 120 can be Si and second channel region 160 can be IGZO which has a higher oxygen concentration than Si, see fig 2, para 20).
KO and CHEN are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the channel composition of CHEN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the channel composition of CHEN in order to have a device with high electron mobility and low leakage current (see CHEN para 21).
Claim(s) 9-10 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KO (US 20210193838) in view of NODA (US 20120248432).
Regarding claim 9, KO discloses the array substrate according to claim 2.
KO fails to explicitly disclose a device, wherein the first channel portion comprises a first sub-channel on a side of the first channel portion close to the substrate and a second sub-channel on a side of first channel portion away from the substrate, and wherein a mass ratio of a narrow band gap elements in the first sub-channel is greater than a mass ratio of a narrow band gap elements in the second sub-channel.
NODA teaches a device, wherein the first channel portion comprises a first sub-channel on a side of the first channel portion close to the substrate (131, which is closer to the substrate 1011 than 132, see fig 2B, para 91) and a second sub-channel on a side of first channel portion away from the substrate (132, which is farther way from 101 than 131, see fig 2B, para 91), and wherein a mass ratio of a narrow band gap elements in the first sub-channel is greater than a mass ratio of a narrow band gap elements in the second sub-channel (131 can have a higher In concentration than 132, see fig 2B, para 91).
KO and NODA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the channel composition of NODA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the channel composition of NODA in order to suppress gate leakage current (see NODA para 91).
Regarding claim 10, KO discloses the array substrate according to claim 9.
KO fails to explicitly disclose a device, wherein the mass ratio of the narrow bandgap elements in the first channel portion gradually decreases in a direction from the substrate to the first active layer.
NODA teaches a device, wherein the mass ratio of the narrow bandgap elements in the first channel portion gradually decreases in a direction from the substrate to the first active layer (the indium concentration in the film thickness direction is a gradient, see para 21).
KO and NODA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the channel composition of NODA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the channel composition of NODA in order to suppress gate leakage current (see NODA para 91).
Regarding claim 19, KO discloses the display panel according to claim 13.
KO fails to explicitly disclose a device, wherein the first channel portion comprises a first sub-channel on a side of the first channel portion close to the substrate and a second sub-channel on a side of the first channel portion away from the substrate, and wherein a mass ratio of a narrow band gap elements in the first sub-channel is greater than a mass ratio of a narrow band gap elements in the second sub-channel.
NODA teaches a device, wherein the first channel portion comprises a first sub-channel on a side of the first channel portion close to the substrate (131, which is closer to the substrate 1011 than 132, see fig 2B, para 91) and a second sub-channel on a side of first channel portion away from the substrate (132, which is farther way from 101 than 131, see fig 2B, para 91), and wherein a mass ratio of a narrow band gap elements in the first sub-channel is greater than a mass ratio of a narrow band gap elements in the second sub-channel (131 can have a higher In concentration than 132, see fig 2B, para 91).
KO and NODA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the channel composition of NODA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the channel composition of NODA in order to suppress gate leakage current (see NODA para 91).
Regarding claim 20, KO discloses the display panel according to claim 19.
KO fails to explicitly disclose a device, wherein the mass ratio of the narrow bandgap elements in the first channel portion gradually decreases in a direction from the substrate to the first active layer.
NODA teaches a device, wherein the mass ratio of the narrow bandgap elements in the first channel portion gradually decreases in a direction from the substrate to the first active layer (the indium concentration in the film thickness direction is a gradient, see para 21).
KO and NODA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KO with the channel composition of NODA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KO with the channel composition of NODA in order to suppress gate leakage current (see NODA para 91).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811